1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
24 #include <linux/string_choices.h>
25
26 #include "realtek.h"
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
29 #include "rtl83xx.h"
30 #include "rtl8366rb.h"
31
32 /* Switch Global Configuration register */
33 #define RTL8366RB_SGCR 0x0000
34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
35 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
40 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)
41 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
42 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
43
44 /* Port Enable Control register */
45 #define RTL8366RB_PECR 0x0001
46
47 /* Switch per-port learning disablement register */
48 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002
49
50 /* Security control, actually aging register */
51 #define RTL8366RB_SECURITY_CTRL 0x0003
52
53 #define RTL8366RB_SSCR2 0x0004
54 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
55
56 /* Port Mode Control registers */
57 #define RTL8366RB_PMC0 0x0005
58 #define RTL8366RB_PMC0_SPI BIT(0)
59 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)
60 #define RTL8366RB_PMC0_PROBE BIT(2)
61 #define RTL8366RB_PMC0_DIS_BISR BIT(3)
62 #define RTL8366RB_PMC0_ADCTEST BIT(4)
63 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5)
64 #define RTL8366RB_PMC0_EN_SCAN BIT(6)
65 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7
66 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)
67 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10
68 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)
69 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13
70 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)
71 #define RTL8366RB_PMC1 0x0006
72
73 /* Port Mirror Control Register */
74 #define RTL8366RB_PMCR 0x0007
75 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
76 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
77 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
78 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
79 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
80 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
81 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
82 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
83
84 /* bits 0..7 = port 0, bits 8..15 = port 1 */
85 #define RTL8366RB_PAACR0 0x0010
86 /* bits 0..7 = port 2, bits 8..15 = port 3 */
87 #define RTL8366RB_PAACR1 0x0011
88 /* bits 0..7 = port 4, bits 8..15 = port 5 */
89 #define RTL8366RB_PAACR2 0x0012
90 #define RTL8366RB_PAACR_SPEED_10M 0
91 #define RTL8366RB_PAACR_SPEED_100M 1
92 #define RTL8366RB_PAACR_SPEED_1000M 2
93 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
94 #define RTL8366RB_PAACR_LINK_UP BIT(4)
95 #define RTL8366RB_PAACR_TX_PAUSE BIT(5)
96 #define RTL8366RB_PAACR_RX_PAUSE BIT(6)
97 #define RTL8366RB_PAACR_AN BIT(7)
98
99 /* bits 0..7 = port 0, bits 8..15 = port 1 */
100 #define RTL8366RB_PSTAT0 0x0014
101 /* bits 0..7 = port 2, bits 8..15 = port 3 */
102 #define RTL8366RB_PSTAT1 0x0015
103 /* bits 0..7 = port 4, bits 8..15 = port 5 */
104 #define RTL8366RB_PSTAT2 0x0016
105
106 #define RTL8366RB_POWER_SAVING_REG 0x0021
107
108 /* Spanning tree status (STP) control, two bits per port per FID */
109 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */
110 #define RTL8366RB_STP_STATE_DISABLED 0x0
111 #define RTL8366RB_STP_STATE_BLOCKING 0x1
112 #define RTL8366RB_STP_STATE_LEARNING 0x2
113 #define RTL8366RB_STP_STATE_FORWARDING 0x3
114 #define RTL8366RB_STP_MASK GENMASK(1, 0)
115 #define RTL8366RB_STP_STATE(port, state) \
116 ((state) << ((port) * 2))
117 #define RTL8366RB_STP_STATE_MASK(port) \
118 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
119
120 /* CPU port control reg */
121 #define RTL8366RB_CPU_CTRL_REG 0x0061
122 #define RTL8366RB_CPU_PORTS_MSK 0x00FF
123 /* Disables inserting custom tag length/type 0x8899 */
124 #define RTL8366RB_CPU_NO_TAG BIT(15)
125 #define RTL8366RB_CPU_TAG_SIZE 4
126
127 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
128 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
129 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
130
131 #define RTL8366RB_RESET_CTRL_REG 0x0100
132 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
133 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
134
135 #define RTL8366RB_CHIP_ID_REG 0x0509
136 #define RTL8366RB_CHIP_ID_8366 0x5937
137 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
138 #define RTL8366RB_CHIP_VERSION_MASK 0xf
139
140 /* PHY registers control */
141 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
142 #define RTL8366RB_PHY_CTRL_READ BIT(0)
143 #define RTL8366RB_PHY_CTRL_WRITE 0
144 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
145 #define RTL8366RB_PHY_INT_BUSY BIT(0)
146 #define RTL8366RB_PHY_EXT_BUSY BIT(4)
147 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
148 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
149 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
150 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
151
152 #define RTL8366RB_PHY_REG_MASK 0x1f
153 #define RTL8366RB_PHY_PAGE_OFFSET 5
154 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
155 #define RTL8366RB_PHY_NO_OFFSET 9
156 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
157
158 /* VLAN Ingress Control Register 1, one bit per port.
159 * bit 0 .. 5 will make the switch drop ingress frames without
160 * VID such as untagged or priority-tagged frames for respective
161 * port.
162 * bit 6 .. 11 will make the switch drop ingress frames carrying
163 * a C-tag with VID != 0 for respective port.
164 */
165 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E
166 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
167
168 /* VLAN Ingress Control Register 2, one bit per port.
169 * bit0 .. bit5 will make the switch drop all ingress frames with
170 * a VLAN classification that does not include the port is in its
171 * member set.
172 */
173 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
174
175 #define RTL8366RB_MIB_COUNT 33
176 #define RTL8366RB_GLOBAL_MIB_COUNT 1
177 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
178 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
179 #define RTL8366RB_MIB_CTRL_REG 0x13F0
180 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
181 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
182 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
183 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
184 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
185
186 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
187 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
188 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
189 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
190 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
191
192 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
193 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
194
195 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
196 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
197 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
198
199 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
200
201 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
202 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
203 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
204 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
205 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
206 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
207 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
208
209 #define RTL8366RB_NUM_VLANS 16
210 #define RTL8366RB_NUM_VIDS 4096
211 #define RTL8366RB_PRIORITYMAX 7
212 #define RTL8366RB_NUM_FIDS 8
213 #define RTL8366RB_FIDMAX 7
214
215 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
216 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
217 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
218 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
219 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
220
221 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
222
223 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
224 RTL8366RB_PORT_2 | \
225 RTL8366RB_PORT_3 | \
226 RTL8366RB_PORT_4 | \
227 RTL8366RB_PORT_5 | \
228 RTL8366RB_PORT_CPU)
229
230 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
231 RTL8366RB_PORT_2 | \
232 RTL8366RB_PORT_3 | \
233 RTL8366RB_PORT_4 | \
234 RTL8366RB_PORT_5)
235
236 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
237 RTL8366RB_PORT_2 | \
238 RTL8366RB_PORT_3 | \
239 RTL8366RB_PORT_4)
240
241 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
242
243 /* First configuration word per member config, VID and prio */
244 #define RTL8366RB_VLAN_VID_MASK 0xfff
245 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
246 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
247 /* Second configuration word per member config, member and untagged */
248 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
249 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
250 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
251 /* Third config word per member config, STAG currently unused */
252 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
253 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
254 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
255 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
256 #define RTL8366RB_VLAN_FID_MASK 0x7
257
258 /* Port ingress bandwidth control */
259 #define RTL8366RB_IB_BASE 0x0200
260 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
261 #define RTL8366RB_IB_BDTH_MASK 0x3fff
262 #define RTL8366RB_IB_PREIFG BIT(14)
263
264 /* Port egress bandwidth control */
265 #define RTL8366RB_EB_BASE 0x02d1
266 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
267 #define RTL8366RB_EB_BDTH_MASK 0x3fff
268 #define RTL8366RB_EB_PREIFG_REG 0x02f8
269 #define RTL8366RB_EB_PREIFG BIT(9)
270
271 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
272 #define RTL8366RB_BDTH_UNIT 64
273 #define RTL8366RB_BDTH_REG_DEFAULT 16383
274
275 /* QOS */
276 #define RTL8366RB_QOS BIT(15)
277 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
278 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
279
280 /* Interrupt handling */
281 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
282 #define RTL8366RB_INTERRUPT_POLARITY BIT(0)
283 #define RTL8366RB_P4_RGMII_LED BIT(2)
284 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441
285 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
286 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
287 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
288 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
289 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
290 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
291 RTL8366RB_INTERRUPT_ACLEXCEED | \
292 RTL8366RB_INTERRUPT_STORMEXCEED | \
293 RTL8366RB_INTERRUPT_P4_FIBER | \
294 RTL8366RB_INTERRUPT_P4_UTP)
295 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
296 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
297
298 /* Port isolation registers */
299 #define RTL8366RB_PORT_ISO_BASE 0x0F08
300 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))
301 #define RTL8366RB_PORT_ISO_EN BIT(0)
302 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)
303 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
304
305 /* bits 0..5 enable force when cleared */
306 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
307
308 #define RTL8366RB_OAM_PARSER_REG 0x0F14
309 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
310
311 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51
312 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007
313 #define RTL8366RB_GREEN_FEATURE_TX BIT(0)
314 #define RTL8366RB_GREEN_FEATURE_RX BIT(2)
315
316 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
317 { 0, 0, 4, "IfInOctets" },
318 { 0, 4, 4, "EtherStatsOctets" },
319 { 0, 8, 2, "EtherStatsUnderSizePkts" },
320 { 0, 10, 2, "EtherFragments" },
321 { 0, 12, 2, "EtherStatsPkts64Octets" },
322 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
323 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
324 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
325 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
326 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
327 { 0, 24, 2, "EtherOversizeStats" },
328 { 0, 26, 2, "EtherStatsJabbers" },
329 { 0, 28, 2, "IfInUcastPkts" },
330 { 0, 30, 2, "EtherStatsMulticastPkts" },
331 { 0, 32, 2, "EtherStatsBroadcastPkts" },
332 { 0, 34, 2, "EtherStatsDropEvents" },
333 { 0, 36, 2, "Dot3StatsFCSErrors" },
334 { 0, 38, 2, "Dot3StatsSymbolErrors" },
335 { 0, 40, 2, "Dot3InPauseFrames" },
336 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
337 { 0, 44, 4, "IfOutOctets" },
338 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
339 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
340 { 0, 52, 2, "Dot3sDeferredTransmissions" },
341 { 0, 54, 2, "Dot3StatsLateCollisions" },
342 { 0, 56, 2, "EtherStatsCollisions" },
343 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
344 { 0, 60, 2, "Dot3OutPauseFrames" },
345 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
346 { 0, 64, 2, "Dot1dTpPortInDiscards" },
347 { 0, 66, 2, "IfOutUcastPkts" },
348 { 0, 68, 2, "IfOutMulticastPkts" },
349 { 0, 70, 2, "IfOutBroadcastPkts" },
350 };
351
rtl8366rb_get_mib_counter(struct realtek_priv * priv,int port,struct rtl8366_mib_counter * mib,u64 * mibvalue)352 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
353 int port,
354 struct rtl8366_mib_counter *mib,
355 u64 *mibvalue)
356 {
357 u32 addr, val;
358 int ret;
359 int i;
360
361 addr = RTL8366RB_MIB_COUNTER_BASE +
362 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
363 mib->offset;
364
365 /* Writing access counter address first
366 * then ASIC will prepare 64bits counter wait for being retrived
367 */
368 ret = regmap_write(priv->map, addr, 0); /* Write whatever */
369 if (ret)
370 return ret;
371
372 /* Read MIB control register */
373 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
374 if (ret)
375 return -EIO;
376
377 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
378 return -EBUSY;
379
380 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
381 return -EIO;
382
383 /* Read each individual MIB 16 bits at the time */
384 *mibvalue = 0;
385 for (i = mib->length; i > 0; i--) {
386 ret = regmap_read(priv->map, addr + (i - 1), &val);
387 if (ret)
388 return ret;
389 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
390 }
391 return 0;
392 }
393
rtl8366rb_get_irqmask(struct irq_data * d)394 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
395 {
396 int line = irqd_to_hwirq(d);
397 u32 val;
398
399 /* For line interrupts we combine link down in bits
400 * 6..11 with link up in bits 0..5 into one interrupt.
401 */
402 if (line < 12)
403 val = BIT(line) | BIT(line + 6);
404 else
405 val = BIT(line);
406 return val;
407 }
408
rtl8366rb_mask_irq(struct irq_data * d)409 static void rtl8366rb_mask_irq(struct irq_data *d)
410 {
411 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
412 int ret;
413
414 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
415 rtl8366rb_get_irqmask(d), 0);
416 if (ret)
417 dev_err(priv->dev, "could not mask IRQ\n");
418 }
419
rtl8366rb_unmask_irq(struct irq_data * d)420 static void rtl8366rb_unmask_irq(struct irq_data *d)
421 {
422 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
423 int ret;
424
425 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
426 rtl8366rb_get_irqmask(d),
427 rtl8366rb_get_irqmask(d));
428 if (ret)
429 dev_err(priv->dev, "could not unmask IRQ\n");
430 }
431
rtl8366rb_irq(int irq,void * data)432 static irqreturn_t rtl8366rb_irq(int irq, void *data)
433 {
434 struct realtek_priv *priv = data;
435 u32 stat;
436 int ret;
437
438 /* This clears the IRQ status register */
439 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
440 &stat);
441 if (ret) {
442 dev_err(priv->dev, "can't read interrupt status\n");
443 return IRQ_NONE;
444 }
445 stat &= RTL8366RB_INTERRUPT_VALID;
446 if (!stat)
447 return IRQ_NONE;
448 while (stat) {
449 int line = __ffs(stat);
450 int child_irq;
451
452 stat &= ~BIT(line);
453 /* For line interrupts we combine link down in bits
454 * 6..11 with link up in bits 0..5 into one interrupt.
455 */
456 if (line < 12 && line > 5)
457 line -= 5;
458 child_irq = irq_find_mapping(priv->irqdomain, line);
459 handle_nested_irq(child_irq);
460 }
461 return IRQ_HANDLED;
462 }
463
464 static struct irq_chip rtl8366rb_irq_chip = {
465 .name = "RTL8366RB",
466 .irq_mask = rtl8366rb_mask_irq,
467 .irq_unmask = rtl8366rb_unmask_irq,
468 };
469
rtl8366rb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)470 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
471 irq_hw_number_t hwirq)
472 {
473 irq_set_chip_data(irq, domain->host_data);
474 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
475 irq_set_nested_thread(irq, 1);
476 irq_set_noprobe(irq);
477
478 return 0;
479 }
480
rtl8366rb_irq_unmap(struct irq_domain * d,unsigned int irq)481 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
482 {
483 irq_set_nested_thread(irq, 0);
484 irq_set_chip_and_handler(irq, NULL, NULL);
485 irq_set_chip_data(irq, NULL);
486 }
487
488 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
489 .map = rtl8366rb_irq_map,
490 .unmap = rtl8366rb_irq_unmap,
491 .xlate = irq_domain_xlate_onecell,
492 };
493
rtl8366rb_setup_cascaded_irq(struct realtek_priv * priv)494 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
495 {
496 struct device_node *intc;
497 unsigned long irq_trig;
498 int irq;
499 int ret;
500 u32 val;
501 int i;
502
503 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
504 if (!intc) {
505 dev_err(priv->dev, "missing child interrupt-controller node\n");
506 return -EINVAL;
507 }
508 /* RB8366RB IRQs cascade off this one */
509 irq = of_irq_get(intc, 0);
510 if (irq <= 0) {
511 dev_err(priv->dev, "failed to get parent IRQ\n");
512 ret = irq ? irq : -EINVAL;
513 goto out_put_node;
514 }
515
516 /* This clears the IRQ status register */
517 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
518 &val);
519 if (ret) {
520 dev_err(priv->dev, "can't read interrupt status\n");
521 goto out_put_node;
522 }
523
524 /* Fetch IRQ edge information from the descriptor */
525 irq_trig = irq_get_trigger_type(irq);
526 switch (irq_trig) {
527 case IRQF_TRIGGER_RISING:
528 case IRQF_TRIGGER_HIGH:
529 dev_info(priv->dev, "active high/rising IRQ\n");
530 val = 0;
531 break;
532 case IRQF_TRIGGER_FALLING:
533 case IRQF_TRIGGER_LOW:
534 dev_info(priv->dev, "active low/falling IRQ\n");
535 val = RTL8366RB_INTERRUPT_POLARITY;
536 break;
537 }
538 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
539 RTL8366RB_INTERRUPT_POLARITY,
540 val);
541 if (ret) {
542 dev_err(priv->dev, "could not configure IRQ polarity\n");
543 goto out_put_node;
544 }
545
546 ret = devm_request_threaded_irq(priv->dev, irq, NULL,
547 rtl8366rb_irq, IRQF_ONESHOT,
548 "RTL8366RB", priv);
549 if (ret) {
550 dev_err(priv->dev, "unable to request irq: %d\n", ret);
551 goto out_put_node;
552 }
553 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), RTL8366RB_NUM_INTERRUPT,
554 &rtl8366rb_irqdomain_ops, priv);
555 if (!priv->irqdomain) {
556 dev_err(priv->dev, "failed to create IRQ domain\n");
557 ret = -EINVAL;
558 goto out_put_node;
559 }
560 for (i = 0; i < priv->num_ports; i++)
561 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
562
563 out_put_node:
564 of_node_put(intc);
565 return ret;
566 }
567
rtl8366rb_set_addr(struct realtek_priv * priv)568 static int rtl8366rb_set_addr(struct realtek_priv *priv)
569 {
570 u8 addr[ETH_ALEN];
571 u16 val;
572 int ret;
573
574 eth_random_addr(addr);
575
576 dev_info(priv->dev, "set MAC: %pM\n", addr);
577 val = addr[0] << 8 | addr[1];
578 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
579 if (ret)
580 return ret;
581 val = addr[2] << 8 | addr[3];
582 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
583 if (ret)
584 return ret;
585 val = addr[4] << 8 | addr[5];
586 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
587 if (ret)
588 return ret;
589
590 return 0;
591 }
592
593 /* Found in a vendor driver */
594
595 /* Struct for handling the jam tables' entries */
596 struct rtl8366rb_jam_tbl_entry {
597 u16 reg;
598 u16 val;
599 };
600
601 /* For the "version 0" early silicon, appear in most source releases */
602 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
603 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
604 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
605 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
606 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
607 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
608 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
609 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
610 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
611 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
612 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
613 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
614 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
615 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
616 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
617 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
618 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
619 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
620 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
621 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
622 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
623 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
624 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
625 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
626 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
627 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
628 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
629 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
630 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
631 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
632 };
633
634 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
635 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
636 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
637 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
638 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
639 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
640 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
641 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
642 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
643 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
644 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
645 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
646 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
647 };
648
649 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
650 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
651 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
652 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
653 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
654 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
655 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
656 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
657 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
658 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
659 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
660 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
661 {0xBE00, 0x1340}, {0x0F51, 0x0010},
662 };
663
664 /* Appears in a DDWRT code dump */
665 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
666 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
667 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
668 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
669 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
670 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
671 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
672 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
673 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
674 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
675 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
676 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
677 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
678 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
679 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
680 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
681 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
682 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
683 };
684
685 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
686 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
687 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
688 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
689 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
690 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
691 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
692 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
693 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
694 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
695 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
696 };
697
698 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
699 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
700 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
701 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
702 {0x0401, 0x0000}, {0x0431, 0x0960},
703 };
704
705 /* This jam table activates "green ethernet", which means low power mode
706 * and is claimed to detect the cable length and not use more power than
707 * necessary, and the ports should enter power saving mode 10 seconds after
708 * a cable is disconnected. Seems to always be the same.
709 */
710 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
711 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
712 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
713 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
714 };
715
716 /* Function that jams the tables in the proper registers */
rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry * jam_table,int jam_size,struct realtek_priv * priv,bool write_dbg)717 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
718 int jam_size, struct realtek_priv *priv,
719 bool write_dbg)
720 {
721 u32 val;
722 int ret;
723 int i;
724
725 for (i = 0; i < jam_size; i++) {
726 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
727 ret = regmap_read(priv->map,
728 RTL8366RB_PHY_ACCESS_BUSY_REG,
729 &val);
730 if (ret)
731 return ret;
732 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
733 ret = regmap_write(priv->map,
734 RTL8366RB_PHY_ACCESS_CTRL_REG,
735 RTL8366RB_PHY_CTRL_WRITE);
736 if (ret)
737 return ret;
738 }
739 }
740 if (write_dbg)
741 dev_dbg(priv->dev, "jam %04x into register %04x\n",
742 jam_table[i].val,
743 jam_table[i].reg);
744 ret = regmap_write(priv->map,
745 jam_table[i].reg,
746 jam_table[i].val);
747 if (ret)
748 return ret;
749 }
750 return 0;
751 }
752
753 /* This code is used also with LEDs disabled */
rb8366rb_set_ledgroup_mode(struct realtek_priv * priv,u8 led_group,enum rtl8366_ledgroup_mode mode)754 int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,
755 u8 led_group,
756 enum rtl8366_ledgroup_mode mode)
757 {
758 int ret;
759 u32 val;
760
761 val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);
762
763 ret = regmap_update_bits(priv->map,
764 RTL8366RB_LED_CTRL_REG,
765 RTL8366RB_LED_CTRL_MASK(led_group),
766 val);
767 if (ret)
768 return ret;
769
770 return 0;
771 }
772
773 /* This code is used also with LEDs disabled */
rtl8366rb_setup_all_leds_off(struct realtek_priv * priv)774 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)
775 {
776 int ret = 0;
777 int i;
778
779 regmap_update_bits(priv->map,
780 RTL8366RB_INTERRUPT_CONTROL_REG,
781 RTL8366RB_P4_RGMII_LED,
782 0);
783
784 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
785 ret = rb8366rb_set_ledgroup_mode(priv, i,
786 RTL8366RB_LEDGROUP_OFF);
787 if (ret)
788 return ret;
789 }
790
791 return ret;
792 }
793
rtl8366rb_port_set_isolation(struct realtek_priv * priv,int port,u32 mask)794 static int rtl8366rb_port_set_isolation(struct realtek_priv *priv, int port,
795 u32 mask)
796 {
797 /* Bit 0 enables isolation, the mask indicates allowed forwarding
798 * ports
799 */
800 mask = RTL8366RB_PORT_ISO_PORTS(mask) | RTL8366RB_PORT_ISO_EN;
801
802 return regmap_write(priv->map, RTL8366RB_PORT_ISO(port),
803 mask);
804 }
805
rtl8366rb_port_add_isolation(struct realtek_priv * priv,int port,u32 mask)806 static int rtl8366rb_port_add_isolation(struct realtek_priv *priv, int port,
807 u32 mask)
808 {
809 /* We assume isolation bit is on */
810 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
811 RTL8366RB_PORT_ISO_PORTS(mask),
812 RTL8366RB_PORT_ISO_PORTS(mask));
813 }
814
rtl8366rb_port_remove_isolation(struct realtek_priv * priv,int port,u32 mask)815 static int rtl8366rb_port_remove_isolation(struct realtek_priv *priv, int port,
816 u32 mask)
817 {
818 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
819 RTL8366RB_PORT_ISO_PORTS(mask), 0);
820 }
821
822 static void
rtl8366rb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)823 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
824 {
825 struct realtek_priv *priv = ds->priv;
826 u32 val;
827 int i;
828
829 switch (state) {
830 case BR_STATE_DISABLED:
831 val = RTL8366RB_STP_STATE_DISABLED;
832 break;
833 case BR_STATE_BLOCKING:
834 case BR_STATE_LISTENING:
835 val = RTL8366RB_STP_STATE_BLOCKING;
836 break;
837 case BR_STATE_LEARNING:
838 val = RTL8366RB_STP_STATE_LEARNING;
839 break;
840 case BR_STATE_FORWARDING:
841 val = RTL8366RB_STP_STATE_FORWARDING;
842 break;
843 default:
844 dev_err(priv->dev, "unknown bridge state requested\n");
845 return;
846 }
847
848 /* Set the same status for the port on all the FIDs */
849 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
850 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
851 RTL8366RB_STP_STATE_MASK(port),
852 RTL8366RB_STP_STATE(port, val));
853 }
854 }
855
rtl8366rb_port_set_learning(struct realtek_priv * priv,int port,bool enable)856 static int rtl8366rb_port_set_learning(struct realtek_priv *priv, int port,
857 bool enable)
858 {
859 /* Notice inverted semantics in this register: setting a bit disables
860 * learning instead of enabling it.
861 */
862 return regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
863 BIT(port), enable ? 0 : BIT(port));
864 }
865
rtl8366rb_setup(struct dsa_switch * ds)866 static int rtl8366rb_setup(struct dsa_switch *ds)
867 {
868 struct realtek_priv *priv = ds->priv;
869 const struct rtl8366rb_jam_tbl_entry *jam_table;
870 u32 downports_mask = 0;
871 struct rtl8366rb *rb;
872 u32 upports_mask = 0;
873 struct dsa_port *dp;
874 u32 chip_ver = 0;
875 u32 chip_id = 0;
876 int jam_size;
877 int ret;
878 int i;
879
880 rb = priv->chip_data;
881
882 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
883 if (ret) {
884 dev_err(priv->dev, "unable to read chip id\n");
885 return ret;
886 }
887
888 switch (chip_id) {
889 case RTL8366RB_CHIP_ID_8366:
890 break;
891 default:
892 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
893 return -ENODEV;
894 }
895
896 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
897 &chip_ver);
898 if (ret) {
899 dev_err(priv->dev, "unable to read chip version\n");
900 return ret;
901 }
902
903 dev_info(priv->dev, "RTL%04x ver %u chip found\n",
904 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
905
906 /* Do the init dance using the right jam table */
907 switch (chip_ver) {
908 case 0:
909 jam_table = rtl8366rb_init_jam_ver_0;
910 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
911 break;
912 case 1:
913 jam_table = rtl8366rb_init_jam_ver_1;
914 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
915 break;
916 case 2:
917 jam_table = rtl8366rb_init_jam_ver_2;
918 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
919 break;
920 default:
921 jam_table = rtl8366rb_init_jam_ver_3;
922 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
923 break;
924 }
925
926 /* Special jam tables for special routers
927 * TODO: are these necessary? Maintainers, please test
928 * without them, using just the off-the-shelf tables.
929 */
930 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
931 jam_table = rtl8366rb_init_jam_f5d8235;
932 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
933 }
934 if (of_machine_is_compatible("netgear,dgn3500") ||
935 of_machine_is_compatible("netgear,dgn3500b")) {
936 jam_table = rtl8366rb_init_jam_dgn3500;
937 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
938 }
939
940 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
941 if (ret)
942 return ret;
943
944 /* Start with all ports blocked, including unused ports */
945 dsa_switch_for_each_port(dp, ds) {
946 /* Set the initial STP state of all ports to DISABLED, otherwise
947 * ports will still forward frames to the CPU despite being
948 * administratively down by default.
949 */
950 rtl8366rb_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED);
951
952 /* Start with all ports completely isolated */
953 ret = rtl8366rb_port_set_isolation(priv, dp->index, 0);
954 if (ret)
955 return ret;
956
957 /* Disable learning */
958 ret = rtl8366rb_port_set_learning(priv, dp->index, false);
959 if (ret)
960 return ret;
961
962 /* Collect CPU ports. If we support cascade switches, it should
963 * also include the upstream DSA ports.
964 */
965 if (!dsa_port_is_cpu(dp))
966 continue;
967
968 upports_mask |= BIT(dp->index);
969 }
970
971 /* Configure user ports */
972 dsa_switch_for_each_port(dp, ds) {
973 if (!dsa_port_is_user(dp))
974 continue;
975
976 /* Forward only to the CPU(s), isolate from all other ports */
977 ret = rtl8366rb_port_set_isolation(priv, dp->index, upports_mask);
978 if (ret)
979 return ret;
980
981 /* If we support cascade switches, it should also include the
982 * downstream DSA ports.
983 */
984 downports_mask |= BIT(dp->index);
985 }
986
987 /* Configure CPU ports. If we support cascade switches, this will also
988 * include DSA ports.
989 */
990 dsa_switch_for_each_cpu_port(dp, ds) {
991 /* Forward to all user ports */
992 ret = rtl8366rb_port_set_isolation(priv, dp->index, downports_mask);
993 if (ret)
994 return ret;
995 }
996
997 /* Set up the "green ethernet" feature */
998 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
999 ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
1000 if (ret)
1001 return ret;
1002
1003 ret = regmap_write(priv->map,
1004 RTL8366RB_GREEN_FEATURE_REG,
1005 (chip_ver == 1) ? 0x0007 : 0x0003);
1006 if (ret)
1007 return ret;
1008
1009 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
1010 ret = regmap_write(priv->map, 0x0c, 0x240);
1011 if (ret)
1012 return ret;
1013 ret = regmap_write(priv->map, 0x0d, 0x240);
1014 if (ret)
1015 return ret;
1016
1017 /* Set some random MAC address */
1018 ret = rtl8366rb_set_addr(priv);
1019 if (ret)
1020 return ret;
1021
1022 /* Enable CPU port with custom DSA tag 8899.
1023 *
1024 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
1025 * the custom tag is turned off.
1026 */
1027 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
1028 0xFFFF,
1029 BIT(priv->cpu_port));
1030 if (ret)
1031 return ret;
1032
1033 /* Make sure we default-enable the fixed CPU port */
1034 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
1035 BIT(priv->cpu_port),
1036 0);
1037 if (ret)
1038 return ret;
1039
1040 /* Set default maximum packet length to 1536 bytes */
1041 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
1042 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1043 RTL8366RB_SGCR_MAX_LENGTH_1536);
1044 if (ret)
1045 return ret;
1046 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1047 if (i == priv->cpu_port)
1048 /* CPU port need to also accept the tag */
1049 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
1050 else
1051 rb->max_mtu[i] = ETH_DATA_LEN;
1052 }
1053
1054 /* Enable auto ageing for all ports */
1055 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
1056 if (ret)
1057 return ret;
1058
1059 /* Port 4 setup: this enables Port 4, usually the WAN port,
1060 * common PHY IO mode is apparently mode 0, and this is not what
1061 * the port is initialized to. There is no explanation of the
1062 * IO modes in the Realtek source code, if your WAN port is
1063 * connected to something exotic such as fiber, then this might
1064 * be worth experimenting with.
1065 */
1066 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
1067 RTL8366RB_PMC0_P4_IOMODE_MASK,
1068 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
1069 if (ret)
1070 return ret;
1071
1072 /* Accept all packets by default, we enable filtering on-demand */
1073 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1074 0);
1075 if (ret)
1076 return ret;
1077 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1078 0);
1079 if (ret)
1080 return ret;
1081
1082 /* Don't drop packets whose DA has not been learned */
1083 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
1084 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
1085 if (ret)
1086 return ret;
1087
1088 /* Set blinking, used by all LED groups using HW triggers.
1089 * TODO: make this configurable
1090 */
1091 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
1092 RTL8366RB_LED_BLINKRATE_MASK,
1093 RTL8366RB_LED_BLINKRATE_56MS);
1094 if (ret)
1095 return ret;
1096
1097 /* Set up LED activity:
1098 * Each port has 4 LEDs on fixed groups. Each group shares the same
1099 * hardware trigger across all ports. LEDs can only be indiviually
1100 * controlled setting the LED group to fixed mode and using the driver
1101 * to toggle them LEDs on/off.
1102 */
1103 if (priv->leds_disabled) {
1104 ret = rtl8366rb_setup_all_leds_off(priv);
1105 if (ret)
1106 return ret;
1107 } else {
1108 ret = rtl8366rb_setup_leds(priv);
1109 if (ret)
1110 return ret;
1111 }
1112
1113 ret = rtl8366_reset_vlan(priv);
1114 if (ret)
1115 return ret;
1116
1117 ret = rtl8366rb_setup_cascaded_irq(priv);
1118 if (ret)
1119 dev_info(priv->dev, "no interrupt support\n");
1120
1121 ret = rtl83xx_setup_user_mdio(ds);
1122 if (ret) {
1123 dev_err(priv->dev, "could not set up MDIO bus\n");
1124 return -ENODEV;
1125 }
1126
1127 return 0;
1128 }
1129
rtl8366_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1130 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1131 int port,
1132 enum dsa_tag_protocol mp)
1133 {
1134 /* This switch uses the 4 byte protocol A Realtek DSA tag */
1135 return DSA_TAG_PROTO_RTL4_A;
1136 }
1137
rtl8366rb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1138 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1139 struct phylink_config *config)
1140 {
1141 unsigned long *interfaces = config->supported_interfaces;
1142 struct realtek_priv *priv = ds->priv;
1143
1144 if (port == priv->cpu_port) {
1145 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1146 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1147 /* REVMII only supports 100M FD */
1148 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1149 /* RGMII only supports 1G FD */
1150 phy_interface_set_rgmii(interfaces);
1151
1152 config->mac_capabilities = MAC_1000 | MAC_100 |
1153 MAC_SYM_PAUSE;
1154 } else {
1155 /* RSGMII port, but we don't have that, and we don't
1156 * specify in DT, so phylib uses the default of GMII
1157 */
1158 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1159 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1160 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1161 }
1162 }
1163
1164 static void
rtl8366rb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1165 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,
1166 const struct phylink_link_state *state)
1167 {
1168 }
1169
1170 static void
rtl8366rb_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1171 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
1172 unsigned int mode, phy_interface_t interface,
1173 int speed, int duplex, bool tx_pause, bool rx_pause)
1174 {
1175 struct dsa_port *dp = dsa_phylink_to_port(config);
1176 struct realtek_priv *priv = dp->ds->priv;
1177 int port = dp->index;
1178 unsigned int val;
1179 int ret;
1180
1181 /* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1182 * We assume autonegotiation works on the PHY-facing ports.
1183 */
1184 if (port != priv->cpu_port)
1185 return;
1186
1187 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1188
1189 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1190 BIT(port), BIT(port));
1191 if (ret) {
1192 dev_err(priv->dev, "failed to force CPU port\n");
1193 return;
1194 }
1195
1196 /* Conjure port config */
1197 switch (speed) {
1198 case SPEED_10:
1199 val = RTL8366RB_PAACR_SPEED_10M;
1200 break;
1201 case SPEED_100:
1202 val = RTL8366RB_PAACR_SPEED_100M;
1203 break;
1204 case SPEED_1000:
1205 val = RTL8366RB_PAACR_SPEED_1000M;
1206 break;
1207 default:
1208 val = RTL8366RB_PAACR_SPEED_1000M;
1209 break;
1210 }
1211
1212 if (duplex == DUPLEX_FULL)
1213 val |= RTL8366RB_PAACR_FULL_DUPLEX;
1214
1215 if (tx_pause)
1216 val |= RTL8366RB_PAACR_TX_PAUSE;
1217
1218 if (rx_pause)
1219 val |= RTL8366RB_PAACR_RX_PAUSE;
1220
1221 val |= RTL8366RB_PAACR_LINK_UP;
1222
1223 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1224 0xFF00U,
1225 val << 8);
1226 if (ret) {
1227 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1228 return;
1229 }
1230
1231 dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1232
1233 /* Enable the CPU port */
1234 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1235 0);
1236 if (ret) {
1237 dev_err(priv->dev, "failed to enable the CPU port\n");
1238 return;
1239 }
1240 }
1241
1242 static void
rtl8366rb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1243 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,
1244 phy_interface_t interface)
1245 {
1246 struct dsa_port *dp = dsa_phylink_to_port(config);
1247 struct realtek_priv *priv = dp->ds->priv;
1248 int port = dp->index;
1249 int ret;
1250
1251 if (port != priv->cpu_port)
1252 return;
1253
1254 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1255
1256 /* Disable the CPU port */
1257 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1258 BIT(port));
1259 if (ret) {
1260 dev_err(priv->dev, "failed to disable the CPU port\n");
1261 return;
1262 }
1263 }
1264
1265 static int
rtl8366rb_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1266 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1267 struct phy_device *phy)
1268 {
1269 struct realtek_priv *priv = ds->priv;
1270 int ret;
1271
1272 dev_dbg(priv->dev, "enable port %d\n", port);
1273 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1274 0);
1275 if (ret)
1276 return ret;
1277
1278 return 0;
1279 }
1280
1281 static void
rtl8366rb_port_disable(struct dsa_switch * ds,int port)1282 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1283 {
1284 struct realtek_priv *priv = ds->priv;
1285 int ret;
1286
1287 dev_dbg(priv->dev, "disable port %d\n", port);
1288 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1289 BIT(port));
1290 if (ret)
1291 return;
1292 }
1293
1294 /**
1295 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1296 * @priv: SMI state container
1297 * @port: the port to drop untagged and C-tagged frames on
1298 * @drop: whether to drop or pass untagged and C-tagged frames
1299 *
1300 * Return: zero for success, a negative number on error.
1301 */
rtl8366rb_drop_untagged(struct realtek_priv * priv,int port,bool drop)1302 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1303 {
1304 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1305 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1306 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1307 }
1308
rtl8366rb_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1309 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1310 bool vlan_filtering,
1311 struct netlink_ext_ack *extack)
1312 {
1313 struct realtek_priv *priv = ds->priv;
1314 struct rtl8366rb *rb;
1315 int ret;
1316
1317 rb = priv->chip_data;
1318
1319 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1320 str_enable_disable(vlan_filtering));
1321
1322 /* If the port is not in the member set, the frame will be dropped */
1323 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1324 BIT(port), vlan_filtering ? BIT(port) : 0);
1325 if (ret)
1326 return ret;
1327
1328 /* If VLAN filtering is enabled and PVID is also enabled, we must
1329 * not drop any untagged or C-tagged frames. If we turn off VLAN
1330 * filtering on a port, we need to accept any frames.
1331 */
1332 if (vlan_filtering)
1333 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1334 else
1335 ret = rtl8366rb_drop_untagged(priv, port, false);
1336
1337 return ret;
1338 }
1339
1340 static int
rtl8366rb_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1341 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1342 struct switchdev_brport_flags flags,
1343 struct netlink_ext_ack *extack)
1344 {
1345 /* We support enabling/disabling learning */
1346 if (flags.mask & ~(BR_LEARNING))
1347 return -EINVAL;
1348
1349 return 0;
1350 }
1351
1352 static void
rtl8366rb_port_fast_age(struct dsa_switch * ds,int port)1353 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1354 {
1355 struct realtek_priv *priv = ds->priv;
1356
1357 /* This will age out any learned L2 entries */
1358 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1359 BIT(port), BIT(port));
1360 /* Restore the normal state of things */
1361 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1362 BIT(port), 0);
1363 }
1364
rtl8366rb_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1365 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1366 {
1367 struct realtek_priv *priv = ds->priv;
1368 struct rtl8366rb *rb;
1369 unsigned int max_mtu;
1370 u32 len;
1371 int i;
1372
1373 /* Cache the per-port MTU setting */
1374 rb = priv->chip_data;
1375 rb->max_mtu[port] = new_mtu;
1376
1377 /* Roof out the MTU for the entire switch to the greatest
1378 * common denominator: the biggest set for any one port will
1379 * be the biggest MTU for the switch.
1380 */
1381 max_mtu = ETH_DATA_LEN;
1382 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1383 if (rb->max_mtu[i] > max_mtu)
1384 max_mtu = rb->max_mtu[i];
1385 }
1386
1387 /* Translate to layer 2 size.
1388 * Add ethernet and (possible) VLAN headers, and checksum to the size.
1389 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1390 */
1391 max_mtu += VLAN_ETH_HLEN;
1392 max_mtu += ETH_FCS_LEN;
1393
1394 if (max_mtu <= 1522)
1395 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1396 else if (max_mtu > 1522 && max_mtu <= 1536)
1397 /* This will be the most common default if using VLAN and
1398 * CPU tagging on a port as both VLAN and CPU tag will
1399 * result in 1518 + 4 + 4 = 1526 bytes.
1400 */
1401 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1402 else if (max_mtu > 1536 && max_mtu <= 1552)
1403 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1404 else
1405 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1406
1407 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1408 RTL8366RB_SGCR_MAX_LENGTH_MASK,
1409 len);
1410 }
1411
rtl8366rb_max_mtu(struct dsa_switch * ds,int port)1412 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1413 {
1414 /* The max MTU is 16000 bytes, so we subtract the ethernet
1415 * headers with VLAN and checksum and arrive at
1416 * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1417 * since that is added to the requested MTU by the DSA framework.
1418 */
1419 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1420 }
1421
rtl8366rb_get_vlan_4k(struct realtek_priv * priv,u32 vid,struct rtl8366_vlan_4k * vlan4k)1422 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1423 struct rtl8366_vlan_4k *vlan4k)
1424 {
1425 u32 data[3];
1426 int ret;
1427 int i;
1428
1429 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1430
1431 if (vid >= RTL8366RB_NUM_VIDS)
1432 return -EINVAL;
1433
1434 /* write VID */
1435 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1436 vid & RTL8366RB_VLAN_VID_MASK);
1437 if (ret)
1438 return ret;
1439
1440 /* write table access control word */
1441 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1442 RTL8366RB_TABLE_VLAN_READ_CTRL);
1443 if (ret)
1444 return ret;
1445
1446 for (i = 0; i < 3; i++) {
1447 ret = regmap_read(priv->map,
1448 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1449 &data[i]);
1450 if (ret)
1451 return ret;
1452 }
1453
1454 vlan4k->vid = vid;
1455 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1456 RTL8366RB_VLAN_UNTAG_MASK;
1457 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1458 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1459
1460 return 0;
1461 }
1462
rtl8366rb_set_vlan_4k(struct realtek_priv * priv,const struct rtl8366_vlan_4k * vlan4k)1463 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1464 const struct rtl8366_vlan_4k *vlan4k)
1465 {
1466 u32 data[3];
1467 int ret;
1468 int i;
1469
1470 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1471 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1472 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1473 vlan4k->fid > RTL8366RB_FIDMAX)
1474 return -EINVAL;
1475
1476 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1477 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1478 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1479 RTL8366RB_VLAN_UNTAG_SHIFT);
1480 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1481
1482 for (i = 0; i < 3; i++) {
1483 ret = regmap_write(priv->map,
1484 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1485 data[i]);
1486 if (ret)
1487 return ret;
1488 }
1489
1490 /* write table access control word */
1491 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1492 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1493
1494 return ret;
1495 }
1496
rtl8366rb_get_vlan_mc(struct realtek_priv * priv,u32 index,struct rtl8366_vlan_mc * vlanmc)1497 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1498 struct rtl8366_vlan_mc *vlanmc)
1499 {
1500 u32 data[3];
1501 int ret;
1502 int i;
1503
1504 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1505
1506 if (index >= RTL8366RB_NUM_VLANS)
1507 return -EINVAL;
1508
1509 for (i = 0; i < 3; i++) {
1510 ret = regmap_read(priv->map,
1511 RTL8366RB_VLAN_MC_BASE(index) + i,
1512 &data[i]);
1513 if (ret)
1514 return ret;
1515 }
1516
1517 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1518 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1519 RTL8366RB_VLAN_PRIORITY_MASK;
1520 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1521 RTL8366RB_VLAN_UNTAG_MASK;
1522 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1523 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1524
1525 return 0;
1526 }
1527
rtl8366rb_set_vlan_mc(struct realtek_priv * priv,u32 index,const struct rtl8366_vlan_mc * vlanmc)1528 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1529 const struct rtl8366_vlan_mc *vlanmc)
1530 {
1531 u32 data[3];
1532 int ret;
1533 int i;
1534
1535 if (index >= RTL8366RB_NUM_VLANS ||
1536 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1537 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1538 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1539 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1540 vlanmc->fid > RTL8366RB_FIDMAX)
1541 return -EINVAL;
1542
1543 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1544 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1545 RTL8366RB_VLAN_PRIORITY_SHIFT);
1546 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1547 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1548 RTL8366RB_VLAN_UNTAG_SHIFT);
1549 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1550
1551 for (i = 0; i < 3; i++) {
1552 ret = regmap_write(priv->map,
1553 RTL8366RB_VLAN_MC_BASE(index) + i,
1554 data[i]);
1555 if (ret)
1556 return ret;
1557 }
1558
1559 return 0;
1560 }
1561
rtl8366rb_get_mc_index(struct realtek_priv * priv,int port,int * val)1562 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1563 {
1564 u32 data;
1565 int ret;
1566
1567 if (port >= priv->num_ports)
1568 return -EINVAL;
1569
1570 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1571 &data);
1572 if (ret)
1573 return ret;
1574
1575 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1576 RTL8366RB_PORT_VLAN_CTRL_MASK;
1577
1578 return 0;
1579 }
1580
rtl8366rb_set_mc_index(struct realtek_priv * priv,int port,int index)1581 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1582 {
1583 struct dsa_switch *ds = &priv->ds;
1584 struct rtl8366rb *rb;
1585 bool pvid_enabled;
1586 int ret;
1587
1588 rb = priv->chip_data;
1589 pvid_enabled = !!index;
1590
1591 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1592 return -EINVAL;
1593
1594 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1595 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1596 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1597 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1598 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1599 if (ret)
1600 return ret;
1601
1602 rb->pvid_enabled[port] = pvid_enabled;
1603
1604 /* If VLAN filtering is enabled and PVID is also enabled, we must
1605 * not drop any untagged or C-tagged frames. Make sure to update the
1606 * filtering setting.
1607 */
1608 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1609 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1610
1611 return ret;
1612 }
1613
rtl8366rb_is_vlan_valid(struct realtek_priv * priv,unsigned int vlan)1614 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1615 {
1616 unsigned int max = RTL8366RB_NUM_VLANS - 1;
1617
1618 if (priv->vlan4k_enabled)
1619 max = RTL8366RB_NUM_VIDS - 1;
1620
1621 if (vlan > max)
1622 return false;
1623
1624 return true;
1625 }
1626
rtl8366rb_enable_vlan(struct realtek_priv * priv,bool enable)1627 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1628 {
1629 dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable));
1630 return regmap_update_bits(priv->map,
1631 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1632 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1633 }
1634
rtl8366rb_enable_vlan4k(struct realtek_priv * priv,bool enable)1635 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1636 {
1637 dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable));
1638 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1639 RTL8366RB_SGCR_EN_VLAN_4KTB,
1640 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1641 }
1642
rtl8366rb_phy_read(struct realtek_priv * priv,int phy,int regnum)1643 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1644 {
1645 u32 val;
1646 u32 reg;
1647 int ret;
1648
1649 if (phy > RTL8366RB_PHY_NO_MAX)
1650 return -EINVAL;
1651
1652 rtl83xx_lock(priv);
1653
1654 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1655 RTL8366RB_PHY_CTRL_READ);
1656 if (ret)
1657 goto out;
1658
1659 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1660
1661 ret = regmap_write(priv->map_nolock, reg, 0);
1662 if (ret) {
1663 dev_err(priv->dev,
1664 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1665 phy, regnum, reg, ret);
1666 goto out;
1667 }
1668
1669 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1670 &val);
1671 if (ret)
1672 goto out;
1673
1674 ret = val;
1675
1676 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1677 phy, regnum, reg, val);
1678
1679 out:
1680 rtl83xx_unlock(priv);
1681
1682 return ret;
1683 }
1684
rtl8366rb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)1685 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1686 u16 val)
1687 {
1688 u32 reg;
1689 int ret;
1690
1691 if (phy > RTL8366RB_PHY_NO_MAX)
1692 return -EINVAL;
1693
1694 rtl83xx_lock(priv);
1695
1696 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1697 RTL8366RB_PHY_CTRL_WRITE);
1698 if (ret)
1699 goto out;
1700
1701 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1702
1703 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1704 phy, regnum, reg, val);
1705
1706 ret = regmap_write(priv->map_nolock, reg, val);
1707 if (ret)
1708 goto out;
1709
1710 out:
1711 rtl83xx_unlock(priv);
1712
1713 return ret;
1714 }
1715
rtl8366rb_reset_chip(struct realtek_priv * priv)1716 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1717 {
1718 int timeout = 10;
1719 u32 val;
1720 int ret;
1721
1722 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1723 RTL8366RB_CHIP_CTRL_RESET_HW);
1724 do {
1725 usleep_range(20000, 25000);
1726 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1727 if (ret)
1728 return ret;
1729
1730 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1731 break;
1732 } while (--timeout);
1733
1734 if (!timeout) {
1735 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1736 return -EIO;
1737 }
1738
1739 return 0;
1740 }
1741
rtl8366rb_detect(struct realtek_priv * priv)1742 static int rtl8366rb_detect(struct realtek_priv *priv)
1743 {
1744 struct device *dev = priv->dev;
1745 int ret;
1746 u32 val;
1747
1748 /* Detect device */
1749 ret = regmap_read(priv->map, 0x5c, &val);
1750 if (ret) {
1751 dev_err(dev, "can't get chip ID (%d)\n", ret);
1752 return ret;
1753 }
1754
1755 switch (val) {
1756 case 0x6027:
1757 dev_info(dev, "found an RTL8366S switch\n");
1758 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1759 return -ENODEV;
1760 case 0x5937:
1761 dev_info(dev, "found an RTL8366RB switch\n");
1762 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1763 priv->num_ports = RTL8366RB_NUM_PORTS;
1764 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1765 priv->mib_counters = rtl8366rb_mib_counters;
1766 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1767 break;
1768 default:
1769 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1770 val);
1771 break;
1772 }
1773
1774 ret = rtl8366rb_reset_chip(priv);
1775 if (ret)
1776 return ret;
1777
1778 return 0;
1779 }
1780
1781 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {
1782 .mac_config = rtl8366rb_mac_config,
1783 .mac_link_down = rtl8366rb_mac_link_down,
1784 .mac_link_up = rtl8366rb_mac_link_up,
1785 };
1786
1787 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1788 .get_tag_protocol = rtl8366_get_tag_protocol,
1789 .setup = rtl8366rb_setup,
1790 .phylink_get_caps = rtl8366rb_phylink_get_caps,
1791 .get_strings = rtl8366_get_strings,
1792 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1793 .get_sset_count = rtl8366_get_sset_count,
1794 .port_bridge_join = rtl83xx_port_bridge_join,
1795 .port_bridge_leave = rtl83xx_port_bridge_leave,
1796 .port_vlan_filtering = rtl8366rb_vlan_filtering,
1797 .port_vlan_add = rtl8366_vlan_add,
1798 .port_vlan_del = rtl8366_vlan_del,
1799 .port_enable = rtl8366rb_port_enable,
1800 .port_disable = rtl8366rb_port_disable,
1801 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1802 .port_bridge_flags = rtl83xx_port_bridge_flags,
1803 .port_stp_state_set = rtl8366rb_port_stp_state_set,
1804 .port_fast_age = rtl8366rb_port_fast_age,
1805 .port_change_mtu = rtl8366rb_change_mtu,
1806 .port_max_mtu = rtl8366rb_max_mtu,
1807 .port_hsr_join = dsa_port_simple_hsr_join,
1808 .port_hsr_leave = dsa_port_simple_hsr_leave,
1809 };
1810
1811 static const struct realtek_ops rtl8366rb_ops = {
1812 .detect = rtl8366rb_detect,
1813 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1814 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1815 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1816 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1817 .get_mc_index = rtl8366rb_get_mc_index,
1818 .set_mc_index = rtl8366rb_set_mc_index,
1819 .get_mib_counter = rtl8366rb_get_mib_counter,
1820 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1821 .enable_vlan = rtl8366rb_enable_vlan,
1822 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1823 .port_add_isolation = rtl8366rb_port_add_isolation,
1824 .port_remove_isolation = rtl8366rb_port_remove_isolation,
1825 .port_set_learning = rtl8366rb_port_set_learning,
1826 .phy_read = rtl8366rb_phy_read,
1827 .phy_write = rtl8366rb_phy_write,
1828 };
1829
1830 const struct realtek_variant rtl8366rb_variant = {
1831 .ds_ops = &rtl8366rb_switch_ops,
1832 .ops = &rtl8366rb_ops,
1833 .phylink_mac_ops = &rtl8366rb_phylink_mac_ops,
1834 .clk_delay = 10,
1835 .cmd_read = 0xa9,
1836 .cmd_write = 0xa8,
1837 .chip_data_sz = sizeof(struct rtl8366rb),
1838 };
1839
1840 static const struct of_device_id rtl8366rb_of_match[] = {
1841 { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
1842 { /* sentinel */ },
1843 };
1844 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
1845
1846 static struct platform_driver rtl8366rb_smi_driver = {
1847 .driver = {
1848 .name = "rtl8366rb-smi",
1849 .of_match_table = rtl8366rb_of_match,
1850 },
1851 .probe = realtek_smi_probe,
1852 .remove = realtek_smi_remove,
1853 .shutdown = realtek_smi_shutdown,
1854 };
1855
1856 static struct mdio_driver rtl8366rb_mdio_driver = {
1857 .mdiodrv.driver = {
1858 .name = "rtl8366rb-mdio",
1859 .of_match_table = rtl8366rb_of_match,
1860 },
1861 .probe = realtek_mdio_probe,
1862 .remove = realtek_mdio_remove,
1863 .shutdown = realtek_mdio_shutdown,
1864 };
1865
rtl8366rb_init(void)1866 static int rtl8366rb_init(void)
1867 {
1868 int ret;
1869
1870 ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);
1871 if (ret)
1872 return ret;
1873
1874 ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);
1875 if (ret) {
1876 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1877 return ret;
1878 }
1879
1880 return 0;
1881 }
1882 module_init(rtl8366rb_init);
1883
rtl8366rb_exit(void)1884 static void __exit rtl8366rb_exit(void)
1885 {
1886 realtek_smi_driver_unregister(&rtl8366rb_smi_driver);
1887 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1888 }
1889 module_exit(rtl8366rb_exit);
1890
1891 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1892 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1893 MODULE_LICENSE("GPL");
1894 MODULE_IMPORT_NS("REALTEK_DSA");
1895