1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10 #include <linux/bitops.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/clk.h>
16 #include <linux/string_choices.h>
17
18 #include "realtek.h"
19
20 #define RTL821x_PHYSR 0x11
21 #define RTL821x_PHYSR_DUPLEX BIT(13)
22 #define RTL821x_PHYSR_SPEED GENMASK(15, 14)
23
24 #define RTL821x_INER 0x12
25 #define RTL8211B_INER_INIT 0x6400
26 #define RTL8211E_INER_LINK_STATUS BIT(10)
27 #define RTL8211F_INER_LINK_STATUS BIT(4)
28
29 #define RTL821x_INSR 0x13
30
31 #define RTL821x_EXT_PAGE_SELECT 0x1e
32 #define RTL821x_PAGE_SELECT 0x1f
33
34 #define RTL8211F_PHYCR1 0x18
35 #define RTL8211F_PHYCR2 0x19
36 #define RTL8211F_CLKOUT_EN BIT(0)
37 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5)
38
39 #define RTL8211F_INSR 0x1d
40
41 #define RTL8211F_LEDCR 0x10
42 #define RTL8211F_LEDCR_MODE BIT(15)
43 #define RTL8211F_LEDCR_ACT_TXRX BIT(4)
44 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
45 #define RTL8211F_LEDCR_LINK_100 BIT(1)
46 #define RTL8211F_LEDCR_LINK_10 BIT(0)
47 #define RTL8211F_LEDCR_MASK GENMASK(4, 0)
48 #define RTL8211F_LEDCR_SHIFT 5
49
50 #define RTL8211F_TX_DELAY BIT(8)
51 #define RTL8211F_RX_DELAY BIT(3)
52
53 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
54 #define RTL8211F_ALDPS_ENABLE BIT(2)
55 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
56
57 #define RTL8211E_CTRL_DELAY BIT(13)
58 #define RTL8211E_TX_DELAY BIT(12)
59 #define RTL8211E_RX_DELAY BIT(11)
60
61 #define RTL8201F_ISR 0x1e
62 #define RTL8201F_ISR_ANERR BIT(15)
63 #define RTL8201F_ISR_DUPLEX BIT(13)
64 #define RTL8201F_ISR_LINK BIT(11)
65 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
66 RTL8201F_ISR_DUPLEX | \
67 RTL8201F_ISR_LINK)
68 #define RTL8201F_IER 0x13
69
70 #define RTL822X_VND1_SERDES_OPTION 0x697a
71 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
72 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
73 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
74
75 #define RTL822X_VND1_SERDES_CTRL3 0x7580
76 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
77 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
78 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
79
80 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
81 * is set, they cannot be accessed by C45-over-C22.
82 */
83 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg))
84
85 #define RTL8366RB_POWER_SAVE 0x15
86 #define RTL8366RB_POWER_SAVE_ON BIT(12)
87
88 #define RTL9000A_GINMR 0x14
89 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
90
91 #define RTL_VND2_PHYSR 0xa434
92 #define RTL_VND2_PHYSR_DUPLEX BIT(3)
93 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
94 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
95 #define RTL_VND2_PHYSR_MASTER BIT(11)
96 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
97
98 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4
99 #define RTL_MDIO_AN_EEE_ADV 0xa5d0
100 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2
101 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4
102 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6
103 #define RTL_MDIO_PMA_SPEED 0xa616
104 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0
105 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4
106 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec
107
108 #define RTL_GENERIC_PHYID 0x001cc800
109 #define RTL_8211FVD_PHYID 0x001cc878
110 #define RTL_8221B 0x001cc840
111 #define RTL_8221B_VB_CG 0x001cc849
112 #define RTL_8221B_VN_CG 0x001cc84a
113 #define RTL_8251B 0x001cc862
114
115 #define RTL8211F_LED_COUNT 3
116
117 MODULE_DESCRIPTION("Realtek PHY driver");
118 MODULE_AUTHOR("Johnson Leung");
119 MODULE_LICENSE("GPL");
120
121 struct rtl821x_priv {
122 u16 phycr1;
123 u16 phycr2;
124 bool has_phycr2;
125 struct clk *clk;
126 };
127
rtl821x_read_page(struct phy_device * phydev)128 static int rtl821x_read_page(struct phy_device *phydev)
129 {
130 return __phy_read(phydev, RTL821x_PAGE_SELECT);
131 }
132
rtl821x_write_page(struct phy_device * phydev,int page)133 static int rtl821x_write_page(struct phy_device *phydev, int page)
134 {
135 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
136 }
137
rtl821x_probe(struct phy_device * phydev)138 static int rtl821x_probe(struct phy_device *phydev)
139 {
140 struct device *dev = &phydev->mdio.dev;
141 struct rtl821x_priv *priv;
142 u32 phy_id = phydev->drv->phy_id;
143 int ret;
144
145 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
146 if (!priv)
147 return -ENOMEM;
148
149 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
150 if (IS_ERR(priv->clk))
151 return dev_err_probe(dev, PTR_ERR(priv->clk),
152 "failed to get phy clock\n");
153
154 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
155 if (ret < 0)
156 return ret;
157
158 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
159 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
160 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
161
162 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
163 if (priv->has_phycr2) {
164 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
165 if (ret < 0)
166 return ret;
167
168 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
169 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
170 priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
171 }
172
173 phydev->priv = priv;
174
175 return 0;
176 }
177
rtl8201_ack_interrupt(struct phy_device * phydev)178 static int rtl8201_ack_interrupt(struct phy_device *phydev)
179 {
180 int err;
181
182 err = phy_read(phydev, RTL8201F_ISR);
183
184 return (err < 0) ? err : 0;
185 }
186
rtl821x_ack_interrupt(struct phy_device * phydev)187 static int rtl821x_ack_interrupt(struct phy_device *phydev)
188 {
189 int err;
190
191 err = phy_read(phydev, RTL821x_INSR);
192
193 return (err < 0) ? err : 0;
194 }
195
rtl8211f_ack_interrupt(struct phy_device * phydev)196 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
197 {
198 int err;
199
200 err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
201
202 return (err < 0) ? err : 0;
203 }
204
rtl8201_config_intr(struct phy_device * phydev)205 static int rtl8201_config_intr(struct phy_device *phydev)
206 {
207 u16 val;
208 int err;
209
210 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
211 err = rtl8201_ack_interrupt(phydev);
212 if (err)
213 return err;
214
215 val = BIT(13) | BIT(12) | BIT(11);
216 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
217 } else {
218 val = 0;
219 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
220 if (err)
221 return err;
222
223 err = rtl8201_ack_interrupt(phydev);
224 }
225
226 return err;
227 }
228
rtl8211b_config_intr(struct phy_device * phydev)229 static int rtl8211b_config_intr(struct phy_device *phydev)
230 {
231 int err;
232
233 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
234 err = rtl821x_ack_interrupt(phydev);
235 if (err)
236 return err;
237
238 err = phy_write(phydev, RTL821x_INER,
239 RTL8211B_INER_INIT);
240 } else {
241 err = phy_write(phydev, RTL821x_INER, 0);
242 if (err)
243 return err;
244
245 err = rtl821x_ack_interrupt(phydev);
246 }
247
248 return err;
249 }
250
rtl8211e_config_intr(struct phy_device * phydev)251 static int rtl8211e_config_intr(struct phy_device *phydev)
252 {
253 int err;
254
255 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
256 err = rtl821x_ack_interrupt(phydev);
257 if (err)
258 return err;
259
260 err = phy_write(phydev, RTL821x_INER,
261 RTL8211E_INER_LINK_STATUS);
262 } else {
263 err = phy_write(phydev, RTL821x_INER, 0);
264 if (err)
265 return err;
266
267 err = rtl821x_ack_interrupt(phydev);
268 }
269
270 return err;
271 }
272
rtl8211f_config_intr(struct phy_device * phydev)273 static int rtl8211f_config_intr(struct phy_device *phydev)
274 {
275 u16 val;
276 int err;
277
278 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
279 err = rtl8211f_ack_interrupt(phydev);
280 if (err)
281 return err;
282
283 val = RTL8211F_INER_LINK_STATUS;
284 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
285 } else {
286 val = 0;
287 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
288 if (err)
289 return err;
290
291 err = rtl8211f_ack_interrupt(phydev);
292 }
293
294 return err;
295 }
296
rtl8201_handle_interrupt(struct phy_device * phydev)297 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
298 {
299 int irq_status;
300
301 irq_status = phy_read(phydev, RTL8201F_ISR);
302 if (irq_status < 0) {
303 phy_error(phydev);
304 return IRQ_NONE;
305 }
306
307 if (!(irq_status & RTL8201F_ISR_MASK))
308 return IRQ_NONE;
309
310 phy_trigger_machine(phydev);
311
312 return IRQ_HANDLED;
313 }
314
rtl821x_handle_interrupt(struct phy_device * phydev)315 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
316 {
317 int irq_status, irq_enabled;
318
319 irq_status = phy_read(phydev, RTL821x_INSR);
320 if (irq_status < 0) {
321 phy_error(phydev);
322 return IRQ_NONE;
323 }
324
325 irq_enabled = phy_read(phydev, RTL821x_INER);
326 if (irq_enabled < 0) {
327 phy_error(phydev);
328 return IRQ_NONE;
329 }
330
331 if (!(irq_status & irq_enabled))
332 return IRQ_NONE;
333
334 phy_trigger_machine(phydev);
335
336 return IRQ_HANDLED;
337 }
338
rtl8211f_handle_interrupt(struct phy_device * phydev)339 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
340 {
341 int irq_status;
342
343 irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
344 if (irq_status < 0) {
345 phy_error(phydev);
346 return IRQ_NONE;
347 }
348
349 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
350 return IRQ_NONE;
351
352 phy_trigger_machine(phydev);
353
354 return IRQ_HANDLED;
355 }
356
rtl8211_config_aneg(struct phy_device * phydev)357 static int rtl8211_config_aneg(struct phy_device *phydev)
358 {
359 int ret;
360
361 ret = genphy_config_aneg(phydev);
362 if (ret < 0)
363 return ret;
364
365 /* Quirk was copied from vendor driver. Unfortunately it includes no
366 * description of the magic numbers.
367 */
368 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
369 phy_write(phydev, 0x17, 0x2138);
370 phy_write(phydev, 0x0e, 0x0260);
371 } else {
372 phy_write(phydev, 0x17, 0x2108);
373 phy_write(phydev, 0x0e, 0x0000);
374 }
375
376 return 0;
377 }
378
rtl8211c_config_init(struct phy_device * phydev)379 static int rtl8211c_config_init(struct phy_device *phydev)
380 {
381 /* RTL8211C has an issue when operating in Gigabit slave mode */
382 return phy_set_bits(phydev, MII_CTRL1000,
383 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
384 }
385
rtl8211f_config_init(struct phy_device * phydev)386 static int rtl8211f_config_init(struct phy_device *phydev)
387 {
388 struct rtl821x_priv *priv = phydev->priv;
389 struct device *dev = &phydev->mdio.dev;
390 u16 val_txdly, val_rxdly;
391 int ret;
392
393 ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
394 RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
395 priv->phycr1);
396 if (ret < 0) {
397 dev_err(dev, "aldps mode configuration failed: %pe\n",
398 ERR_PTR(ret));
399 return ret;
400 }
401
402 switch (phydev->interface) {
403 case PHY_INTERFACE_MODE_RGMII:
404 val_txdly = 0;
405 val_rxdly = 0;
406 break;
407
408 case PHY_INTERFACE_MODE_RGMII_RXID:
409 val_txdly = 0;
410 val_rxdly = RTL8211F_RX_DELAY;
411 break;
412
413 case PHY_INTERFACE_MODE_RGMII_TXID:
414 val_txdly = RTL8211F_TX_DELAY;
415 val_rxdly = 0;
416 break;
417
418 case PHY_INTERFACE_MODE_RGMII_ID:
419 val_txdly = RTL8211F_TX_DELAY;
420 val_rxdly = RTL8211F_RX_DELAY;
421 break;
422
423 default: /* the rest of the modes imply leaving delay as is. */
424 return 0;
425 }
426
427 ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
428 val_txdly);
429 if (ret < 0) {
430 dev_err(dev, "Failed to update the TX delay register\n");
431 return ret;
432 } else if (ret) {
433 dev_dbg(dev,
434 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
435 str_enable_disable(val_txdly));
436 } else {
437 dev_dbg(dev,
438 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
439 str_enabled_disabled(val_txdly));
440 }
441
442 ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
443 val_rxdly);
444 if (ret < 0) {
445 dev_err(dev, "Failed to update the RX delay register\n");
446 return ret;
447 } else if (ret) {
448 dev_dbg(dev,
449 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
450 str_enable_disable(val_rxdly));
451 } else {
452 dev_dbg(dev,
453 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
454 str_enabled_disabled(val_rxdly));
455 }
456
457 /* Disable PHY-mode EEE so LPI is passed to the MAC */
458 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
459 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
460 if (ret)
461 return ret;
462
463 if (priv->has_phycr2) {
464 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
465 RTL8211F_CLKOUT_EN, priv->phycr2);
466 if (ret < 0) {
467 dev_err(dev, "clkout configuration failed: %pe\n",
468 ERR_PTR(ret));
469 return ret;
470 }
471
472 return genphy_soft_reset(phydev);
473 }
474
475 return 0;
476 }
477
rtl821x_suspend(struct phy_device * phydev)478 static int rtl821x_suspend(struct phy_device *phydev)
479 {
480 struct rtl821x_priv *priv = phydev->priv;
481 int ret = 0;
482
483 if (!phydev->wol_enabled) {
484 ret = genphy_suspend(phydev);
485
486 if (ret)
487 return ret;
488
489 clk_disable_unprepare(priv->clk);
490 }
491
492 return ret;
493 }
494
rtl821x_resume(struct phy_device * phydev)495 static int rtl821x_resume(struct phy_device *phydev)
496 {
497 struct rtl821x_priv *priv = phydev->priv;
498 int ret;
499
500 if (!phydev->wol_enabled)
501 clk_prepare_enable(priv->clk);
502
503 ret = genphy_resume(phydev);
504 if (ret < 0)
505 return ret;
506
507 msleep(20);
508
509 return 0;
510 }
511
rtl8211f_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)512 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
513 unsigned long rules)
514 {
515 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
516 BIT(TRIGGER_NETDEV_LINK_100) |
517 BIT(TRIGGER_NETDEV_LINK_1000) |
518 BIT(TRIGGER_NETDEV_RX) |
519 BIT(TRIGGER_NETDEV_TX);
520
521 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
522 * - Link: Configurable subset of 10/100/1000 link rates
523 * - Active: Blink on activity, RX or TX is not differentiated
524 * The Active option has two modes, A and B:
525 * - A: Link and Active indication at configurable, but matching,
526 * subset of 10/100/1000 link rates
527 * - B: Link indication at configurable subset of 10/100/1000 link
528 * rates and Active indication always at all three 10+100+1000
529 * link rates.
530 * This code currently uses mode B only.
531 */
532
533 if (index >= RTL8211F_LED_COUNT)
534 return -EINVAL;
535
536 /* Filter out any other unsupported triggers. */
537 if (rules & ~mask)
538 return -EOPNOTSUPP;
539
540 /* RX and TX are not differentiated, either both are set or not set. */
541 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
542 return -EOPNOTSUPP;
543
544 return 0;
545 }
546
rtl8211f_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)547 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
548 unsigned long *rules)
549 {
550 int val;
551
552 if (index >= RTL8211F_LED_COUNT)
553 return -EINVAL;
554
555 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
556 if (val < 0)
557 return val;
558
559 val >>= RTL8211F_LEDCR_SHIFT * index;
560 val &= RTL8211F_LEDCR_MASK;
561
562 if (val & RTL8211F_LEDCR_LINK_10)
563 set_bit(TRIGGER_NETDEV_LINK_10, rules);
564
565 if (val & RTL8211F_LEDCR_LINK_100)
566 set_bit(TRIGGER_NETDEV_LINK_100, rules);
567
568 if (val & RTL8211F_LEDCR_LINK_1000)
569 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
570
571 if (val & RTL8211F_LEDCR_ACT_TXRX) {
572 set_bit(TRIGGER_NETDEV_RX, rules);
573 set_bit(TRIGGER_NETDEV_TX, rules);
574 }
575
576 return 0;
577 }
578
rtl8211f_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)579 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
580 unsigned long rules)
581 {
582 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
583 u16 reg = 0;
584
585 if (index >= RTL8211F_LED_COUNT)
586 return -EINVAL;
587
588 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
589 reg |= RTL8211F_LEDCR_LINK_10;
590
591 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
592 reg |= RTL8211F_LEDCR_LINK_100;
593
594 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
595 reg |= RTL8211F_LEDCR_LINK_1000;
596
597 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
598 test_bit(TRIGGER_NETDEV_TX, &rules)) {
599 reg |= RTL8211F_LEDCR_ACT_TXRX;
600 }
601
602 reg <<= RTL8211F_LEDCR_SHIFT * index;
603 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
604
605 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
606 }
607
rtl8211e_config_init(struct phy_device * phydev)608 static int rtl8211e_config_init(struct phy_device *phydev)
609 {
610 int ret = 0, oldpage;
611 u16 val;
612
613 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
614 switch (phydev->interface) {
615 case PHY_INTERFACE_MODE_RGMII:
616 val = RTL8211E_CTRL_DELAY | 0;
617 break;
618 case PHY_INTERFACE_MODE_RGMII_ID:
619 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
620 break;
621 case PHY_INTERFACE_MODE_RGMII_RXID:
622 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
623 break;
624 case PHY_INTERFACE_MODE_RGMII_TXID:
625 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
626 break;
627 default: /* the rest of the modes imply leaving delays as is. */
628 return 0;
629 }
630
631 /* According to a sample driver there is a 0x1c config register on the
632 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
633 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
634 * The configuration register definition:
635 * 14 = reserved
636 * 13 = Force Tx RX Delay controlled by bit12 bit11,
637 * 12 = RX Delay, 11 = TX Delay
638 * 10:0 = Test && debug settings reserved by realtek
639 */
640 oldpage = phy_select_page(phydev, 0x7);
641 if (oldpage < 0)
642 goto err_restore_page;
643
644 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
645 if (ret)
646 goto err_restore_page;
647
648 ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
649 | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
650 val);
651
652 err_restore_page:
653 return phy_restore_page(phydev, oldpage, ret);
654 }
655
rtl8211b_suspend(struct phy_device * phydev)656 static int rtl8211b_suspend(struct phy_device *phydev)
657 {
658 phy_write(phydev, MII_MMD_DATA, BIT(9));
659
660 return genphy_suspend(phydev);
661 }
662
rtl8211b_resume(struct phy_device * phydev)663 static int rtl8211b_resume(struct phy_device *phydev)
664 {
665 phy_write(phydev, MII_MMD_DATA, 0);
666
667 return genphy_resume(phydev);
668 }
669
rtl8366rb_config_init(struct phy_device * phydev)670 static int rtl8366rb_config_init(struct phy_device *phydev)
671 {
672 int ret;
673
674 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
675 RTL8366RB_POWER_SAVE_ON);
676 if (ret) {
677 dev_err(&phydev->mdio.dev,
678 "error enabling power management\n");
679 }
680
681 return ret;
682 }
683
684 /* get actual speed to cover the downshift case */
rtlgen_decode_physr(struct phy_device * phydev,int val)685 static void rtlgen_decode_physr(struct phy_device *phydev, int val)
686 {
687 /* bit 3
688 * 0: Half Duplex
689 * 1: Full Duplex
690 */
691 if (val & RTL_VND2_PHYSR_DUPLEX)
692 phydev->duplex = DUPLEX_FULL;
693 else
694 phydev->duplex = DUPLEX_HALF;
695
696 switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
697 case 0x0000:
698 phydev->speed = SPEED_10;
699 break;
700 case 0x0010:
701 phydev->speed = SPEED_100;
702 break;
703 case 0x0020:
704 phydev->speed = SPEED_1000;
705 break;
706 case 0x0200:
707 phydev->speed = SPEED_10000;
708 break;
709 case 0x0210:
710 phydev->speed = SPEED_2500;
711 break;
712 case 0x0220:
713 phydev->speed = SPEED_5000;
714 break;
715 default:
716 break;
717 }
718
719 /* bit 11
720 * 0: Slave Mode
721 * 1: Master Mode
722 */
723 if (phydev->speed >= 1000) {
724 if (val & RTL_VND2_PHYSR_MASTER)
725 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
726 else
727 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
728 } else {
729 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
730 }
731 }
732
rtlgen_read_status(struct phy_device * phydev)733 static int rtlgen_read_status(struct phy_device *phydev)
734 {
735 int ret, val;
736
737 ret = genphy_read_status(phydev);
738 if (ret < 0)
739 return ret;
740
741 if (!phydev->link)
742 return 0;
743
744 val = phy_read_paged(phydev, 0xa43, 0x12);
745 if (val < 0)
746 return val;
747
748 rtlgen_decode_physr(phydev, val);
749
750 return 0;
751 }
752
rtlgen_read_vend2(struct phy_device * phydev,int regnum)753 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum)
754 {
755 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum);
756 }
757
rtlgen_write_vend2(struct phy_device * phydev,int regnum,u16 val)758 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val)
759 {
760 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum,
761 val);
762 }
763
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)764 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
765 {
766 int ret;
767
768 if (devnum == MDIO_MMD_VEND2)
769 ret = rtlgen_read_vend2(phydev, regnum);
770 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
771 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE);
772 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
773 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV);
774 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
775 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE);
776 else
777 ret = -EOPNOTSUPP;
778
779 return ret;
780 }
781
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)782 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
783 u16 val)
784 {
785 int ret;
786
787 if (devnum == MDIO_MMD_VEND2)
788 ret = rtlgen_write_vend2(phydev, regnum, val);
789 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
790 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV);
791 else
792 ret = -EOPNOTSUPP;
793
794 return ret;
795 }
796
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)797 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
798 {
799 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
800
801 if (ret != -EOPNOTSUPP)
802 return ret;
803
804 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
805 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2);
806 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
807 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2);
808 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
809 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2);
810
811 return ret;
812 }
813
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)814 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
815 u16 val)
816 {
817 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
818
819 if (ret != -EOPNOTSUPP)
820 return ret;
821
822 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
823 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val);
824
825 return ret;
826 }
827
rtl822x_probe(struct phy_device * phydev)828 static int rtl822x_probe(struct phy_device *phydev)
829 {
830 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) &&
831 phydev->phy_id != RTL_GENERIC_PHYID)
832 return rtl822x_hwmon_init(phydev);
833
834 return 0;
835 }
836
rtl822xb_config_init(struct phy_device * phydev)837 static int rtl822xb_config_init(struct phy_device *phydev)
838 {
839 bool has_2500, has_sgmii;
840 u16 mode;
841 int ret;
842
843 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
844 phydev->host_interfaces) ||
845 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
846
847 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
848 phydev->host_interfaces) ||
849 phydev->interface == PHY_INTERFACE_MODE_SGMII;
850
851 /* fill in possible interfaces */
852 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
853 has_2500);
854 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
855 has_sgmii);
856
857 if (!has_2500 && !has_sgmii)
858 return 0;
859
860 /* determine SerDes option mode */
861 if (has_2500 && !has_sgmii) {
862 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
863 phydev->rate_matching = RATE_MATCH_PAUSE;
864 } else {
865 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
866 phydev->rate_matching = RATE_MATCH_NONE;
867 }
868
869 /* the following sequence with magic numbers sets up the SerDes
870 * option mode
871 */
872 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
873 if (ret < 0)
874 return ret;
875
876 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
877 RTL822X_VND1_SERDES_OPTION,
878 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
879 mode);
880 if (ret < 0)
881 return ret;
882
883 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
884 if (ret < 0)
885 return ret;
886
887 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
888 if (ret < 0)
889 return ret;
890
891 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
892 }
893
rtl822xb_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)894 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
895 phy_interface_t iface)
896 {
897 int val;
898
899 /* Only rate matching at 2500base-x */
900 if (iface != PHY_INTERFACE_MODE_2500BASEX)
901 return RATE_MATCH_NONE;
902
903 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
904 if (val < 0)
905 return val;
906
907 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
908 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
909 return RATE_MATCH_PAUSE;
910
911 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
912 return RATE_MATCH_NONE;
913 }
914
rtl822x_get_features(struct phy_device * phydev)915 static int rtl822x_get_features(struct phy_device *phydev)
916 {
917 int val;
918
919 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED);
920 if (val < 0)
921 return val;
922
923 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
924 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
925 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
926 phydev->supported, val & MDIO_PMA_SPEED_5G);
927 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
928 phydev->supported, val & MDIO_SPEED_10G);
929
930 return genphy_read_abilities(phydev);
931 }
932
rtl822x_config_aneg(struct phy_device * phydev)933 static int rtl822x_config_aneg(struct phy_device *phydev)
934 {
935 int ret = 0;
936
937 if (phydev->autoneg == AUTONEG_ENABLE) {
938 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
939
940 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
941 RTL_MDIO_AN_10GBT_CTRL,
942 MDIO_AN_10GBT_CTRL_ADV2_5G |
943 MDIO_AN_10GBT_CTRL_ADV5G, adv);
944 if (ret < 0)
945 return ret;
946 }
947
948 return __genphy_config_aneg(phydev, ret);
949 }
950
rtl822xb_update_interface(struct phy_device * phydev)951 static void rtl822xb_update_interface(struct phy_device *phydev)
952 {
953 int val;
954
955 if (!phydev->link)
956 return;
957
958 /* Change interface according to serdes mode */
959 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
960 if (val < 0)
961 return;
962
963 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
964 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
965 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
966 break;
967 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
968 phydev->interface = PHY_INTERFACE_MODE_SGMII;
969 break;
970 }
971 }
972
rtl822x_read_status(struct phy_device * phydev)973 static int rtl822x_read_status(struct phy_device *phydev)
974 {
975 int lpadv, ret;
976
977 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
978
979 ret = rtlgen_read_status(phydev);
980 if (ret < 0)
981 return ret;
982
983 if (phydev->autoneg == AUTONEG_DISABLE ||
984 !phydev->autoneg_complete)
985 return 0;
986
987 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT);
988 if (lpadv < 0)
989 return lpadv;
990
991 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
992
993 return 0;
994 }
995
rtl822xb_read_status(struct phy_device * phydev)996 static int rtl822xb_read_status(struct phy_device *phydev)
997 {
998 int ret;
999
1000 ret = rtl822x_read_status(phydev);
1001 if (ret < 0)
1002 return ret;
1003
1004 rtl822xb_update_interface(phydev);
1005
1006 return 0;
1007 }
1008
rtl822x_c45_get_features(struct phy_device * phydev)1009 static int rtl822x_c45_get_features(struct phy_device *phydev)
1010 {
1011 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1012 phydev->supported);
1013
1014 return genphy_c45_pma_read_abilities(phydev);
1015 }
1016
rtl822x_c45_config_aneg(struct phy_device * phydev)1017 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1018 {
1019 bool changed = false;
1020 int ret, val;
1021
1022 if (phydev->autoneg == AUTONEG_DISABLE)
1023 return genphy_c45_pma_setup_forced(phydev);
1024
1025 ret = genphy_c45_an_config_aneg(phydev);
1026 if (ret < 0)
1027 return ret;
1028 if (ret > 0)
1029 changed = true;
1030
1031 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1032
1033 /* Vendor register as C45 has no standardized support for 1000BaseT */
1034 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
1035 RTL822X_VND2_C22_REG(MII_CTRL1000),
1036 ADVERTISE_1000FULL, val);
1037 if (ret < 0)
1038 return ret;
1039 if (ret > 0)
1040 changed = true;
1041
1042 return genphy_c45_check_and_restart_aneg(phydev, changed);
1043 }
1044
rtl822x_c45_read_status(struct phy_device * phydev)1045 static int rtl822x_c45_read_status(struct phy_device *phydev)
1046 {
1047 int ret, val;
1048
1049 /* Vendor register as C45 has no standardized support for 1000BaseT */
1050 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1051 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1052 RTL822X_VND2_C22_REG(MII_STAT1000));
1053 if (val < 0)
1054 return val;
1055 } else {
1056 val = 0;
1057 }
1058 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1059
1060 ret = genphy_c45_read_status(phydev);
1061 if (ret < 0)
1062 return ret;
1063
1064 if (!phydev->link) {
1065 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1066 return 0;
1067 }
1068
1069 /* Read actual speed from vendor register. */
1070 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1071 if (val < 0)
1072 return val;
1073
1074 rtlgen_decode_physr(phydev, val);
1075
1076 return 0;
1077 }
1078
rtl822xb_c45_read_status(struct phy_device * phydev)1079 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1080 {
1081 int ret;
1082
1083 ret = rtl822x_c45_read_status(phydev);
1084 if (ret < 0)
1085 return ret;
1086
1087 rtl822xb_update_interface(phydev);
1088
1089 return 0;
1090 }
1091
rtlgen_supports_2_5gbps(struct phy_device * phydev)1092 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1093 {
1094 int val;
1095
1096 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1097 val = phy_read(phydev, 0x13);
1098 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1099
1100 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1101 }
1102
1103 /* On internal PHY's MMD reads over C22 always return 0.
1104 * Check a MMD register which is known to be non-zero.
1105 */
rtlgen_supports_mmd(struct phy_device * phydev)1106 static bool rtlgen_supports_mmd(struct phy_device *phydev)
1107 {
1108 int val;
1109
1110 phy_lock_mdio_bus(phydev);
1111 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1112 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1113 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1114 val = __phy_read(phydev, MII_MMD_DATA);
1115 phy_unlock_mdio_bus(phydev);
1116
1117 return val > 0;
1118 }
1119
rtlgen_match_phy_device(struct phy_device * phydev)1120 static int rtlgen_match_phy_device(struct phy_device *phydev)
1121 {
1122 return phydev->phy_id == RTL_GENERIC_PHYID &&
1123 !rtlgen_supports_2_5gbps(phydev);
1124 }
1125
rtl8226_match_phy_device(struct phy_device * phydev)1126 static int rtl8226_match_phy_device(struct phy_device *phydev)
1127 {
1128 return phydev->phy_id == RTL_GENERIC_PHYID &&
1129 rtlgen_supports_2_5gbps(phydev) &&
1130 rtlgen_supports_mmd(phydev);
1131 }
1132
rtlgen_is_c45_match(struct phy_device * phydev,unsigned int id,bool is_c45)1133 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1134 bool is_c45)
1135 {
1136 if (phydev->is_c45)
1137 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1138 else
1139 return !is_c45 && (id == phydev->phy_id);
1140 }
1141
rtl8221b_match_phy_device(struct phy_device * phydev)1142 static int rtl8221b_match_phy_device(struct phy_device *phydev)
1143 {
1144 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1145 }
1146
rtl8221b_vb_cg_c22_match_phy_device(struct phy_device * phydev)1147 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1148 {
1149 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1150 }
1151
rtl8221b_vb_cg_c45_match_phy_device(struct phy_device * phydev)1152 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1153 {
1154 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1155 }
1156
rtl8221b_vn_cg_c22_match_phy_device(struct phy_device * phydev)1157 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1158 {
1159 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1160 }
1161
rtl8221b_vn_cg_c45_match_phy_device(struct phy_device * phydev)1162 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1163 {
1164 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1165 }
1166
rtl_internal_nbaset_match_phy_device(struct phy_device * phydev)1167 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
1168 {
1169 if (phydev->is_c45)
1170 return false;
1171
1172 switch (phydev->phy_id) {
1173 case RTL_GENERIC_PHYID:
1174 case RTL_8221B:
1175 case RTL_8251B:
1176 case 0x001cc841:
1177 break;
1178 default:
1179 return false;
1180 }
1181
1182 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1183 }
1184
rtl8251b_c45_match_phy_device(struct phy_device * phydev)1185 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1186 {
1187 return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1188 }
1189
rtlgen_resume(struct phy_device * phydev)1190 static int rtlgen_resume(struct phy_device *phydev)
1191 {
1192 int ret = genphy_resume(phydev);
1193
1194 /* Internal PHY's from RTL8168h up may not be instantly ready */
1195 msleep(20);
1196
1197 return ret;
1198 }
1199
rtlgen_c45_resume(struct phy_device * phydev)1200 static int rtlgen_c45_resume(struct phy_device *phydev)
1201 {
1202 int ret = genphy_c45_pma_resume(phydev);
1203
1204 msleep(20);
1205
1206 return ret;
1207 }
1208
rtl9000a_config_init(struct phy_device * phydev)1209 static int rtl9000a_config_init(struct phy_device *phydev)
1210 {
1211 phydev->autoneg = AUTONEG_DISABLE;
1212 phydev->speed = SPEED_100;
1213 phydev->duplex = DUPLEX_FULL;
1214
1215 return 0;
1216 }
1217
rtl9000a_config_aneg(struct phy_device * phydev)1218 static int rtl9000a_config_aneg(struct phy_device *phydev)
1219 {
1220 int ret;
1221 u16 ctl = 0;
1222
1223 switch (phydev->master_slave_set) {
1224 case MASTER_SLAVE_CFG_MASTER_FORCE:
1225 ctl |= CTL1000_AS_MASTER;
1226 break;
1227 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1228 break;
1229 case MASTER_SLAVE_CFG_UNKNOWN:
1230 case MASTER_SLAVE_CFG_UNSUPPORTED:
1231 return 0;
1232 default:
1233 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1234 return -EOPNOTSUPP;
1235 }
1236
1237 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1238 if (ret == 1)
1239 ret = genphy_soft_reset(phydev);
1240
1241 return ret;
1242 }
1243
rtl9000a_read_status(struct phy_device * phydev)1244 static int rtl9000a_read_status(struct phy_device *phydev)
1245 {
1246 int ret;
1247
1248 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1249 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1250
1251 ret = genphy_update_link(phydev);
1252 if (ret)
1253 return ret;
1254
1255 ret = phy_read(phydev, MII_CTRL1000);
1256 if (ret < 0)
1257 return ret;
1258 if (ret & CTL1000_AS_MASTER)
1259 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1260 else
1261 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1262
1263 ret = phy_read(phydev, MII_STAT1000);
1264 if (ret < 0)
1265 return ret;
1266 if (ret & LPA_1000MSRES)
1267 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1268 else
1269 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1270
1271 return 0;
1272 }
1273
rtl9000a_ack_interrupt(struct phy_device * phydev)1274 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1275 {
1276 int err;
1277
1278 err = phy_read(phydev, RTL8211F_INSR);
1279
1280 return (err < 0) ? err : 0;
1281 }
1282
rtl9000a_config_intr(struct phy_device * phydev)1283 static int rtl9000a_config_intr(struct phy_device *phydev)
1284 {
1285 u16 val;
1286 int err;
1287
1288 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1289 err = rtl9000a_ack_interrupt(phydev);
1290 if (err)
1291 return err;
1292
1293 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1294 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1295 } else {
1296 val = ~0;
1297 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1298 if (err)
1299 return err;
1300
1301 err = rtl9000a_ack_interrupt(phydev);
1302 }
1303
1304 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1305 }
1306
rtl9000a_handle_interrupt(struct phy_device * phydev)1307 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1308 {
1309 int irq_status;
1310
1311 irq_status = phy_read(phydev, RTL8211F_INSR);
1312 if (irq_status < 0) {
1313 phy_error(phydev);
1314 return IRQ_NONE;
1315 }
1316
1317 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1318 return IRQ_NONE;
1319
1320 phy_trigger_machine(phydev);
1321
1322 return IRQ_HANDLED;
1323 }
1324
1325 static struct phy_driver realtek_drvs[] = {
1326 {
1327 PHY_ID_MATCH_EXACT(0x00008201),
1328 .name = "RTL8201CP Ethernet",
1329 .read_page = rtl821x_read_page,
1330 .write_page = rtl821x_write_page,
1331 }, {
1332 PHY_ID_MATCH_EXACT(0x001cc816),
1333 .name = "RTL8201F Fast Ethernet",
1334 .config_intr = &rtl8201_config_intr,
1335 .handle_interrupt = rtl8201_handle_interrupt,
1336 .suspend = genphy_suspend,
1337 .resume = genphy_resume,
1338 .read_page = rtl821x_read_page,
1339 .write_page = rtl821x_write_page,
1340 }, {
1341 PHY_ID_MATCH_MODEL(0x001cc880),
1342 .name = "RTL8208 Fast Ethernet",
1343 .read_mmd = genphy_read_mmd_unsupported,
1344 .write_mmd = genphy_write_mmd_unsupported,
1345 .suspend = genphy_suspend,
1346 .resume = genphy_resume,
1347 .read_page = rtl821x_read_page,
1348 .write_page = rtl821x_write_page,
1349 }, {
1350 PHY_ID_MATCH_EXACT(0x001cc910),
1351 .name = "RTL8211 Gigabit Ethernet",
1352 .config_aneg = rtl8211_config_aneg,
1353 .read_mmd = &genphy_read_mmd_unsupported,
1354 .write_mmd = &genphy_write_mmd_unsupported,
1355 .read_page = rtl821x_read_page,
1356 .write_page = rtl821x_write_page,
1357 }, {
1358 PHY_ID_MATCH_EXACT(0x001cc912),
1359 .name = "RTL8211B Gigabit Ethernet",
1360 .config_intr = &rtl8211b_config_intr,
1361 .handle_interrupt = rtl821x_handle_interrupt,
1362 .read_mmd = &genphy_read_mmd_unsupported,
1363 .write_mmd = &genphy_write_mmd_unsupported,
1364 .suspend = rtl8211b_suspend,
1365 .resume = rtl8211b_resume,
1366 .read_page = rtl821x_read_page,
1367 .write_page = rtl821x_write_page,
1368 }, {
1369 PHY_ID_MATCH_EXACT(0x001cc913),
1370 .name = "RTL8211C Gigabit Ethernet",
1371 .config_init = rtl8211c_config_init,
1372 .read_mmd = &genphy_read_mmd_unsupported,
1373 .write_mmd = &genphy_write_mmd_unsupported,
1374 .read_page = rtl821x_read_page,
1375 .write_page = rtl821x_write_page,
1376 }, {
1377 PHY_ID_MATCH_EXACT(0x001cc914),
1378 .name = "RTL8211DN Gigabit Ethernet",
1379 .config_intr = rtl8211e_config_intr,
1380 .handle_interrupt = rtl821x_handle_interrupt,
1381 .suspend = genphy_suspend,
1382 .resume = genphy_resume,
1383 .read_page = rtl821x_read_page,
1384 .write_page = rtl821x_write_page,
1385 }, {
1386 PHY_ID_MATCH_EXACT(0x001cc915),
1387 .name = "RTL8211E Gigabit Ethernet",
1388 .config_init = &rtl8211e_config_init,
1389 .config_intr = &rtl8211e_config_intr,
1390 .handle_interrupt = rtl821x_handle_interrupt,
1391 .suspend = genphy_suspend,
1392 .resume = genphy_resume,
1393 .read_page = rtl821x_read_page,
1394 .write_page = rtl821x_write_page,
1395 }, {
1396 PHY_ID_MATCH_EXACT(0x001cc916),
1397 .name = "RTL8211F Gigabit Ethernet",
1398 .probe = rtl821x_probe,
1399 .config_init = &rtl8211f_config_init,
1400 .read_status = rtlgen_read_status,
1401 .config_intr = &rtl8211f_config_intr,
1402 .handle_interrupt = rtl8211f_handle_interrupt,
1403 .suspend = rtl821x_suspend,
1404 .resume = rtl821x_resume,
1405 .read_page = rtl821x_read_page,
1406 .write_page = rtl821x_write_page,
1407 .flags = PHY_ALWAYS_CALL_SUSPEND,
1408 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1409 .led_hw_control_get = rtl8211f_led_hw_control_get,
1410 .led_hw_control_set = rtl8211f_led_hw_control_set,
1411 }, {
1412 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1413 .name = "RTL8211F-VD Gigabit Ethernet",
1414 .probe = rtl821x_probe,
1415 .config_init = &rtl8211f_config_init,
1416 .read_status = rtlgen_read_status,
1417 .config_intr = &rtl8211f_config_intr,
1418 .handle_interrupt = rtl8211f_handle_interrupt,
1419 .suspend = rtl821x_suspend,
1420 .resume = rtl821x_resume,
1421 .read_page = rtl821x_read_page,
1422 .write_page = rtl821x_write_page,
1423 .flags = PHY_ALWAYS_CALL_SUSPEND,
1424 }, {
1425 .name = "Generic FE-GE Realtek PHY",
1426 .match_phy_device = rtlgen_match_phy_device,
1427 .read_status = rtlgen_read_status,
1428 .suspend = genphy_suspend,
1429 .resume = rtlgen_resume,
1430 .read_page = rtl821x_read_page,
1431 .write_page = rtl821x_write_page,
1432 .read_mmd = rtlgen_read_mmd,
1433 .write_mmd = rtlgen_write_mmd,
1434 }, {
1435 .name = "RTL8226 2.5Gbps PHY",
1436 .match_phy_device = rtl8226_match_phy_device,
1437 .get_features = rtl822x_get_features,
1438 .config_aneg = rtl822x_config_aneg,
1439 .read_status = rtl822x_read_status,
1440 .suspend = genphy_suspend,
1441 .resume = rtlgen_resume,
1442 .read_page = rtl821x_read_page,
1443 .write_page = rtl821x_write_page,
1444 }, {
1445 .match_phy_device = rtl8221b_match_phy_device,
1446 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1447 .get_features = rtl822x_get_features,
1448 .config_aneg = rtl822x_config_aneg,
1449 .config_init = rtl822xb_config_init,
1450 .get_rate_matching = rtl822xb_get_rate_matching,
1451 .read_status = rtl822xb_read_status,
1452 .suspend = genphy_suspend,
1453 .resume = rtlgen_resume,
1454 .read_page = rtl821x_read_page,
1455 .write_page = rtl821x_write_page,
1456 }, {
1457 PHY_ID_MATCH_EXACT(0x001cc838),
1458 .name = "RTL8226-CG 2.5Gbps PHY",
1459 .get_features = rtl822x_get_features,
1460 .config_aneg = rtl822x_config_aneg,
1461 .read_status = rtl822x_read_status,
1462 .suspend = genphy_suspend,
1463 .resume = rtlgen_resume,
1464 .read_page = rtl821x_read_page,
1465 .write_page = rtl821x_write_page,
1466 }, {
1467 PHY_ID_MATCH_EXACT(0x001cc848),
1468 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1469 .get_features = rtl822x_get_features,
1470 .config_aneg = rtl822x_config_aneg,
1471 .config_init = rtl822xb_config_init,
1472 .get_rate_matching = rtl822xb_get_rate_matching,
1473 .read_status = rtl822xb_read_status,
1474 .suspend = genphy_suspend,
1475 .resume = rtlgen_resume,
1476 .read_page = rtl821x_read_page,
1477 .write_page = rtl821x_write_page,
1478 }, {
1479 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1480 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1481 .probe = rtl822x_probe,
1482 .get_features = rtl822x_get_features,
1483 .config_aneg = rtl822x_config_aneg,
1484 .config_init = rtl822xb_config_init,
1485 .get_rate_matching = rtl822xb_get_rate_matching,
1486 .read_status = rtl822xb_read_status,
1487 .suspend = genphy_suspend,
1488 .resume = rtlgen_resume,
1489 .read_page = rtl821x_read_page,
1490 .write_page = rtl821x_write_page,
1491 }, {
1492 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1493 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1494 .probe = rtl822x_probe,
1495 .config_init = rtl822xb_config_init,
1496 .get_rate_matching = rtl822xb_get_rate_matching,
1497 .get_features = rtl822x_c45_get_features,
1498 .config_aneg = rtl822x_c45_config_aneg,
1499 .read_status = rtl822xb_c45_read_status,
1500 .suspend = genphy_c45_pma_suspend,
1501 .resume = rtlgen_c45_resume,
1502 }, {
1503 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1504 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1505 .probe = rtl822x_probe,
1506 .get_features = rtl822x_get_features,
1507 .config_aneg = rtl822x_config_aneg,
1508 .config_init = rtl822xb_config_init,
1509 .get_rate_matching = rtl822xb_get_rate_matching,
1510 .read_status = rtl822xb_read_status,
1511 .suspend = genphy_suspend,
1512 .resume = rtlgen_resume,
1513 .read_page = rtl821x_read_page,
1514 .write_page = rtl821x_write_page,
1515 }, {
1516 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1517 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1518 .probe = rtl822x_probe,
1519 .config_init = rtl822xb_config_init,
1520 .get_rate_matching = rtl822xb_get_rate_matching,
1521 .get_features = rtl822x_c45_get_features,
1522 .config_aneg = rtl822x_c45_config_aneg,
1523 .read_status = rtl822xb_c45_read_status,
1524 .suspend = genphy_c45_pma_suspend,
1525 .resume = rtlgen_c45_resume,
1526 }, {
1527 .match_phy_device = rtl8251b_c45_match_phy_device,
1528 .name = "RTL8251B 5Gbps PHY",
1529 .probe = rtl822x_probe,
1530 .get_features = rtl822x_get_features,
1531 .config_aneg = rtl822x_config_aneg,
1532 .read_status = rtl822x_read_status,
1533 .suspend = genphy_suspend,
1534 .resume = rtlgen_resume,
1535 .read_page = rtl821x_read_page,
1536 .write_page = rtl821x_write_page,
1537 }, {
1538 .match_phy_device = rtl_internal_nbaset_match_phy_device,
1539 .name = "Realtek Internal NBASE-T PHY",
1540 .flags = PHY_IS_INTERNAL,
1541 .probe = rtl822x_probe,
1542 .get_features = rtl822x_get_features,
1543 .config_aneg = rtl822x_config_aneg,
1544 .read_status = rtl822x_read_status,
1545 .suspend = genphy_suspend,
1546 .resume = rtlgen_resume,
1547 .read_page = rtl821x_read_page,
1548 .write_page = rtl821x_write_page,
1549 .read_mmd = rtl822x_read_mmd,
1550 .write_mmd = rtl822x_write_mmd,
1551 }, {
1552 PHY_ID_MATCH_EXACT(0x001ccad0),
1553 .name = "RTL8224 2.5Gbps PHY",
1554 .get_features = rtl822x_c45_get_features,
1555 .config_aneg = rtl822x_c45_config_aneg,
1556 .read_status = rtl822x_c45_read_status,
1557 .suspend = genphy_c45_pma_suspend,
1558 .resume = rtlgen_c45_resume,
1559 }, {
1560 PHY_ID_MATCH_EXACT(0x001cc961),
1561 .name = "RTL8366RB Gigabit Ethernet",
1562 .config_init = &rtl8366rb_config_init,
1563 /* These interrupts are handled by the irq controller
1564 * embedded inside the RTL8366RB, they get unmasked when the
1565 * irq is requested and ACKed by reading the status register,
1566 * which is done by the irqchip code.
1567 */
1568 .config_intr = genphy_no_config_intr,
1569 .handle_interrupt = genphy_handle_interrupt_no_ack,
1570 .suspend = genphy_suspend,
1571 .resume = genphy_resume,
1572 }, {
1573 PHY_ID_MATCH_EXACT(0x001ccb00),
1574 .name = "RTL9000AA_RTL9000AN Ethernet",
1575 .features = PHY_BASIC_T1_FEATURES,
1576 .config_init = rtl9000a_config_init,
1577 .config_aneg = rtl9000a_config_aneg,
1578 .read_status = rtl9000a_read_status,
1579 .config_intr = rtl9000a_config_intr,
1580 .handle_interrupt = rtl9000a_handle_interrupt,
1581 .suspend = genphy_suspend,
1582 .resume = genphy_resume,
1583 .read_page = rtl821x_read_page,
1584 .write_page = rtl821x_write_page,
1585 }, {
1586 PHY_ID_MATCH_EXACT(0x001cc942),
1587 .name = "RTL8365MB-VC Gigabit Ethernet",
1588 /* Interrupt handling analogous to RTL8366RB */
1589 .config_intr = genphy_no_config_intr,
1590 .handle_interrupt = genphy_handle_interrupt_no_ack,
1591 .suspend = genphy_suspend,
1592 .resume = genphy_resume,
1593 }, {
1594 PHY_ID_MATCH_EXACT(0x001cc960),
1595 .name = "RTL8366S Gigabit Ethernet",
1596 .suspend = genphy_suspend,
1597 .resume = genphy_resume,
1598 .read_mmd = genphy_read_mmd_unsupported,
1599 .write_mmd = genphy_write_mmd_unsupported,
1600 },
1601 };
1602
1603 module_phy_driver(realtek_drvs);
1604
1605 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1606 { PHY_ID_MATCH_VENDOR(0x001cc800) },
1607 { }
1608 };
1609
1610 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1611