1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10 #include <linux/bitops.h>
11 #include <linux/ethtool_netlink.h>
12 #include <linux/of.h>
13 #include <linux/phy.h>
14 #include <linux/pm_wakeirq.h>
15 #include <linux/netdevice.h>
16 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/string_choices.h>
20
21 #include "realtek.h"
22
23 #define RTL8201F_IER 0x13
24
25 #define RTL8201F_ISR 0x1e
26 #define RTL8201F_ISR_ANERR BIT(15)
27 #define RTL8201F_ISR_DUPLEX BIT(13)
28 #define RTL8201F_ISR_LINK BIT(11)
29 #define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
30 RTL8201F_ISR_DUPLEX | \
31 RTL8201F_ISR_LINK)
32
33 #define RTL821x_INER 0x12
34 #define RTL8211B_INER_INIT 0x6400
35 #define RTL8211E_INER_LINK_STATUS BIT(10)
36 #define RTL8211F_INER_PME BIT(7)
37 #define RTL8211F_INER_LINK_STATUS BIT(4)
38
39 #define RTL821x_INSR 0x13
40
41 #define RTL821x_EXT_PAGE_SELECT 0x1e
42
43 #define RTL821x_PAGE_SELECT 0x1f
44 #define RTL821x_SET_EXT_PAGE 0x07
45
46 /* RTL8211E extension page 44/0x2c */
47 #define RTL8211E_LEDCR_EXT_PAGE 0x2c
48 #define RTL8211E_LEDCR1 0x1a
49 #define RTL8211E_LEDCR1_ACT_TXRX BIT(4)
50 #define RTL8211E_LEDCR1_MASK BIT(4)
51 #define RTL8211E_LEDCR1_SHIFT 1
52
53 #define RTL8211E_LEDCR2 0x1c
54 #define RTL8211E_LEDCR2_LINK_1000 BIT(2)
55 #define RTL8211E_LEDCR2_LINK_100 BIT(1)
56 #define RTL8211E_LEDCR2_LINK_10 BIT(0)
57 #define RTL8211E_LEDCR2_MASK GENMASK(2, 0)
58 #define RTL8211E_LEDCR2_SHIFT 4
59
60 /* RTL8211E extension page 164/0xa4 */
61 #define RTL8211E_RGMII_EXT_PAGE 0xa4
62 #define RTL8211E_RGMII_DELAY 0x1c
63 #define RTL8211E_CTRL_DELAY BIT(13)
64 #define RTL8211E_TX_DELAY BIT(12)
65 #define RTL8211E_RX_DELAY BIT(11)
66 #define RTL8211E_DELAY_MASK GENMASK(13, 11)
67
68 /* RTL8211F PHY configuration */
69 #define RTL8211F_PHYCR_PAGE 0xa43
70 #define RTL8211F_PHYCR1 0x18
71 #define RTL8211F_ALDPS_PLL_OFF BIT(1)
72 #define RTL8211F_ALDPS_ENABLE BIT(2)
73 #define RTL8211F_ALDPS_XTAL_OFF BIT(12)
74
75 #define RTL8211F_PHYCR2 0x19
76 #define RTL8211F_CLKOUT_EN BIT(0)
77 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5)
78
79 #define RTL8211F_INSR_PAGE 0xa43
80 #define RTL8211F_INSR 0x1d
81
82 /* RTL8211F LED configuration */
83 #define RTL8211F_LEDCR_PAGE 0xd04
84 #define RTL8211F_LEDCR 0x10
85 #define RTL8211F_LEDCR_MODE BIT(15)
86 #define RTL8211F_LEDCR_ACT_TXRX BIT(4)
87 #define RTL8211F_LEDCR_LINK_1000 BIT(3)
88 #define RTL8211F_LEDCR_LINK_100 BIT(1)
89 #define RTL8211F_LEDCR_LINK_10 BIT(0)
90 #define RTL8211F_LEDCR_MASK GENMASK(4, 0)
91 #define RTL8211F_LEDCR_SHIFT 5
92
93 /* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values
94 * to undocumented register pages. The names here do not reflect the datasheet.
95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2.
96 */
97 #define RTL8211FVD_CLKOUT_PAGE 0xd05
98 #define RTL8211FVD_CLKOUT_REG 0x11
99 #define RTL8211FVD_CLKOUT_EN BIT(8)
100
101 /* RTL8211F RGMII configuration */
102 #define RTL8211F_RGMII_PAGE 0xd08
103
104 #define RTL8211F_TXCR 0x11
105 #define RTL8211F_TX_DELAY BIT(8)
106
107 #define RTL8211F_RXCR 0x15
108 #define RTL8211F_RX_DELAY BIT(3)
109
110 /* RTL8211F WOL settings */
111 #define RTL8211F_WOL_PAGE 0xd8a
112 #define RTL8211F_WOL_SETTINGS_EVENTS 16
113 #define RTL8211F_WOL_EVENT_MAGIC BIT(12)
114 #define RTL8211F_WOL_RST_RMSQ 17
115 #define RTL8211F_WOL_RG_RSTB BIT(15)
116 #define RTL8211F_WOL_RMSQ 0x1fff
117
118 /* RTL8211F Unique phyiscal and multicast address (WOL) */
119 #define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c
120 #define RTL8211F_PHYSICAL_ADDR_WORD0 16
121 #define RTL8211F_PHYSICAL_ADDR_WORD1 17
122 #define RTL8211F_PHYSICAL_ADDR_WORD2 18
123
124 #define RTL822X_VND1_SERDES_OPTION 0x697a
125 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
126 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
127 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
128
129 #define RTL822X_VND1_SERDES_CTRL3 0x7580
130 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
131 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
132 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
133
134 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
135 * is set, they cannot be accessed by C45-over-C22.
136 */
137 #define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg))
138
139 #define RTL8221B_VND2_INER 0xa4d2
140 #define RTL8221B_VND2_INER_LINK_STATUS BIT(4)
141
142 #define RTL8221B_VND2_INSR 0xa4d4
143
144 #define RTL8224_MII_RTCT 0x11
145 #define RTL8224_MII_RTCT_ENABLE BIT(0)
146 #define RTL8224_MII_RTCT_PAIR_A BIT(4)
147 #define RTL8224_MII_RTCT_PAIR_B BIT(5)
148 #define RTL8224_MII_RTCT_PAIR_C BIT(6)
149 #define RTL8224_MII_RTCT_PAIR_D BIT(7)
150 #define RTL8224_MII_RTCT_DONE BIT(15)
151
152 #define RTL8224_MII_SRAM_ADDR 0x1b
153 #define RTL8224_MII_SRAM_DATA 0x1c
154
155 #define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4)
156 #define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0)
157 #define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3)
158 #define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4)
159 #define RTL8224_SRAM_RTCT_FAULT_OK BIT(5)
160 #define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6)
161 #define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7)
162
163 #define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
164
165 #define RTL8366RB_POWER_SAVE 0x15
166 #define RTL8366RB_POWER_SAVE_ON BIT(12)
167
168 #define RTL9000A_GINMR 0x14
169 #define RTL9000A_GINMR_LINK_STATUS BIT(4)
170
171 #define RTL_VND2_PHYSR 0xa434
172 #define RTL_VND2_PHYSR_DUPLEX BIT(3)
173 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
174 #define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
175 #define RTL_VND2_PHYSR_MASTER BIT(11)
176 #define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
177
178 #define RTL_MDIO_PCS_EEE_ABLE 0xa5c4
179 #define RTL_MDIO_AN_EEE_ADV 0xa5d0
180 #define RTL_MDIO_AN_EEE_LPABLE 0xa5d2
181 #define RTL_MDIO_AN_10GBT_CTRL 0xa5d4
182 #define RTL_MDIO_AN_10GBT_STAT 0xa5d6
183 #define RTL_MDIO_PMA_SPEED 0xa616
184 #define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0
185 #define RTL_MDIO_AN_EEE_ADV2 0xa6d4
186 #define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec
187
188 #define RTL_GENERIC_PHYID 0x001cc800
189 #define RTL_8211FVD_PHYID 0x001cc878
190 #define RTL_8221B 0x001cc840
191 #define RTL_8221B_VB_CG 0x001cc849
192 #define RTL_8221B_VM_CG 0x001cc84a
193 #define RTL_8251B 0x001cc862
194 #define RTL_8261C 0x001cc890
195
196 /* RTL8211E and RTL8211F support up to three LEDs */
197 #define RTL8211x_LED_COUNT 3
198
199 MODULE_DESCRIPTION("Realtek PHY driver");
200 MODULE_AUTHOR("Johnson Leung");
201 MODULE_LICENSE("GPL");
202
203 struct rtl821x_priv {
204 bool enable_aldps;
205 bool disable_clk_out;
206 struct clk *clk;
207 /* rtl8211f */
208 u16 iner;
209 };
210
rtl821x_read_page(struct phy_device * phydev)211 static int rtl821x_read_page(struct phy_device *phydev)
212 {
213 return __phy_read(phydev, RTL821x_PAGE_SELECT);
214 }
215
rtl821x_write_page(struct phy_device * phydev,int page)216 static int rtl821x_write_page(struct phy_device *phydev, int page)
217 {
218 return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
219 }
220
rtl821x_read_ext_page(struct phy_device * phydev,u16 ext_page,u32 regnum)221 static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page,
222 u32 regnum)
223 {
224 int oldpage, ret = 0;
225
226 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
227 if (oldpage >= 0) {
228 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
229 if (ret == 0)
230 ret = __phy_read(phydev, regnum);
231 }
232
233 return phy_restore_page(phydev, oldpage, ret);
234 }
235
rtl821x_modify_ext_page(struct phy_device * phydev,u16 ext_page,u32 regnum,u16 mask,u16 set)236 static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
237 u32 regnum, u16 mask, u16 set)
238 {
239 int oldpage, ret = 0;
240
241 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
242 if (oldpage >= 0) {
243 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, ext_page);
244 if (ret == 0)
245 ret = __phy_modify(phydev, regnum, mask, set);
246 }
247
248 return phy_restore_page(phydev, oldpage, ret);
249 }
250
rtl821x_probe(struct phy_device * phydev)251 static int rtl821x_probe(struct phy_device *phydev)
252 {
253 struct device *dev = &phydev->mdio.dev;
254 struct rtl821x_priv *priv;
255
256 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
257 if (!priv)
258 return -ENOMEM;
259
260 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
261 if (IS_ERR(priv->clk))
262 return dev_err_probe(dev, PTR_ERR(priv->clk),
263 "failed to get phy clock\n");
264
265 priv->enable_aldps = of_property_read_bool(dev->of_node,
266 "realtek,aldps-enable");
267 priv->disable_clk_out = of_property_read_bool(dev->of_node,
268 "realtek,clkout-disable");
269
270 phydev->priv = priv;
271
272 return 0;
273 }
274
rtl8211f_probe(struct phy_device * phydev)275 static int rtl8211f_probe(struct phy_device *phydev)
276 {
277 struct device *dev = &phydev->mdio.dev;
278 int ret;
279
280 ret = rtl821x_probe(phydev);
281 if (ret < 0)
282 return ret;
283
284 /* Disable all PME events */
285 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
286 RTL8211F_WOL_SETTINGS_EVENTS, 0);
287 if (ret < 0)
288 return ret;
289
290 /* Mark this PHY as wakeup capable and register the interrupt as a
291 * wakeup IRQ if the PHY is marked as a wakeup source in firmware,
292 * and the interrupt is valid.
293 */
294 if (device_property_read_bool(dev, "wakeup-source") &&
295 phy_interrupt_is_valid(phydev)) {
296 device_set_wakeup_capable(dev, true);
297 devm_pm_set_wake_irq(dev, phydev->irq);
298 }
299
300 return ret;
301 }
302
rtl8201_ack_interrupt(struct phy_device * phydev)303 static int rtl8201_ack_interrupt(struct phy_device *phydev)
304 {
305 int err;
306
307 err = phy_read(phydev, RTL8201F_ISR);
308
309 return (err < 0) ? err : 0;
310 }
311
rtl821x_ack_interrupt(struct phy_device * phydev)312 static int rtl821x_ack_interrupt(struct phy_device *phydev)
313 {
314 int err;
315
316 err = phy_read(phydev, RTL821x_INSR);
317
318 return (err < 0) ? err : 0;
319 }
320
rtl8211f_ack_interrupt(struct phy_device * phydev)321 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
322 {
323 int err;
324
325 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
326
327 return (err < 0) ? err : 0;
328 }
329
rtl8201_config_intr(struct phy_device * phydev)330 static int rtl8201_config_intr(struct phy_device *phydev)
331 {
332 u16 val;
333 int err;
334
335 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
336 err = rtl8201_ack_interrupt(phydev);
337 if (err)
338 return err;
339
340 val = BIT(13) | BIT(12) | BIT(11);
341 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
342 } else {
343 val = 0;
344 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
345 if (err)
346 return err;
347
348 err = rtl8201_ack_interrupt(phydev);
349 }
350
351 return err;
352 }
353
rtl8211b_config_intr(struct phy_device * phydev)354 static int rtl8211b_config_intr(struct phy_device *phydev)
355 {
356 int err;
357
358 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
359 err = rtl821x_ack_interrupt(phydev);
360 if (err)
361 return err;
362
363 err = phy_write(phydev, RTL821x_INER,
364 RTL8211B_INER_INIT);
365 } else {
366 err = phy_write(phydev, RTL821x_INER, 0);
367 if (err)
368 return err;
369
370 err = rtl821x_ack_interrupt(phydev);
371 }
372
373 return err;
374 }
375
rtl8211e_config_intr(struct phy_device * phydev)376 static int rtl8211e_config_intr(struct phy_device *phydev)
377 {
378 int err;
379
380 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
381 err = rtl821x_ack_interrupt(phydev);
382 if (err)
383 return err;
384
385 err = phy_write(phydev, RTL821x_INER,
386 RTL8211E_INER_LINK_STATUS);
387 } else {
388 err = phy_write(phydev, RTL821x_INER, 0);
389 if (err)
390 return err;
391
392 err = rtl821x_ack_interrupt(phydev);
393 }
394
395 return err;
396 }
397
rtl8211f_config_intr(struct phy_device * phydev)398 static int rtl8211f_config_intr(struct phy_device *phydev)
399 {
400 struct rtl821x_priv *priv = phydev->priv;
401 u16 val;
402 int err;
403
404 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
405 err = rtl8211f_ack_interrupt(phydev);
406 if (err)
407 return err;
408
409 val = RTL8211F_INER_LINK_STATUS;
410 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
411 if (err == 0)
412 priv->iner = val;
413 } else {
414 priv->iner = val = 0;
415 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
416 if (err)
417 return err;
418
419 err = rtl8211f_ack_interrupt(phydev);
420 }
421
422 return err;
423 }
424
rtl8201_handle_interrupt(struct phy_device * phydev)425 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
426 {
427 int irq_status;
428
429 irq_status = phy_read(phydev, RTL8201F_ISR);
430 if (irq_status < 0) {
431 phy_error(phydev);
432 return IRQ_NONE;
433 }
434
435 if (!(irq_status & RTL8201F_ISR_MASK))
436 return IRQ_NONE;
437
438 phy_trigger_machine(phydev);
439
440 return IRQ_HANDLED;
441 }
442
rtl821x_handle_interrupt(struct phy_device * phydev)443 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
444 {
445 int irq_status, irq_enabled;
446
447 irq_status = phy_read(phydev, RTL821x_INSR);
448 if (irq_status < 0) {
449 phy_error(phydev);
450 return IRQ_NONE;
451 }
452
453 irq_enabled = phy_read(phydev, RTL821x_INER);
454 if (irq_enabled < 0) {
455 phy_error(phydev);
456 return IRQ_NONE;
457 }
458
459 if (!(irq_status & irq_enabled))
460 return IRQ_NONE;
461
462 phy_trigger_machine(phydev);
463
464 return IRQ_HANDLED;
465 }
466
rtl8211f_handle_interrupt(struct phy_device * phydev)467 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
468 {
469 int irq_status;
470
471 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
472 if (irq_status < 0) {
473 phy_error(phydev);
474 return IRQ_NONE;
475 }
476
477 if (irq_status & RTL8211F_INER_LINK_STATUS) {
478 phy_trigger_machine(phydev);
479 return IRQ_HANDLED;
480 }
481
482 if (irq_status & RTL8211F_INER_PME) {
483 pm_wakeup_event(&phydev->mdio.dev, 0);
484 return IRQ_HANDLED;
485 }
486
487 return IRQ_NONE;
488 }
489
rtl8211f_get_wol(struct phy_device * dev,struct ethtool_wolinfo * wol)490 static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
491 {
492 int wol_events;
493
494 /* If the PHY is not capable of waking the system, then WoL can not
495 * be supported.
496 */
497 if (!device_can_wakeup(&dev->mdio.dev)) {
498 wol->supported = 0;
499 return;
500 }
501
502 wol->supported = WAKE_MAGIC;
503
504 wol_events = phy_read_paged(dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS);
505 if (wol_events < 0)
506 return;
507
508 if (wol_events & RTL8211F_WOL_EVENT_MAGIC)
509 wol->wolopts = WAKE_MAGIC;
510 }
511
rtl8211f_set_wol(struct phy_device * dev,struct ethtool_wolinfo * wol)512 static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
513 {
514 const u8 *mac_addr = dev->attached_dev->dev_addr;
515 int oldpage;
516
517 if (!device_can_wakeup(&dev->mdio.dev))
518 return -EOPNOTSUPP;
519
520 oldpage = phy_save_page(dev);
521 if (oldpage < 0)
522 goto err;
523
524 if (wol->wolopts & WAKE_MAGIC) {
525 /* Store the device address for the magic packet */
526 rtl821x_write_page(dev, RTL8211F_PHYSICAL_ADDR_PAGE);
527 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD0, mac_addr[1] << 8 | (mac_addr[0]));
528 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD1, mac_addr[3] << 8 | (mac_addr[2]));
529 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4]));
530
531 /* Enable magic packet matching */
532 rtl821x_write_page(dev, RTL8211F_WOL_PAGE);
533 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC);
534 /* Set the maximum packet size, and assert WoL reset */
535 __phy_write(dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ);
536 } else {
537 /* Disable magic packet matching */
538 rtl821x_write_page(dev, RTL8211F_WOL_PAGE);
539 __phy_write(dev, RTL8211F_WOL_SETTINGS_EVENTS, 0);
540
541 /* Place WoL in reset */
542 __phy_clear_bits(dev, RTL8211F_WOL_RST_RMSQ,
543 RTL8211F_WOL_RG_RSTB);
544 }
545
546 device_set_wakeup_enable(&dev->mdio.dev, !!(wol->wolopts & WAKE_MAGIC));
547
548 err:
549 return phy_restore_page(dev, oldpage, 0);
550 }
551
rtl8211_config_aneg(struct phy_device * phydev)552 static int rtl8211_config_aneg(struct phy_device *phydev)
553 {
554 int ret;
555
556 ret = genphy_config_aneg(phydev);
557 if (ret < 0)
558 return ret;
559
560 /* Quirk was copied from vendor driver. Unfortunately it includes no
561 * description of the magic numbers.
562 */
563 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
564 phy_write(phydev, 0x17, 0x2138);
565 phy_write(phydev, 0x0e, 0x0260);
566 } else {
567 phy_write(phydev, 0x17, 0x2108);
568 phy_write(phydev, 0x0e, 0x0000);
569 }
570
571 return 0;
572 }
573
rtl8211c_config_init(struct phy_device * phydev)574 static int rtl8211c_config_init(struct phy_device *phydev)
575 {
576 /* RTL8211C has an issue when operating in Gigabit slave mode */
577 return phy_set_bits(phydev, MII_CTRL1000,
578 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
579 }
580
rtl8211f_config_rgmii_delay(struct phy_device * phydev)581 static int rtl8211f_config_rgmii_delay(struct phy_device *phydev)
582 {
583 u16 val_txdly, val_rxdly;
584 int ret;
585
586 switch (phydev->interface) {
587 case PHY_INTERFACE_MODE_RGMII:
588 val_txdly = 0;
589 val_rxdly = 0;
590 break;
591
592 case PHY_INTERFACE_MODE_RGMII_RXID:
593 val_txdly = 0;
594 val_rxdly = RTL8211F_RX_DELAY;
595 break;
596
597 case PHY_INTERFACE_MODE_RGMII_TXID:
598 val_txdly = RTL8211F_TX_DELAY;
599 val_rxdly = 0;
600 break;
601
602 case PHY_INTERFACE_MODE_RGMII_ID:
603 val_txdly = RTL8211F_TX_DELAY;
604 val_rxdly = RTL8211F_RX_DELAY;
605 break;
606
607 default: /* the rest of the modes imply leaving delay as is. */
608 return 0;
609 }
610
611 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
612 RTL8211F_TXCR, RTL8211F_TX_DELAY,
613 val_txdly);
614 if (ret < 0) {
615 phydev_err(phydev, "Failed to update the TX delay register: %pe\n",
616 ERR_PTR(ret));
617 return ret;
618 } else if (ret) {
619 phydev_dbg(phydev,
620 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
621 str_enable_disable(val_txdly));
622 } else {
623 phydev_dbg(phydev,
624 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
625 str_enabled_disabled(val_txdly));
626 }
627
628 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
629 RTL8211F_RXCR, RTL8211F_RX_DELAY,
630 val_rxdly);
631 if (ret < 0) {
632 phydev_err(phydev, "Failed to update the RX delay register: %pe\n",
633 ERR_PTR(ret));
634 return ret;
635 } else if (ret) {
636 phydev_dbg(phydev,
637 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
638 str_enable_disable(val_rxdly));
639 } else {
640 phydev_dbg(phydev,
641 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
642 str_enabled_disabled(val_rxdly));
643 }
644
645 return 0;
646 }
647
rtl8211f_config_clk_out(struct phy_device * phydev)648 static int rtl8211f_config_clk_out(struct phy_device *phydev)
649 {
650 struct rtl821x_priv *priv = phydev->priv;
651 int ret;
652
653 /* The value is preserved if the device tree property is absent */
654 if (!priv->disable_clk_out)
655 return 0;
656
657 if (phydev->drv->phy_id == RTL_8211FVD_PHYID)
658 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE,
659 RTL8211FVD_CLKOUT_REG,
660 RTL8211FVD_CLKOUT_EN, 0);
661 else
662 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
663 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 0);
664 if (ret)
665 return ret;
666
667 return genphy_soft_reset(phydev);
668 }
669
670 /* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour,
671 * which causes the RXC clock signal to stop for tens to hundreds of
672 * milliseconds.
673 *
674 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is
675 * only enabled based on an opt-in device tree property.
676 */
rtl8211f_config_aldps(struct phy_device * phydev)677 static int rtl8211f_config_aldps(struct phy_device *phydev)
678 {
679 struct rtl821x_priv *priv = phydev->priv;
680 u16 mask = RTL8211F_ALDPS_PLL_OFF |
681 RTL8211F_ALDPS_ENABLE |
682 RTL8211F_ALDPS_XTAL_OFF;
683
684 /* The value is preserved if the device tree property is absent */
685 if (!priv->enable_aldps)
686 return 0;
687
688 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
689 mask, mask);
690 }
691
rtl8211f_config_phy_eee(struct phy_device * phydev)692 static int rtl8211f_config_phy_eee(struct phy_device *phydev)
693 {
694 /* RTL8211FVD has no PHYCR2 register */
695 if (phydev->drv->phy_id == RTL_8211FVD_PHYID)
696 return 0;
697
698 /* Disable PHY-mode EEE so LPI is passed to the MAC */
699 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
700 RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
701 }
702
rtl8211f_config_init(struct phy_device * phydev)703 static int rtl8211f_config_init(struct phy_device *phydev)
704 {
705 struct device *dev = &phydev->mdio.dev;
706 int ret;
707
708 ret = rtl8211f_config_aldps(phydev);
709 if (ret) {
710 dev_err(dev, "aldps mode configuration failed: %pe\n",
711 ERR_PTR(ret));
712 return ret;
713 }
714
715 ret = rtl8211f_config_rgmii_delay(phydev);
716 if (ret)
717 return ret;
718
719 ret = rtl8211f_config_clk_out(phydev);
720 if (ret) {
721 dev_err(dev, "clkout configuration failed: %pe\n",
722 ERR_PTR(ret));
723 return ret;
724 }
725
726 return rtl8211f_config_phy_eee(phydev);
727 }
728
rtl821x_suspend(struct phy_device * phydev)729 static int rtl821x_suspend(struct phy_device *phydev)
730 {
731 struct rtl821x_priv *priv = phydev->priv;
732 int ret = 0;
733
734 if (!phydev->wol_enabled) {
735 ret = genphy_suspend(phydev);
736
737 if (ret)
738 return ret;
739
740 clk_disable_unprepare(priv->clk);
741 }
742
743 return ret;
744 }
745
rtl8211f_suspend(struct phy_device * phydev)746 static int rtl8211f_suspend(struct phy_device *phydev)
747 {
748 u16 wol_rst;
749 int ret;
750
751 ret = rtl821x_suspend(phydev);
752 if (ret < 0)
753 return ret;
754
755 /* If a PME event is enabled, then configure the interrupt for
756 * PME events only, disabling link interrupt. We avoid switching
757 * to PMEB mode as we don't have a status bit for that.
758 */
759 if (device_may_wakeup(&phydev->mdio.dev)) {
760 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER,
761 RTL8211F_INER_PME);
762 if (ret < 0)
763 goto err;
764
765 /* Read the INSR to clear any pending interrupt */
766 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
767
768 /* Reset the WoL to ensure that an event is picked up.
769 * Unless we do this, even if we receive another packet,
770 * we may not have a PME interrupt raised.
771 */
772 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE,
773 RTL8211F_WOL_RST_RMSQ);
774 if (ret < 0)
775 goto err;
776
777 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB;
778 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
779 RTL8211F_WOL_RST_RMSQ, wol_rst);
780 if (ret < 0)
781 goto err;
782
783 wol_rst |= RTL8211F_WOL_RG_RSTB;
784 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
785 RTL8211F_WOL_RST_RMSQ, wol_rst);
786 }
787
788 err:
789 return ret;
790 }
791
rtl821x_resume(struct phy_device * phydev)792 static int rtl821x_resume(struct phy_device *phydev)
793 {
794 struct rtl821x_priv *priv = phydev->priv;
795 int ret;
796
797 if (!phydev->wol_enabled)
798 clk_prepare_enable(priv->clk);
799
800 ret = genphy_resume(phydev);
801 if (ret < 0)
802 return ret;
803
804 msleep(20);
805
806 return 0;
807 }
808
rtl8211f_resume(struct phy_device * phydev)809 static int rtl8211f_resume(struct phy_device *phydev)
810 {
811 struct rtl821x_priv *priv = phydev->priv;
812 int ret;
813
814 ret = rtl821x_resume(phydev);
815 if (ret < 0)
816 return ret;
817
818 /* If the device was programmed for a PME event, restore the interrupt
819 * enable so phylib can receive link state interrupts.
820 */
821 if (device_may_wakeup(&phydev->mdio.dev))
822 ret = phy_write_paged(phydev, 0xa42, RTL821x_INER, priv->iner);
823
824 return ret;
825 }
826
rtl8211x_led_hw_is_supported(struct phy_device * phydev,u8 index,unsigned long rules)827 static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index,
828 unsigned long rules)
829 {
830 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) |
831 BIT(TRIGGER_NETDEV_LINK_10) |
832 BIT(TRIGGER_NETDEV_LINK_100) |
833 BIT(TRIGGER_NETDEV_LINK_1000) |
834 BIT(TRIGGER_NETDEV_RX) |
835 BIT(TRIGGER_NETDEV_TX);
836
837 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
838 * - Link: Configurable subset of 10/100/1000 link rates
839 * - Active: Blink on activity, RX or TX is not differentiated
840 * The Active option has two modes, A and B:
841 * - A: Link and Active indication at configurable, but matching,
842 * subset of 10/100/1000 link rates
843 * - B: Link indication at configurable subset of 10/100/1000 link
844 * rates and Active indication always at all three 10+100+1000
845 * link rates.
846 * This code currently uses mode B only.
847 *
848 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B.
849 */
850
851 if (index >= RTL8211x_LED_COUNT)
852 return -EINVAL;
853
854 /* Filter out any other unsupported triggers. */
855 if (rules & ~mask)
856 return -EOPNOTSUPP;
857
858 /* RX and TX are not differentiated, either both are set or not set. */
859 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
860 return -EOPNOTSUPP;
861
862 return 0;
863 }
864
rtl8211f_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)865 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
866 unsigned long *rules)
867 {
868 int val;
869
870 if (index >= RTL8211x_LED_COUNT)
871 return -EINVAL;
872
873 val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
874 if (val < 0)
875 return val;
876
877 val >>= RTL8211F_LEDCR_SHIFT * index;
878 val &= RTL8211F_LEDCR_MASK;
879
880 if (val & RTL8211F_LEDCR_LINK_10)
881 __set_bit(TRIGGER_NETDEV_LINK_10, rules);
882
883 if (val & RTL8211F_LEDCR_LINK_100)
884 __set_bit(TRIGGER_NETDEV_LINK_100, rules);
885
886 if (val & RTL8211F_LEDCR_LINK_1000)
887 __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
888
889 if ((val & RTL8211F_LEDCR_LINK_10) &&
890 (val & RTL8211F_LEDCR_LINK_100) &&
891 (val & RTL8211F_LEDCR_LINK_1000)) {
892 __set_bit(TRIGGER_NETDEV_LINK, rules);
893 }
894
895 if (val & RTL8211F_LEDCR_ACT_TXRX) {
896 __set_bit(TRIGGER_NETDEV_RX, rules);
897 __set_bit(TRIGGER_NETDEV_TX, rules);
898 }
899
900 return 0;
901 }
902
rtl8211f_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)903 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
904 unsigned long rules)
905 {
906 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
907 u16 reg = 0;
908
909 if (index >= RTL8211x_LED_COUNT)
910 return -EINVAL;
911
912 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
913 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) {
914 reg |= RTL8211F_LEDCR_LINK_10;
915 }
916
917 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
918 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) {
919 reg |= RTL8211F_LEDCR_LINK_100;
920 }
921
922 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
923 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) {
924 reg |= RTL8211F_LEDCR_LINK_1000;
925 }
926
927 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
928 test_bit(TRIGGER_NETDEV_TX, &rules)) {
929 reg |= RTL8211F_LEDCR_ACT_TXRX;
930 }
931
932 reg <<= RTL8211F_LEDCR_SHIFT * index;
933 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
934
935 return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
936 }
937
rtl8211e_led_hw_control_get(struct phy_device * phydev,u8 index,unsigned long * rules)938 static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index,
939 unsigned long *rules)
940 {
941 int ret;
942 u16 cr1, cr2;
943
944 if (index >= RTL8211x_LED_COUNT)
945 return -EINVAL;
946
947 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
948 RTL8211E_LEDCR1);
949 if (ret < 0)
950 return ret;
951
952 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index;
953 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) {
954 __set_bit(TRIGGER_NETDEV_RX, rules);
955 __set_bit(TRIGGER_NETDEV_TX, rules);
956 }
957
958 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
959 RTL8211E_LEDCR2);
960 if (ret < 0)
961 return ret;
962
963 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index;
964 if (cr2 & RTL8211E_LEDCR2_LINK_10)
965 __set_bit(TRIGGER_NETDEV_LINK_10, rules);
966
967 if (cr2 & RTL8211E_LEDCR2_LINK_100)
968 __set_bit(TRIGGER_NETDEV_LINK_100, rules);
969
970 if (cr2 & RTL8211E_LEDCR2_LINK_1000)
971 __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
972
973 if ((cr2 & RTL8211E_LEDCR2_LINK_10) &&
974 (cr2 & RTL8211E_LEDCR2_LINK_100) &&
975 (cr2 & RTL8211E_LEDCR2_LINK_1000)) {
976 __set_bit(TRIGGER_NETDEV_LINK, rules);
977 }
978
979 return ret;
980 }
981
rtl8211e_led_hw_control_set(struct phy_device * phydev,u8 index,unsigned long rules)982 static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index,
983 unsigned long rules)
984 {
985 const u16 cr1mask =
986 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index);
987 const u16 cr2mask =
988 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index);
989 u16 cr1 = 0, cr2 = 0;
990 int ret;
991
992 if (index >= RTL8211x_LED_COUNT)
993 return -EINVAL;
994
995 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
996 test_bit(TRIGGER_NETDEV_TX, &rules)) {
997 cr1 |= RTL8211E_LEDCR1_ACT_TXRX;
998 }
999
1000 cr1 <<= RTL8211E_LEDCR1_SHIFT * index;
1001 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
1002 RTL8211E_LEDCR1, cr1mask, cr1);
1003 if (ret < 0)
1004 return ret;
1005
1006 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1007 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) {
1008 cr2 |= RTL8211E_LEDCR2_LINK_10;
1009 }
1010
1011 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1012 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) {
1013 cr2 |= RTL8211E_LEDCR2_LINK_100;
1014 }
1015
1016 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1017 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) {
1018 cr2 |= RTL8211E_LEDCR2_LINK_1000;
1019 }
1020
1021 cr2 <<= RTL8211E_LEDCR2_SHIFT * index;
1022 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
1023 RTL8211E_LEDCR2, cr2mask, cr2);
1024
1025 return ret;
1026 }
1027
rtl8211e_config_init(struct phy_device * phydev)1028 static int rtl8211e_config_init(struct phy_device *phydev)
1029 {
1030 u16 val;
1031
1032 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
1033 switch (phydev->interface) {
1034 case PHY_INTERFACE_MODE_RGMII:
1035 val = RTL8211E_CTRL_DELAY | 0;
1036 break;
1037 case PHY_INTERFACE_MODE_RGMII_ID:
1038 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
1039 break;
1040 case PHY_INTERFACE_MODE_RGMII_RXID:
1041 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
1042 break;
1043 case PHY_INTERFACE_MODE_RGMII_TXID:
1044 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
1045 break;
1046 default: /* the rest of the modes imply leaving delays as is. */
1047 return 0;
1048 }
1049
1050 /* According to a sample driver there is a 0x1c config register on the
1051 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
1052 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
1053 * The configuration register definition:
1054 * 14 = reserved
1055 * 13 = Force Tx RX Delay controlled by bit12 bit11,
1056 * 12 = RX Delay, 11 = TX Delay
1057 * 10:0 = Test && debug settings reserved by realtek
1058 */
1059 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE,
1060 RTL8211E_RGMII_DELAY,
1061 RTL8211E_DELAY_MASK, val);
1062 }
1063
rtl8211b_suspend(struct phy_device * phydev)1064 static int rtl8211b_suspend(struct phy_device *phydev)
1065 {
1066 phy_write(phydev, MII_MMD_DATA, BIT(9));
1067
1068 return genphy_suspend(phydev);
1069 }
1070
rtl8211b_resume(struct phy_device * phydev)1071 static int rtl8211b_resume(struct phy_device *phydev)
1072 {
1073 phy_write(phydev, MII_MMD_DATA, 0);
1074
1075 return genphy_resume(phydev);
1076 }
1077
rtl8366rb_config_init(struct phy_device * phydev)1078 static int rtl8366rb_config_init(struct phy_device *phydev)
1079 {
1080 int ret;
1081
1082 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
1083 RTL8366RB_POWER_SAVE_ON);
1084 if (ret) {
1085 dev_err(&phydev->mdio.dev,
1086 "error enabling power management\n");
1087 }
1088
1089 return ret;
1090 }
1091
1092 /* get actual speed to cover the downshift case */
rtlgen_decode_physr(struct phy_device * phydev,int val)1093 static void rtlgen_decode_physr(struct phy_device *phydev, int val)
1094 {
1095 /* bit 3
1096 * 0: Half Duplex
1097 * 1: Full Duplex
1098 */
1099 if (val & RTL_VND2_PHYSR_DUPLEX)
1100 phydev->duplex = DUPLEX_FULL;
1101 else
1102 phydev->duplex = DUPLEX_HALF;
1103
1104 switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
1105 case 0x0000:
1106 phydev->speed = SPEED_10;
1107 break;
1108 case 0x0010:
1109 phydev->speed = SPEED_100;
1110 break;
1111 case 0x0020:
1112 phydev->speed = SPEED_1000;
1113 break;
1114 case 0x0200:
1115 phydev->speed = SPEED_10000;
1116 break;
1117 case 0x0210:
1118 phydev->speed = SPEED_2500;
1119 break;
1120 case 0x0220:
1121 phydev->speed = SPEED_5000;
1122 break;
1123 default:
1124 break;
1125 }
1126
1127 /* bit 11
1128 * 0: Slave Mode
1129 * 1: Master Mode
1130 */
1131 if (phydev->speed >= 1000) {
1132 if (val & RTL_VND2_PHYSR_MASTER)
1133 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1134 else
1135 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1136 } else {
1137 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
1138 }
1139 }
1140
rtlgen_read_status(struct phy_device * phydev)1141 static int rtlgen_read_status(struct phy_device *phydev)
1142 {
1143 int ret, val;
1144
1145 ret = genphy_read_status(phydev);
1146 if (ret < 0)
1147 return ret;
1148
1149 if (!phydev->link)
1150 return 0;
1151
1152 val = phy_read_paged(phydev, 0xa43, 0x12);
1153 if (val < 0)
1154 return val;
1155
1156 rtlgen_decode_physr(phydev, val);
1157
1158 return 0;
1159 }
1160
rtlgen_read_vend2(struct phy_device * phydev,int regnum)1161 static int rtlgen_read_vend2(struct phy_device *phydev, int regnum)
1162 {
1163 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum);
1164 }
1165
rtlgen_write_vend2(struct phy_device * phydev,int regnum,u16 val)1166 static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val)
1167 {
1168 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum,
1169 val);
1170 }
1171
rtlgen_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)1172 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
1173 {
1174 int ret;
1175
1176 if (devnum == MDIO_MMD_VEND2)
1177 ret = rtlgen_read_vend2(phydev, regnum);
1178 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
1179 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE);
1180 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
1181 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV);
1182 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
1183 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE);
1184 else
1185 ret = -EOPNOTSUPP;
1186
1187 return ret;
1188 }
1189
rtlgen_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)1190 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
1191 u16 val)
1192 {
1193 int ret;
1194
1195 if (devnum == MDIO_MMD_VEND2)
1196 ret = rtlgen_write_vend2(phydev, regnum, val);
1197 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
1198 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV);
1199 else
1200 ret = -EOPNOTSUPP;
1201
1202 return ret;
1203 }
1204
rtl822x_read_mmd(struct phy_device * phydev,int devnum,u16 regnum)1205 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
1206 {
1207 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
1208
1209 if (ret != -EOPNOTSUPP)
1210 return ret;
1211
1212 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
1213 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2);
1214 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
1215 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2);
1216 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
1217 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2);
1218
1219 return ret;
1220 }
1221
rtl822x_write_mmd(struct phy_device * phydev,int devnum,u16 regnum,u16 val)1222 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
1223 u16 val)
1224 {
1225 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
1226
1227 if (ret != -EOPNOTSUPP)
1228 return ret;
1229
1230 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
1231 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val);
1232
1233 return ret;
1234 }
1235
rtl822x_probe(struct phy_device * phydev)1236 static int rtl822x_probe(struct phy_device *phydev)
1237 {
1238 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) &&
1239 phydev->phy_id != RTL_GENERIC_PHYID)
1240 return rtl822x_hwmon_init(phydev);
1241
1242 return 0;
1243 }
1244
rtl822x_set_serdes_option_mode(struct phy_device * phydev,bool gen1)1245 static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1)
1246 {
1247 bool has_2500, has_sgmii;
1248 u16 mode;
1249 int ret;
1250
1251 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
1252 phydev->host_interfaces) ||
1253 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
1254
1255 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
1256 phydev->host_interfaces) ||
1257 phydev->interface == PHY_INTERFACE_MODE_SGMII;
1258
1259 /* fill in possible interfaces */
1260 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
1261 has_2500);
1262 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
1263 has_sgmii);
1264
1265 if (!has_2500 && !has_sgmii)
1266 return 0;
1267
1268 /* determine SerDes option mode */
1269 if (has_2500 && !has_sgmii) {
1270 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
1271 phydev->rate_matching = RATE_MATCH_PAUSE;
1272 } else {
1273 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
1274 phydev->rate_matching = RATE_MATCH_NONE;
1275 }
1276
1277 /* the following sequence with magic numbers sets up the SerDes
1278 * option mode
1279 */
1280
1281 if (!gen1) {
1282 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
1283 if (ret < 0)
1284 return ret;
1285 }
1286
1287 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
1288 RTL822X_VND1_SERDES_OPTION,
1289 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
1290 mode);
1291 if (gen1 || ret < 0)
1292 return ret;
1293
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
1295 if (ret < 0)
1296 return ret;
1297
1298 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
1299 if (ret < 0)
1300 return ret;
1301
1302 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
1303 }
1304
rtl822x_config_init(struct phy_device * phydev)1305 static int rtl822x_config_init(struct phy_device *phydev)
1306 {
1307 return rtl822x_set_serdes_option_mode(phydev, true);
1308 }
1309
rtl822xb_config_init(struct phy_device * phydev)1310 static int rtl822xb_config_init(struct phy_device *phydev)
1311 {
1312 return rtl822x_set_serdes_option_mode(phydev, false);
1313 }
1314
rtl822xb_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)1315 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
1316 phy_interface_t iface)
1317 {
1318 int val;
1319
1320 /* Only rate matching at 2500base-x */
1321 if (iface != PHY_INTERFACE_MODE_2500BASEX)
1322 return RATE_MATCH_NONE;
1323
1324 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
1325 if (val < 0)
1326 return val;
1327
1328 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
1329 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
1330 return RATE_MATCH_PAUSE;
1331
1332 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
1333 return RATE_MATCH_NONE;
1334 }
1335
rtl822x_get_features(struct phy_device * phydev)1336 static int rtl822x_get_features(struct phy_device *phydev)
1337 {
1338 int val;
1339
1340 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED);
1341 if (val < 0)
1342 return val;
1343
1344 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1345 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
1346 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1347 phydev->supported, val & MDIO_PMA_SPEED_5G);
1348 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1349 phydev->supported, val & MDIO_SPEED_10G);
1350
1351 return genphy_read_abilities(phydev);
1352 }
1353
rtl822x_config_aneg(struct phy_device * phydev)1354 static int rtl822x_config_aneg(struct phy_device *phydev)
1355 {
1356 int ret = 0;
1357
1358 if (phydev->autoneg == AUTONEG_ENABLE) {
1359 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
1360
1361 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
1362 RTL_MDIO_AN_10GBT_CTRL,
1363 MDIO_AN_10GBT_CTRL_ADV2_5G |
1364 MDIO_AN_10GBT_CTRL_ADV5G, adv);
1365 if (ret < 0)
1366 return ret;
1367 }
1368
1369 return __genphy_config_aneg(phydev, ret);
1370 }
1371
rtl822xb_update_interface(struct phy_device * phydev)1372 static void rtl822xb_update_interface(struct phy_device *phydev)
1373 {
1374 int val;
1375
1376 if (!phydev->link)
1377 return;
1378
1379 /* Change interface according to serdes mode */
1380 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
1381 if (val < 0)
1382 return;
1383
1384 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
1385 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
1386 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1387 break;
1388 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
1389 phydev->interface = PHY_INTERFACE_MODE_SGMII;
1390 break;
1391 }
1392 }
1393
rtl822x_read_status(struct phy_device * phydev)1394 static int rtl822x_read_status(struct phy_device *phydev)
1395 {
1396 int lpadv, ret;
1397
1398 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1399
1400 ret = rtlgen_read_status(phydev);
1401 if (ret < 0)
1402 return ret;
1403
1404 if (phydev->autoneg == AUTONEG_DISABLE ||
1405 !phydev->autoneg_complete)
1406 return 0;
1407
1408 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT);
1409 if (lpadv < 0)
1410 return lpadv;
1411
1412 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
1413
1414 return 0;
1415 }
1416
rtl822xb_read_status(struct phy_device * phydev)1417 static int rtl822xb_read_status(struct phy_device *phydev)
1418 {
1419 int ret;
1420
1421 ret = rtl822x_read_status(phydev);
1422 if (ret < 0)
1423 return ret;
1424
1425 rtl822xb_update_interface(phydev);
1426
1427 return 0;
1428 }
1429
rtl822x_c45_get_features(struct phy_device * phydev)1430 static int rtl822x_c45_get_features(struct phy_device *phydev)
1431 {
1432 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1433 phydev->supported);
1434
1435 return genphy_c45_pma_read_abilities(phydev);
1436 }
1437
rtl822x_c45_config_aneg(struct phy_device * phydev)1438 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1439 {
1440 bool changed = false;
1441 int ret, val;
1442
1443 if (phydev->autoneg == AUTONEG_DISABLE)
1444 return genphy_c45_pma_setup_forced(phydev);
1445
1446 ret = genphy_c45_an_config_aneg(phydev);
1447 if (ret < 0)
1448 return ret;
1449 if (ret > 0)
1450 changed = true;
1451
1452 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1453
1454 /* Vendor register as C45 has no standardized support for 1000BaseT */
1455 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
1456 RTL822X_VND2_C22_REG(MII_CTRL1000),
1457 ADVERTISE_1000FULL, val);
1458 if (ret < 0)
1459 return ret;
1460 if (ret > 0)
1461 changed = true;
1462
1463 return genphy_c45_check_and_restart_aneg(phydev, changed);
1464 }
1465
rtl822x_c45_read_status(struct phy_device * phydev)1466 static int rtl822x_c45_read_status(struct phy_device *phydev)
1467 {
1468 int ret, val;
1469
1470 /* Vendor register as C45 has no standardized support for 1000BaseT */
1471 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1472 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1473 RTL822X_VND2_C22_REG(MII_STAT1000));
1474 if (val < 0)
1475 return val;
1476 } else {
1477 val = 0;
1478 }
1479 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1480
1481 ret = genphy_c45_read_status(phydev);
1482 if (ret < 0)
1483 return ret;
1484
1485 if (!phydev->link) {
1486 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1487 return 0;
1488 }
1489
1490 /* Read actual speed from vendor register. */
1491 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1492 if (val < 0)
1493 return val;
1494
1495 rtlgen_decode_physr(phydev, val);
1496
1497 return 0;
1498 }
1499
rtl822x_c45_soft_reset(struct phy_device * phydev)1500 static int rtl822x_c45_soft_reset(struct phy_device *phydev)
1501 {
1502 int ret, val;
1503
1504 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
1505 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
1506 if (ret < 0)
1507 return ret;
1508
1509 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
1510 MDIO_CTRL1, val,
1511 !(val & MDIO_CTRL1_RESET),
1512 5000, 100000, true);
1513 }
1514
rtl822xb_c45_read_status(struct phy_device * phydev)1515 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1516 {
1517 int ret;
1518
1519 ret = rtl822x_c45_read_status(phydev);
1520 if (ret < 0)
1521 return ret;
1522
1523 rtl822xb_update_interface(phydev);
1524
1525 return 0;
1526 }
1527
rtl8224_cable_test_start(struct phy_device * phydev)1528 static int rtl8224_cable_test_start(struct phy_device *phydev)
1529 {
1530 u32 val;
1531 int ret;
1532
1533 /* disable auto-negotiation and force 1000/Full */
1534 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1535 RTL822X_VND2_C22_REG(MII_BMCR),
1536 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10,
1537 BMCR_SPEED1000 | BMCR_FULLDPLX);
1538 if (ret)
1539 return ret;
1540
1541 mdelay(500);
1542
1543 /* trigger cable test */
1544 val = RTL8224_MII_RTCT_ENABLE;
1545 val |= RTL8224_MII_RTCT_PAIR_A;
1546 val |= RTL8224_MII_RTCT_PAIR_B;
1547 val |= RTL8224_MII_RTCT_PAIR_C;
1548 val |= RTL8224_MII_RTCT_PAIR_D;
1549
1550 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1551 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT),
1552 RTL8224_MII_RTCT_DONE, val);
1553 }
1554
rtl8224_sram_read(struct phy_device * phydev,u32 reg)1555 static int rtl8224_sram_read(struct phy_device *phydev, u32 reg)
1556 {
1557 int ret;
1558
1559 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1560 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR),
1561 reg);
1562 if (ret)
1563 return ret;
1564
1565 return phy_read_mmd(phydev, MDIO_MMD_VEND2,
1566 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA));
1567 }
1568
rtl8224_pair_len_get(struct phy_device * phydev,u32 pair)1569 static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair)
1570 {
1571 int cable_len;
1572 u32 reg_len;
1573 int ret;
1574 u32 cm;
1575
1576 reg_len = RTL8224_SRAM_RTCT_LEN(pair);
1577
1578 ret = rtl8224_sram_read(phydev, reg_len);
1579 if (ret < 0)
1580 return ret;
1581
1582 cable_len = ret & 0xff00;
1583
1584 ret = rtl8224_sram_read(phydev, reg_len + 1);
1585 if (ret < 0)
1586 return ret;
1587
1588 cable_len |= (ret & 0xff00) >> 8;
1589
1590 cable_len -= 620;
1591 cable_len = max(cable_len, 0);
1592
1593 cm = cable_len * 100 / 78;
1594
1595 return cm;
1596 }
1597
rtl8224_cable_test_result_trans(u32 result)1598 static int rtl8224_cable_test_result_trans(u32 result)
1599 {
1600 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE))
1601 return -EBUSY;
1602
1603 if (result & RTL8224_SRAM_RTCT_FAULT_OK)
1604 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1605
1606 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN)
1607 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1608
1609 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT)
1610 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1611
1612 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY)
1613 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1614
1615 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT)
1616 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
1617
1618 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1619 }
1620
rtl8224_cable_test_report_pair(struct phy_device * phydev,unsigned int pair)1621 static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair)
1622 {
1623 int fault_rslt;
1624 int ret;
1625
1626 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair));
1627 if (ret < 0)
1628 return ret;
1629
1630 fault_rslt = rtl8224_cable_test_result_trans(ret);
1631 if (fault_rslt < 0)
1632 return 0;
1633
1634 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
1635 if (ret < 0)
1636 return ret;
1637
1638 switch (fault_rslt) {
1639 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
1640 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
1641 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
1642 ret = rtl8224_pair_len_get(phydev, pair);
1643 if (ret < 0)
1644 return ret;
1645
1646 return ethnl_cable_test_fault_length(phydev, pair, ret);
1647 default:
1648 return 0;
1649 }
1650 }
1651
rtl8224_cable_test_report(struct phy_device * phydev,bool * finished)1652 static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished)
1653 {
1654 unsigned int pair;
1655 int ret;
1656
1657 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
1658 ret = rtl8224_cable_test_report_pair(phydev, pair);
1659 if (ret == -EBUSY) {
1660 *finished = false;
1661 return 0;
1662 }
1663
1664 if (ret < 0)
1665 return ret;
1666 }
1667
1668 return 0;
1669 }
1670
rtl8224_cable_test_get_status(struct phy_device * phydev,bool * finished)1671 static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished)
1672 {
1673 int ret;
1674
1675 *finished = false;
1676
1677 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1678 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT));
1679 if (ret < 0)
1680 return ret;
1681
1682 if (!(ret & RTL8224_MII_RTCT_DONE))
1683 return 0;
1684
1685 *finished = true;
1686
1687 return rtl8224_cable_test_report(phydev, finished);
1688 }
1689
rtlgen_supports_2_5gbps(struct phy_device * phydev)1690 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1691 {
1692 int val;
1693
1694 phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1695 val = phy_read(phydev, 0x13);
1696 phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1697
1698 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1699 }
1700
1701 /* On internal PHY's MMD reads over C22 always return 0.
1702 * Check a MMD register which is known to be non-zero.
1703 */
rtlgen_supports_mmd(struct phy_device * phydev)1704 static bool rtlgen_supports_mmd(struct phy_device *phydev)
1705 {
1706 int val;
1707
1708 phy_lock_mdio_bus(phydev);
1709 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1710 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1711 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1712 val = __phy_read(phydev, MII_MMD_DATA);
1713 phy_unlock_mdio_bus(phydev);
1714
1715 return val > 0;
1716 }
1717
rtlgen_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1718 static int rtlgen_match_phy_device(struct phy_device *phydev,
1719 const struct phy_driver *phydrv)
1720 {
1721 return phydev->phy_id == RTL_GENERIC_PHYID &&
1722 !rtlgen_supports_2_5gbps(phydev);
1723 }
1724
rtl8226_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1725 static int rtl8226_match_phy_device(struct phy_device *phydev,
1726 const struct phy_driver *phydrv)
1727 {
1728 return phydev->phy_id == RTL_GENERIC_PHYID &&
1729 rtlgen_supports_2_5gbps(phydev) &&
1730 rtlgen_supports_mmd(phydev);
1731 }
1732
rtlgen_is_c45_match(struct phy_device * phydev,unsigned int id,bool is_c45)1733 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1734 bool is_c45)
1735 {
1736 if (phydev->is_c45)
1737 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1738 else
1739 return !is_c45 && (id == phydev->phy_id);
1740 }
1741
rtl8221b_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1742 static int rtl8221b_match_phy_device(struct phy_device *phydev,
1743 const struct phy_driver *phydrv)
1744 {
1745 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1746 }
1747
rtl8221b_vb_cg_c22_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1748 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev,
1749 const struct phy_driver *phydrv)
1750 {
1751 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1752 }
1753
rtl8221b_vb_cg_c45_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1754 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev,
1755 const struct phy_driver *phydrv)
1756 {
1757 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1758 }
1759
rtl8221b_vm_cg_c22_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1760 static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev,
1761 const struct phy_driver *phydrv)
1762 {
1763 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, false);
1764 }
1765
rtl8221b_vm_cg_c45_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1766 static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev,
1767 const struct phy_driver *phydrv)
1768 {
1769 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, true);
1770 }
1771
rtl_internal_nbaset_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1772 static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev,
1773 const struct phy_driver *phydrv)
1774 {
1775 if (phydev->is_c45)
1776 return false;
1777
1778 switch (phydev->phy_id) {
1779 case RTL_GENERIC_PHYID:
1780 case RTL_8221B:
1781 case RTL_8251B:
1782 case RTL_8261C:
1783 case 0x001cc841:
1784 break;
1785 default:
1786 return false;
1787 }
1788
1789 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1790 }
1791
rtl8251b_c45_match_phy_device(struct phy_device * phydev,const struct phy_driver * phydrv)1792 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev,
1793 const struct phy_driver *phydrv)
1794 {
1795 return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1796 }
1797
rtlgen_resume(struct phy_device * phydev)1798 static int rtlgen_resume(struct phy_device *phydev)
1799 {
1800 int ret = genphy_resume(phydev);
1801
1802 /* Internal PHY's from RTL8168h up may not be instantly ready */
1803 msleep(20);
1804
1805 return ret;
1806 }
1807
rtlgen_c45_resume(struct phy_device * phydev)1808 static int rtlgen_c45_resume(struct phy_device *phydev)
1809 {
1810 int ret = genphy_c45_pma_resume(phydev);
1811
1812 msleep(20);
1813
1814 return ret;
1815 }
1816
rtl9000a_config_init(struct phy_device * phydev)1817 static int rtl9000a_config_init(struct phy_device *phydev)
1818 {
1819 phydev->autoneg = AUTONEG_DISABLE;
1820 phydev->speed = SPEED_100;
1821 phydev->duplex = DUPLEX_FULL;
1822
1823 return 0;
1824 }
1825
rtl9000a_config_aneg(struct phy_device * phydev)1826 static int rtl9000a_config_aneg(struct phy_device *phydev)
1827 {
1828 int ret;
1829 u16 ctl = 0;
1830
1831 switch (phydev->master_slave_set) {
1832 case MASTER_SLAVE_CFG_MASTER_FORCE:
1833 ctl |= CTL1000_AS_MASTER;
1834 break;
1835 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1836 break;
1837 case MASTER_SLAVE_CFG_UNKNOWN:
1838 case MASTER_SLAVE_CFG_UNSUPPORTED:
1839 return 0;
1840 default:
1841 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1842 return -EOPNOTSUPP;
1843 }
1844
1845 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1846 if (ret == 1)
1847 ret = genphy_soft_reset(phydev);
1848
1849 return ret;
1850 }
1851
rtl9000a_read_status(struct phy_device * phydev)1852 static int rtl9000a_read_status(struct phy_device *phydev)
1853 {
1854 int ret;
1855
1856 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1857 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1858
1859 ret = genphy_update_link(phydev);
1860 if (ret)
1861 return ret;
1862
1863 ret = phy_read(phydev, MII_CTRL1000);
1864 if (ret < 0)
1865 return ret;
1866 if (ret & CTL1000_AS_MASTER)
1867 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1868 else
1869 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1870
1871 ret = phy_read(phydev, MII_STAT1000);
1872 if (ret < 0)
1873 return ret;
1874 if (ret & LPA_1000MSRES)
1875 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1876 else
1877 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1878
1879 return 0;
1880 }
1881
rtl9000a_ack_interrupt(struct phy_device * phydev)1882 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1883 {
1884 int err;
1885
1886 err = phy_read(phydev, RTL8211F_INSR);
1887
1888 return (err < 0) ? err : 0;
1889 }
1890
rtl9000a_config_intr(struct phy_device * phydev)1891 static int rtl9000a_config_intr(struct phy_device *phydev)
1892 {
1893 u16 val;
1894 int err;
1895
1896 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1897 err = rtl9000a_ack_interrupt(phydev);
1898 if (err)
1899 return err;
1900
1901 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1902 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1903 } else {
1904 val = ~0;
1905 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1906 if (err)
1907 return err;
1908
1909 err = rtl9000a_ack_interrupt(phydev);
1910 }
1911
1912 return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1913 }
1914
rtl9000a_handle_interrupt(struct phy_device * phydev)1915 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1916 {
1917 int irq_status;
1918
1919 irq_status = phy_read(phydev, RTL8211F_INSR);
1920 if (irq_status < 0) {
1921 phy_error(phydev);
1922 return IRQ_NONE;
1923 }
1924
1925 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1926 return IRQ_NONE;
1927
1928 phy_trigger_machine(phydev);
1929
1930 return IRQ_HANDLED;
1931 }
1932
rtl8221b_ack_interrupt(struct phy_device * phydev)1933 static int rtl8221b_ack_interrupt(struct phy_device *phydev)
1934 {
1935 int err;
1936
1937 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR);
1938
1939 return (err < 0) ? err : 0;
1940 }
1941
rtl8221b_config_intr(struct phy_device * phydev)1942 static int rtl8221b_config_intr(struct phy_device *phydev)
1943 {
1944 int err;
1945
1946 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1947 err = rtl8221b_ack_interrupt(phydev);
1948 if (err)
1949 return err;
1950
1951 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER,
1952 RTL8221B_VND2_INER_LINK_STATUS);
1953 } else {
1954 err = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1955 RTL8221B_VND2_INER, 0);
1956 if (err)
1957 return err;
1958
1959 err = rtl8221b_ack_interrupt(phydev);
1960 }
1961
1962 return err;
1963 }
1964
rtl8221b_handle_interrupt(struct phy_device * phydev)1965 static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev)
1966 {
1967 int err;
1968
1969 err = rtl8221b_ack_interrupt(phydev);
1970 if (err) {
1971 phy_error(phydev);
1972 return IRQ_NONE;
1973 }
1974
1975 phy_trigger_machine(phydev);
1976
1977 return IRQ_HANDLED;
1978 }
1979
1980 static struct phy_driver realtek_drvs[] = {
1981 {
1982 PHY_ID_MATCH_EXACT(0x00008201),
1983 .name = "RTL8201CP Ethernet",
1984 .read_page = rtl821x_read_page,
1985 .write_page = rtl821x_write_page,
1986 }, {
1987 PHY_ID_MATCH_EXACT(0x001cc816),
1988 .name = "RTL8201F Fast Ethernet",
1989 .config_intr = &rtl8201_config_intr,
1990 .handle_interrupt = rtl8201_handle_interrupt,
1991 .suspend = genphy_suspend,
1992 .resume = genphy_resume,
1993 .read_page = rtl821x_read_page,
1994 .write_page = rtl821x_write_page,
1995 }, {
1996 PHY_ID_MATCH_MODEL(0x001cc880),
1997 .name = "RTL8208 Fast Ethernet",
1998 .read_mmd = genphy_read_mmd_unsupported,
1999 .write_mmd = genphy_write_mmd_unsupported,
2000 .suspend = genphy_suspend,
2001 .resume = genphy_resume,
2002 .read_page = rtl821x_read_page,
2003 .write_page = rtl821x_write_page,
2004 }, {
2005 PHY_ID_MATCH_EXACT(0x001cc910),
2006 .name = "RTL8211 Gigabit Ethernet",
2007 .config_aneg = rtl8211_config_aneg,
2008 .read_mmd = &genphy_read_mmd_unsupported,
2009 .write_mmd = &genphy_write_mmd_unsupported,
2010 .read_page = rtl821x_read_page,
2011 .write_page = rtl821x_write_page,
2012 }, {
2013 PHY_ID_MATCH_EXACT(0x001cc912),
2014 .name = "RTL8211B Gigabit Ethernet",
2015 .config_intr = &rtl8211b_config_intr,
2016 .handle_interrupt = rtl821x_handle_interrupt,
2017 .read_mmd = &genphy_read_mmd_unsupported,
2018 .write_mmd = &genphy_write_mmd_unsupported,
2019 .suspend = rtl8211b_suspend,
2020 .resume = rtl8211b_resume,
2021 .read_page = rtl821x_read_page,
2022 .write_page = rtl821x_write_page,
2023 }, {
2024 PHY_ID_MATCH_EXACT(0x001cc913),
2025 .name = "RTL8211C Gigabit Ethernet",
2026 .config_init = rtl8211c_config_init,
2027 .read_mmd = &genphy_read_mmd_unsupported,
2028 .write_mmd = &genphy_write_mmd_unsupported,
2029 .read_page = rtl821x_read_page,
2030 .write_page = rtl821x_write_page,
2031 }, {
2032 PHY_ID_MATCH_EXACT(0x001cc914),
2033 .name = "RTL8211DN Gigabit Ethernet",
2034 .config_intr = rtl8211e_config_intr,
2035 .handle_interrupt = rtl821x_handle_interrupt,
2036 .suspend = genphy_suspend,
2037 .resume = genphy_resume,
2038 .read_page = rtl821x_read_page,
2039 .write_page = rtl821x_write_page,
2040 }, {
2041 PHY_ID_MATCH_EXACT(0x001cc915),
2042 .name = "RTL8211E Gigabit Ethernet",
2043 .config_init = &rtl8211e_config_init,
2044 .config_intr = &rtl8211e_config_intr,
2045 .handle_interrupt = rtl821x_handle_interrupt,
2046 .suspend = genphy_suspend,
2047 .resume = genphy_resume,
2048 .read_page = rtl821x_read_page,
2049 .write_page = rtl821x_write_page,
2050 .led_hw_is_supported = rtl8211x_led_hw_is_supported,
2051 .led_hw_control_get = rtl8211e_led_hw_control_get,
2052 .led_hw_control_set = rtl8211e_led_hw_control_set,
2053 }, {
2054 PHY_ID_MATCH_EXACT(0x001cc916),
2055 .name = "RTL8211F Gigabit Ethernet",
2056 .probe = rtl8211f_probe,
2057 .config_init = &rtl8211f_config_init,
2058 .read_status = rtlgen_read_status,
2059 .config_intr = &rtl8211f_config_intr,
2060 .handle_interrupt = rtl8211f_handle_interrupt,
2061 .set_wol = rtl8211f_set_wol,
2062 .get_wol = rtl8211f_get_wol,
2063 .suspend = rtl8211f_suspend,
2064 .resume = rtl8211f_resume,
2065 .read_page = rtl821x_read_page,
2066 .write_page = rtl821x_write_page,
2067 .flags = PHY_ALWAYS_CALL_SUSPEND,
2068 .led_hw_is_supported = rtl8211x_led_hw_is_supported,
2069 .led_hw_control_get = rtl8211f_led_hw_control_get,
2070 .led_hw_control_set = rtl8211f_led_hw_control_set,
2071 }, {
2072 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
2073 .name = "RTL8211F-VD Gigabit Ethernet",
2074 .probe = rtl821x_probe,
2075 .config_init = &rtl8211f_config_init,
2076 .read_status = rtlgen_read_status,
2077 .config_intr = &rtl8211f_config_intr,
2078 .handle_interrupt = rtl8211f_handle_interrupt,
2079 .suspend = rtl821x_suspend,
2080 .resume = rtl821x_resume,
2081 .read_page = rtl821x_read_page,
2082 .write_page = rtl821x_write_page,
2083 .flags = PHY_ALWAYS_CALL_SUSPEND,
2084 }, {
2085 .name = "Generic FE-GE Realtek PHY",
2086 .match_phy_device = rtlgen_match_phy_device,
2087 .read_status = rtlgen_read_status,
2088 .suspend = genphy_suspend,
2089 .resume = rtlgen_resume,
2090 .read_page = rtl821x_read_page,
2091 .write_page = rtl821x_write_page,
2092 .read_mmd = rtlgen_read_mmd,
2093 .write_mmd = rtlgen_write_mmd,
2094 }, {
2095 .name = "RTL8226 2.5Gbps PHY",
2096 .match_phy_device = rtl8226_match_phy_device,
2097 .get_features = rtl822x_get_features,
2098 .config_aneg = rtl822x_config_aneg,
2099 .read_status = rtl822x_read_status,
2100 .suspend = genphy_suspend,
2101 .resume = rtlgen_resume,
2102 .read_page = rtl821x_read_page,
2103 .write_page = rtl821x_write_page,
2104 }, {
2105 .match_phy_device = rtl8221b_match_phy_device,
2106 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
2107 .get_features = rtl822x_get_features,
2108 .config_aneg = rtl822x_config_aneg,
2109 .config_init = rtl822xb_config_init,
2110 .get_rate_matching = rtl822xb_get_rate_matching,
2111 .read_status = rtl822xb_read_status,
2112 .suspend = genphy_suspend,
2113 .resume = rtlgen_resume,
2114 .read_page = rtl821x_read_page,
2115 .write_page = rtl821x_write_page,
2116 }, {
2117 PHY_ID_MATCH_EXACT(0x001cc838),
2118 .name = "RTL8226-CG 2.5Gbps PHY",
2119 .soft_reset = rtl822x_c45_soft_reset,
2120 .get_features = rtl822x_c45_get_features,
2121 .config_aneg = rtl822x_c45_config_aneg,
2122 .config_init = rtl822x_config_init,
2123 .read_status = rtl822xb_c45_read_status,
2124 .suspend = genphy_c45_pma_suspend,
2125 .resume = rtlgen_c45_resume,
2126 }, {
2127 PHY_ID_MATCH_EXACT(0x001cc848),
2128 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
2129 .get_features = rtl822x_get_features,
2130 .config_aneg = rtl822x_config_aneg,
2131 .config_init = rtl822xb_config_init,
2132 .get_rate_matching = rtl822xb_get_rate_matching,
2133 .read_status = rtl822xb_read_status,
2134 .suspend = genphy_suspend,
2135 .resume = rtlgen_resume,
2136 .read_page = rtl821x_read_page,
2137 .write_page = rtl821x_write_page,
2138 }, {
2139 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
2140 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
2141 .probe = rtl822x_probe,
2142 .get_features = rtl822x_get_features,
2143 .config_aneg = rtl822x_config_aneg,
2144 .config_init = rtl822xb_config_init,
2145 .get_rate_matching = rtl822xb_get_rate_matching,
2146 .read_status = rtl822xb_read_status,
2147 .suspend = genphy_suspend,
2148 .resume = rtlgen_resume,
2149 .read_page = rtl821x_read_page,
2150 .write_page = rtl821x_write_page,
2151 }, {
2152 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
2153 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
2154 .config_intr = rtl8221b_config_intr,
2155 .handle_interrupt = rtl8221b_handle_interrupt,
2156 .probe = rtl822x_probe,
2157 .config_init = rtl822xb_config_init,
2158 .get_rate_matching = rtl822xb_get_rate_matching,
2159 .get_features = rtl822x_c45_get_features,
2160 .config_aneg = rtl822x_c45_config_aneg,
2161 .read_status = rtl822xb_c45_read_status,
2162 .suspend = genphy_c45_pma_suspend,
2163 .resume = rtlgen_c45_resume,
2164 }, {
2165 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device,
2166 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
2167 .probe = rtl822x_probe,
2168 .get_features = rtl822x_get_features,
2169 .config_aneg = rtl822x_config_aneg,
2170 .config_init = rtl822xb_config_init,
2171 .get_rate_matching = rtl822xb_get_rate_matching,
2172 .read_status = rtl822xb_read_status,
2173 .suspend = genphy_suspend,
2174 .resume = rtlgen_resume,
2175 .read_page = rtl821x_read_page,
2176 .write_page = rtl821x_write_page,
2177 }, {
2178 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device,
2179 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)",
2180 .config_intr = rtl8221b_config_intr,
2181 .handle_interrupt = rtl8221b_handle_interrupt,
2182 .probe = rtl822x_probe,
2183 .config_init = rtl822xb_config_init,
2184 .get_rate_matching = rtl822xb_get_rate_matching,
2185 .get_features = rtl822x_c45_get_features,
2186 .config_aneg = rtl822x_c45_config_aneg,
2187 .read_status = rtl822xb_c45_read_status,
2188 .suspend = genphy_c45_pma_suspend,
2189 .resume = rtlgen_c45_resume,
2190 }, {
2191 .match_phy_device = rtl8251b_c45_match_phy_device,
2192 .name = "RTL8251B 5Gbps PHY",
2193 .probe = rtl822x_probe,
2194 .get_features = rtl822x_get_features,
2195 .config_aneg = rtl822x_config_aneg,
2196 .read_status = rtl822x_read_status,
2197 .suspend = genphy_suspend,
2198 .resume = rtlgen_resume,
2199 .read_page = rtl821x_read_page,
2200 .write_page = rtl821x_write_page,
2201 }, {
2202 .match_phy_device = rtl_internal_nbaset_match_phy_device,
2203 .name = "Realtek Internal NBASE-T PHY",
2204 .flags = PHY_IS_INTERNAL,
2205 .probe = rtl822x_probe,
2206 .get_features = rtl822x_get_features,
2207 .config_aneg = rtl822x_config_aneg,
2208 .read_status = rtl822x_read_status,
2209 .suspend = genphy_suspend,
2210 .resume = rtlgen_resume,
2211 .read_page = rtl821x_read_page,
2212 .write_page = rtl821x_write_page,
2213 .read_mmd = rtl822x_read_mmd,
2214 .write_mmd = rtl822x_write_mmd,
2215 }, {
2216 PHY_ID_MATCH_EXACT(0x001ccad0),
2217 .name = "RTL8224 2.5Gbps PHY",
2218 .flags = PHY_POLL_CABLE_TEST,
2219 .get_features = rtl822x_c45_get_features,
2220 .config_aneg = rtl822x_c45_config_aneg,
2221 .read_status = rtl822x_c45_read_status,
2222 .suspend = genphy_c45_pma_suspend,
2223 .resume = rtlgen_c45_resume,
2224 .cable_test_start = rtl8224_cable_test_start,
2225 .cable_test_get_status = rtl8224_cable_test_get_status,
2226 }, {
2227 PHY_ID_MATCH_EXACT(0x001cc961),
2228 .name = "RTL8366RB Gigabit Ethernet",
2229 .config_init = &rtl8366rb_config_init,
2230 /* These interrupts are handled by the irq controller
2231 * embedded inside the RTL8366RB, they get unmasked when the
2232 * irq is requested and ACKed by reading the status register,
2233 * which is done by the irqchip code.
2234 */
2235 .config_intr = genphy_no_config_intr,
2236 .handle_interrupt = genphy_handle_interrupt_no_ack,
2237 .suspend = genphy_suspend,
2238 .resume = genphy_resume,
2239 }, {
2240 PHY_ID_MATCH_EXACT(0x001ccb00),
2241 .name = "RTL9000AA_RTL9000AN Ethernet",
2242 .features = PHY_BASIC_T1_FEATURES,
2243 .config_init = rtl9000a_config_init,
2244 .config_aneg = rtl9000a_config_aneg,
2245 .read_status = rtl9000a_read_status,
2246 .config_intr = rtl9000a_config_intr,
2247 .handle_interrupt = rtl9000a_handle_interrupt,
2248 .suspend = genphy_suspend,
2249 .resume = genphy_resume,
2250 .read_page = rtl821x_read_page,
2251 .write_page = rtl821x_write_page,
2252 }, {
2253 PHY_ID_MATCH_EXACT(0x001cc942),
2254 .name = "RTL8365MB-VC Gigabit Ethernet",
2255 /* Interrupt handling analogous to RTL8366RB */
2256 .config_intr = genphy_no_config_intr,
2257 .handle_interrupt = genphy_handle_interrupt_no_ack,
2258 .suspend = genphy_suspend,
2259 .resume = genphy_resume,
2260 }, {
2261 PHY_ID_MATCH_EXACT(0x001cc960),
2262 .name = "RTL8366S Gigabit Ethernet",
2263 .suspend = genphy_suspend,
2264 .resume = genphy_resume,
2265 .read_mmd = genphy_read_mmd_unsupported,
2266 .write_mmd = genphy_write_mmd_unsupported,
2267 },
2268 };
2269
2270 module_phy_driver(realtek_drvs);
2271
2272 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
2273 { PHY_ID_MATCH_VENDOR(0x001cc800) },
2274 { }
2275 };
2276
2277 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
2278