1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * rtase is the Linux device driver released for Realtek Automotive Switch 4 * controllers with PCI-Express interface. 5 * 6 * Copyright(c) 2024 Realtek Semiconductor Corp. 7 */ 8 9 #ifndef RTASE_H 10 #define RTASE_H 11 12 #define RTASE_HW_VER_MASK 0x7C800000 13 #define RTASE_HW_VER_906X_7XA 0x00800000 14 #define RTASE_HW_VER_906X_7XC 0x04000000 15 #define RTASE_HW_VER_907XD_V1 0x04800000 16 17 #define RTASE_RX_DMA_BURST_256 4 18 #define RTASE_TX_DMA_BURST_UNLIMITED 7 19 20 #define RTASE_RX_BUF_SIZE (PAGE_SIZE - \ 21 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 22 #define RTASE_MAX_JUMBO_SIZE (RTASE_RX_BUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 23 24 /* 3 means InterFrameGap = the shortest one */ 25 #define RTASE_INTERFRAMEGAP 0x03 26 27 #define RTASE_REGS_SIZE 256 28 #define RTASE_PCI_REGS_SIZE 0x100 29 30 #define RTASE_MULTICAST_FILTER_MASK GENMASK(30, 26) 31 32 #define RTASE_VLAN_FILTER_ENTRY_NUM 32 33 #define RTASE_NUM_TX_QUEUE 8 34 #define RTASE_NUM_RX_QUEUE 4 35 36 #define RTASE_TXQ_CTRL 1 37 #define RTASE_FUNC_TXQ_NUM 1 38 #define RTASE_FUNC_RXQ_NUM 1 39 #define RTASE_INTERRUPT_NUM 1 40 41 #define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0) 42 #define RTASE_MITI_TIME_UNIT_MASK GENMASK(7, 4) 43 #define RTASE_MITI_DEFAULT_TIME 128 44 #define RTASE_MITI_MAX_TIME 491520 45 #define RTASE_MITI_PKT_NUM_COUNT_MASK GENMASK(11, 8) 46 #define RTASE_MITI_PKT_NUM_UNIT_MASK GENMASK(13, 12) 47 #define RTASE_MITI_DEFAULT_PKT_NUM 64 48 #define RTASE_MITI_MAX_PKT_NUM_IDX 3 49 #define RTASE_MITI_MAX_PKT_NUM_UNIT 16 50 #define RTASE_MITI_MAX_PKT_NUM 240 51 #define RTASE_MITI_COUNT_BIT_NUM 4 52 53 #define RTASE_NUM_MSIX 4 54 55 #define RTASE_DWORD_MOD 16 56 57 /*****************************************************************************/ 58 enum rtase_registers { 59 RTASE_MAC0 = 0x0000, 60 RTASE_MAC4 = 0x0004, 61 RTASE_MAR0 = 0x0008, 62 RTASE_MAR1 = 0x000C, 63 RTASE_DTCCR0 = 0x0010, 64 RTASE_DTCCR4 = 0x0014, 65 #define RTASE_COUNTER_RESET BIT(0) 66 #define RTASE_COUNTER_DUMP BIT(3) 67 68 RTASE_FCR = 0x0018, 69 #define RTASE_FCR_RXQ_MASK GENMASK(5, 4) 70 71 RTASE_LBK_CTRL = 0x001A, 72 #define RTASE_LBK_ATLD BIT(1) 73 #define RTASE_LBK_CLR BIT(0) 74 75 RTASE_TX_DESC_ADDR0 = 0x0020, 76 RTASE_TX_DESC_ADDR4 = 0x0024, 77 RTASE_TX_DESC_COMMAND = 0x0028, 78 #define RTASE_TX_DESC_CMD_CS BIT(15) 79 #define RTASE_TX_DESC_CMD_WE BIT(14) 80 81 RTASE_BOOT_CTL = 0x6004, 82 RTASE_CLKSW_SET = 0x6018, 83 84 RTASE_CHIP_CMD = 0x0037, 85 #define RTASE_STOP_REQ BIT(7) 86 #define RTASE_STOP_REQ_DONE BIT(6) 87 #define RTASE_RE BIT(3) 88 #define RTASE_TE BIT(2) 89 90 RTASE_IMR0 = 0x0038, 91 RTASE_ISR0 = 0x003C, 92 #define RTASE_TOK7 BIT(30) 93 #define RTASE_TOK6 BIT(28) 94 #define RTASE_TOK5 BIT(26) 95 #define RTASE_TOK4 BIT(24) 96 #define RTASE_FOVW BIT(6) 97 #define RTASE_RDU BIT(4) 98 #define RTASE_TOK BIT(2) 99 #define RTASE_ROK BIT(0) 100 101 RTASE_IMR1 = 0x0800, 102 RTASE_ISR1 = 0x0802, 103 #define RTASE_Q_TOK BIT(4) 104 #define RTASE_Q_RDU BIT(1) 105 #define RTASE_Q_ROK BIT(0) 106 107 RTASE_EPHY_ISR = 0x6014, 108 RTASE_EPHY_IMR = 0x6016, 109 110 RTASE_TX_CONFIG_0 = 0x0040, 111 #define RTASE_TX_INTER_FRAME_GAP_MASK GENMASK(25, 24) 112 /* DMA burst value (0-7) is shift this many bits */ 113 #define RTASE_TX_DMA_MASK GENMASK(10, 8) 114 115 RTASE_RX_CONFIG_0 = 0x0044, 116 #define RTASE_RX_SINGLE_FETCH BIT(14) 117 #define RTASE_RX_SINGLE_TAG BIT(13) 118 #define RTASE_RX_MX_DMA_MASK GENMASK(10, 8) 119 #define RTASE_ACPT_FLOW BIT(7) 120 #define RTASE_ACCEPT_ERR BIT(5) 121 #define RTASE_ACCEPT_RUNT BIT(4) 122 #define RTASE_ACCEPT_BROADCAST BIT(3) 123 #define RTASE_ACCEPT_MULTICAST BIT(2) 124 #define RTASE_ACCEPT_MYPHYS BIT(1) 125 #define RTASE_ACCEPT_ALLPHYS BIT(0) 126 #define RTASE_ACCEPT_MASK (RTASE_ACPT_FLOW | RTASE_ACCEPT_ERR | \ 127 RTASE_ACCEPT_RUNT | RTASE_ACCEPT_BROADCAST | \ 128 RTASE_ACCEPT_MULTICAST | RTASE_ACCEPT_MYPHYS | \ 129 RTASE_ACCEPT_ALLPHYS) 130 131 RTASE_RX_CONFIG_1 = 0x0046, 132 #define RTASE_RX_MAX_FETCH_DESC_MASK GENMASK(15, 11) 133 #define RTASE_RX_NEW_DESC_FORMAT_EN BIT(8) 134 #define RTASE_OUTER_VLAN_DETAG_EN BIT(7) 135 #define RTASE_INNER_VLAN_DETAG_EN BIT(6) 136 #define RTASE_PCIE_NEW_FLOW BIT(2) 137 #define RTASE_PCIE_RELOAD_EN BIT(0) 138 139 RTASE_EEM = 0x0050, 140 #define RTASE_EEM_UNLOCK 0xC0 141 142 RTASE_TDFNR = 0x0057, 143 RTASE_TPPOLL = 0x0090, 144 RTASE_PDR = 0x00B0, 145 RTASE_FIFOR = 0x00D3, 146 #define RTASE_TX_FIFO_EMPTY BIT(5) 147 #define RTASE_RX_FIFO_EMPTY BIT(4) 148 149 RTASE_RMS = 0x00DA, 150 RTASE_CPLUS_CMD = 0x00E0, 151 #define RTASE_FORCE_RXFLOW_EN BIT(11) 152 #define RTASE_FORCE_TXFLOW_EN BIT(10) 153 #define RTASE_RX_CHKSUM BIT(5) 154 155 RTASE_Q0_RX_DESC_ADDR0 = 0x00E4, 156 RTASE_Q0_RX_DESC_ADDR4 = 0x00E8, 157 RTASE_Q1_RX_DESC_ADDR0 = 0x4000, 158 RTASE_Q1_RX_DESC_ADDR4 = 0x4004, 159 RTASE_MTPS = 0x00EC, 160 #define RTASE_TAG_NUM_SEL_MASK GENMASK(10, 8) 161 162 RTASE_MISC = 0x00F2, 163 #define RTASE_RX_DV_GATE_EN BIT(3) 164 165 RTASE_TFUN_CTRL = 0x0400, 166 #define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0) 167 168 RTASE_TX_CONFIG_1 = 0x203E, 169 #define RTASE_TC_MODE_MASK GENMASK(11, 10) 170 171 RTASE_TOKSEL = 0x2046, 172 RTASE_RFIFONFULL = 0x4406, 173 RTASE_INT_MITI_TX = 0x0A00, 174 RTASE_INT_MITI_RX = 0x0A80, 175 176 RTASE_VLAN_ENTRY_0 = 0xAC80, 177 }; 178 179 enum rtase_desc_status_bit { 180 RTASE_DESC_OWN = BIT(31), /* Descriptor is owned by NIC */ 181 RTASE_RING_END = BIT(30), /* End of descriptor ring */ 182 }; 183 184 enum rtase_sw_flag_content { 185 RTASE_SWF_MSI_ENABLED = BIT(1), 186 RTASE_SWF_MSIX_ENABLED = BIT(2), 187 }; 188 189 #define RSVD_MASK 0x3FFFC000 190 191 struct rtase_tx_desc { 192 __le32 opts1; 193 __le32 opts2; 194 __le64 addr; 195 __le32 opts3; 196 __le32 reserved1; 197 __le32 reserved2; 198 __le32 reserved3; 199 } __packed; 200 201 /*------ offset 0 of tx descriptor ------*/ 202 #define RTASE_TX_FIRST_FRAG BIT(29) /* Tx First segment of a packet */ 203 #define RTASE_TX_LAST_FRAG BIT(28) /* Tx Final segment of a packet */ 204 #define RTASE_GIANT_SEND_V4 BIT(26) /* TCP Giant Send Offload V4 (GSOv4) */ 205 #define RTASE_GIANT_SEND_V6 BIT(25) /* TCP Giant Send Offload V6 (GSOv6) */ 206 #define RTASE_TX_VLAN_TAG BIT(17) /* Add VLAN tag */ 207 208 /*------ offset 4 of tx descriptor ------*/ 209 #define RTASE_TX_UDPCS_C BIT(31) /* Calculate UDP/IP checksum */ 210 #define RTASE_TX_TCPCS_C BIT(30) /* Calculate TCP/IP checksum */ 211 #define RTASE_TX_IPCS_C BIT(29) /* Calculate IP checksum */ 212 #define RTASE_TX_IPV6F_C BIT(28) /* Indicate it is an IPv6 packet */ 213 214 union rtase_rx_desc { 215 struct { 216 __le64 header_buf_addr; 217 __le32 reserved1; 218 __le32 opts_header_len; 219 __le64 addr; 220 __le32 reserved2; 221 __le32 opts1; 222 } __packed desc_cmd; 223 224 struct { 225 __le32 reserved1; 226 __le32 reserved2; 227 __le32 rss; 228 __le32 opts4; 229 __le32 reserved3; 230 __le32 opts3; 231 __le32 opts2; 232 __le32 opts1; 233 } __packed desc_status; 234 } __packed; 235 236 /*------ offset 28 of rx descriptor ------*/ 237 #define RTASE_RX_FIRST_FRAG BIT(25) /* Rx First segment of a packet */ 238 #define RTASE_RX_LAST_FRAG BIT(24) /* Rx Final segment of a packet */ 239 #define RTASE_RX_RES BIT(20) 240 #define RTASE_RX_RUNT BIT(19) 241 #define RTASE_RX_RWT BIT(18) 242 #define RTASE_RX_CRC BIT(16) 243 #define RTASE_RX_V6F BIT(31) 244 #define RTASE_RX_V4F BIT(30) 245 #define RTASE_RX_UDPT BIT(29) 246 #define RTASE_RX_TCPT BIT(28) 247 #define RTASE_RX_IPF BIT(26) /* IP checksum failed */ 248 #define RTASE_RX_UDPF BIT(25) /* UDP/IP checksum failed */ 249 #define RTASE_RX_TCPF BIT(24) /* TCP/IP checksum failed */ 250 #define RTASE_RX_VLAN_TAG BIT(16) /* VLAN tag available */ 251 252 #define RTASE_NUM_DESC 1024 253 #define RTASE_TX_BUDGET_DEFAULT 256 254 #define RTASE_TX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(struct rtase_tx_desc)) 255 #define RTASE_RX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(union rtase_rx_desc)) 256 #define RTASE_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 257 #define RTASE_TX_START_THRS (2 * RTASE_TX_STOP_THRS) 258 #define RTASE_VLAN_TAG_MASK GENMASK(15, 0) 259 #define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0) 260 261 #define RTASE_IVEC_NAME_SIZE (IFNAMSIZ + 10) 262 263 struct rtase_int_vector { 264 struct rtase_private *tp; 265 unsigned int irq; 266 char name[RTASE_IVEC_NAME_SIZE]; 267 u16 index; 268 u16 imr_addr; 269 u16 isr_addr; 270 u32 imr; 271 struct list_head ring_list; 272 struct napi_struct napi; 273 int (*poll)(struct napi_struct *napi, int budget); 274 }; 275 276 struct rtase_ring { 277 struct rtase_int_vector *ivec; 278 void *desc; 279 dma_addr_t phy_addr; 280 u32 cur_idx; 281 u32 dirty_idx; 282 u16 index; 283 284 struct sk_buff *skbuff[RTASE_NUM_DESC]; 285 void *data_buf[RTASE_NUM_DESC]; 286 union { 287 u32 len[RTASE_NUM_DESC]; 288 dma_addr_t data_phy_addr[RTASE_NUM_DESC]; 289 } mis; 290 291 struct list_head ring_entry; 292 int (*ring_handler)(struct rtase_ring *ring, int budget); 293 u64 alloc_fail; 294 }; 295 296 struct rtase_stats { 297 u64 tx_dropped; 298 u64 rx_dropped; 299 u64 multicast; 300 u64 rx_errors; 301 u64 rx_length_errors; 302 u64 rx_crc_errors; 303 }; 304 305 struct rtase_private { 306 void __iomem *mmio_addr; 307 u32 sw_flag; 308 309 struct pci_dev *pdev; 310 struct net_device *dev; 311 u32 rx_buf_sz; 312 313 struct page_pool *page_pool; 314 struct rtase_ring tx_ring[RTASE_NUM_TX_QUEUE]; 315 struct rtase_ring rx_ring[RTASE_NUM_RX_QUEUE]; 316 struct rtase_counters *tally_vaddr; 317 dma_addr_t tally_paddr; 318 319 u32 vlan_filter_ctrl; 320 u16 vlan_filter_vid[RTASE_VLAN_FILTER_ENTRY_NUM]; 321 322 struct msix_entry msix_entry[RTASE_NUM_MSIX]; 323 struct rtase_int_vector int_vector[RTASE_NUM_MSIX]; 324 325 struct rtase_stats stats; 326 327 u16 tx_queue_ctrl; 328 u16 func_tx_queue_num; 329 u16 func_rx_queue_num; 330 u16 int_nums; 331 u16 tx_int_mit; 332 u16 rx_int_mit; 333 334 u32 hw_ver; 335 }; 336 337 #define RTASE_LSO_64K 64000 338 339 #define RTASE_NIC_MAX_PHYS_BUF_COUNT_LSO2 (16 * 4) 340 341 #define RTASE_TCPHO_MASK GENMASK(24, 18) 342 343 #define RTASE_MSS_MASK GENMASK(28, 18) 344 345 #endif /* RTASE_H */ 346