xref: /linux/sound/soc/codecs/rt5660.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * rt5660.h  --  RT5660 ALSA SoC audio driver
4  *
5  * Copyright 2016 Realtek Semiconductor Corp.
6  * Author: Oder Chiou <oder_chiou@realtek.com>
7  */
8 
9 #ifndef _RT5660_H
10 #define _RT5660_H
11 
12 #include <linux/clk.h>
13 #include <sound/rt5660.h>
14 
15 /* Info */
16 #define RT5660_RESET				0x00
17 #define RT5660_VENDOR_ID			0xfd
18 #define RT5660_VENDOR_ID1			0xfe
19 #define RT5660_VENDOR_ID2			0xff
20 /*  I/O - Output */
21 #define RT5660_SPK_VOL				0x01
22 #define RT5660_LOUT_VOL				0x02
23 /* I/O - Input */
24 #define RT5660_IN1_IN2				0x0d
25 #define RT5660_IN3_IN4				0x0e
26 /* I/O - ADC/DAC/DMIC */
27 #define RT5660_DAC1_DIG_VOL			0x19
28 #define RT5660_STO1_ADC_DIG_VOL			0x1c
29 #define RT5660_ADC_BST_VOL1			0x1e
30 /* Mixer - D-D */
31 #define RT5660_STO1_ADC_MIXER			0x27
32 #define RT5660_AD_DA_MIXER			0x29
33 #define RT5660_STO_DAC_MIXER			0x2a
34 #define RT5660_DIG_INF1_DATA			0x2f
35 /* Mixer - ADC */
36 #define RT5660_REC_L1_MIXER			0x3b
37 #define RT5660_REC_L2_MIXER			0x3c
38 #define RT5660_REC_R1_MIXER			0x3d
39 #define RT5660_REC_R2_MIXER			0x3e
40 /* Mixer - DAC */
41 #define RT5660_LOUT_MIXER			0x45
42 #define RT5660_SPK_MIXER			0x46
43 #define RT5660_SPO_MIXER			0x48
44 #define RT5660_SPO_CLSD_RATIO			0x4a
45 #define RT5660_OUT_L_GAIN1			0x4d
46 #define RT5660_OUT_L_GAIN2			0x4e
47 #define RT5660_OUT_L1_MIXER			0x4f
48 #define RT5660_OUT_R_GAIN1			0x50
49 #define RT5660_OUT_R_GAIN2			0x51
50 #define RT5660_OUT_R1_MIXER			0x52
51 /* Power */
52 #define RT5660_PWR_DIG1				0x61
53 #define RT5660_PWR_DIG2				0x62
54 #define RT5660_PWR_ANLG1			0x63
55 #define RT5660_PWR_ANLG2			0x64
56 #define RT5660_PWR_MIXER			0x65
57 #define RT5660_PWR_VOL				0x66
58 /* Private Register Control */
59 #define RT5660_PRIV_INDEX			0x6a
60 #define RT5660_PRIV_DATA			0x6c
61 /* Format - ADC/DAC */
62 #define RT5660_I2S1_SDP				0x70
63 #define RT5660_ADDA_CLK1			0x73
64 #define RT5660_ADDA_CLK2			0x74
65 #define RT5660_DMIC_CTRL1			0x75
66 /* Function - Analog */
67 #define RT5660_GLB_CLK				0x80
68 #define RT5660_PLL_CTRL1			0x81
69 #define RT5660_PLL_CTRL2			0x82
70 #define RT5660_CLSD_AMP_OC_CTRL			0x8c
71 #define RT5660_CLSD_AMP_CTRL			0x8d
72 #define RT5660_LOUT_AMP_CTRL			0x8e
73 #define RT5660_SPK_AMP_SPKVDD			0x92
74 #define RT5660_MICBIAS				0x93
75 #define RT5660_CLSD_OUT_CTRL1			0xa1
76 #define RT5660_CLSD_OUT_CTRL2			0xa2
77 #define RT5660_DIPOLE_MIC_CTRL1			0xa3
78 #define RT5660_DIPOLE_MIC_CTRL2			0xa4
79 #define RT5660_DIPOLE_MIC_CTRL3			0xa5
80 #define RT5660_DIPOLE_MIC_CTRL4			0xa6
81 #define RT5660_DIPOLE_MIC_CTRL5			0xa7
82 #define RT5660_DIPOLE_MIC_CTRL6			0xa8
83 #define RT5660_DIPOLE_MIC_CTRL7			0xa9
84 #define RT5660_DIPOLE_MIC_CTRL8			0xaa
85 #define RT5660_DIPOLE_MIC_CTRL9			0xab
86 #define RT5660_DIPOLE_MIC_CTRL10		0xac
87 #define RT5660_DIPOLE_MIC_CTRL11		0xad
88 #define RT5660_DIPOLE_MIC_CTRL12		0xae
89 /* Function - Digital */
90 #define RT5660_EQ_CTRL1				0xb0
91 #define RT5660_EQ_CTRL2				0xb1
92 #define RT5660_DRC_AGC_CTRL1			0xb3
93 #define RT5660_DRC_AGC_CTRL2			0xb4
94 #define RT5660_DRC_AGC_CTRL3			0xb5
95 #define RT5660_DRC_AGC_CTRL4			0xb6
96 #define RT5660_DRC_AGC_CTRL5			0xb7
97 #define RT5660_JD_CTRL				0xbb
98 #define RT5660_IRQ_CTRL1			0xbd
99 #define RT5660_IRQ_CTRL2			0xbe
100 #define RT5660_INT_IRQ_ST			0xbf
101 #define RT5660_GPIO_CTRL1			0xc0
102 #define RT5660_GPIO_CTRL2			0xc2
103 #define RT5660_WIND_FILTER_CTRL1		0xd3
104 #define RT5660_SV_ZCD1				0xd9
105 #define RT5660_SV_ZCD2				0xda
106 #define RT5660_DRC1_LM_CTRL1			0xe0
107 #define RT5660_DRC1_LM_CTRL2			0xe1
108 #define RT5660_DRC2_LM_CTRL1			0xe2
109 #define RT5660_DRC2_LM_CTRL2			0xe3
110 #define RT5660_MULTI_DRC_CTRL			0xe4
111 #define RT5660_DRC2_CTRL1			0xe5
112 #define RT5660_DRC2_CTRL2			0xe6
113 #define RT5660_DRC2_CTRL3			0xe7
114 #define RT5660_DRC2_CTRL4			0xe8
115 #define RT5660_DRC2_CTRL5			0xe9
116 #define RT5660_ALC_PGA_CTRL1			0xea
117 #define RT5660_ALC_PGA_CTRL2			0xeb
118 #define RT5660_ALC_PGA_CTRL3			0xec
119 #define RT5660_ALC_PGA_CTRL4			0xed
120 #define RT5660_ALC_PGA_CTRL5			0xee
121 #define RT5660_ALC_PGA_CTRL6			0xef
122 #define RT5660_ALC_PGA_CTRL7			0xf0
123 
124 /* General Control */
125 #define RT5660_GEN_CTRL1			0xfa
126 #define RT5660_GEN_CTRL2			0xfb
127 #define RT5660_GEN_CTRL3			0xfc
128 
129 /* Index of Codec Private Register definition */
130 #define RT5660_CHOP_DAC_ADC			0x3d
131 
132 /* Global Definition */
133 #define RT5660_L_MUTE				(0x1 << 15)
134 #define RT5660_L_MUTE_SFT			15
135 #define RT5660_VOL_L_MUTE			(0x1 << 14)
136 #define RT5660_VOL_L_SFT			14
137 #define RT5660_R_MUTE				(0x1 << 7)
138 #define RT5660_R_MUTE_SFT			7
139 #define RT5660_VOL_R_MUTE			(0x1 << 6)
140 #define RT5660_VOL_R_SFT			6
141 #define RT5660_L_VOL_MASK			(0x3f << 8)
142 #define RT5660_L_VOL_SFT			8
143 #define RT5660_R_VOL_MASK			(0x3f)
144 #define RT5660_R_VOL_SFT			0
145 
146 /* IN1 and IN2 Control (0x0d) */
147 #define RT5660_IN_DF1				(0x1 << 15)
148 #define RT5660_IN_SFT1				15
149 #define RT5660_BST_MASK1			(0x7f << 8)
150 #define RT5660_BST_SFT1				8
151 #define RT5660_IN_DF2				(0x1 << 7)
152 #define RT5660_IN_SFT2				7
153 #define RT5660_BST_MASK2			(0x7f << 0)
154 #define RT5660_BST_SFT2				0
155 
156 /* IN3 and IN4 Control (0x0e) */
157 #define RT5660_IN_DF3				(0x1 << 15)
158 #define RT5660_IN_SFT3				15
159 #define RT5660_BST_MASK3			(0x7f << 8)
160 #define RT5660_BST_SFT3				8
161 #define RT5660_IN_DF4				(0x1 << 7)
162 #define RT5660_IN_SFT4				7
163 #define RT5660_BST_MASK4			(0x7f << 0)
164 #define RT5660_BST_SFT4				0
165 
166 /* DAC1 Digital Volume (0x19) */
167 #define RT5660_DAC_L1_VOL_MASK			(0x7f << 9)
168 #define RT5660_DAC_L1_VOL_SFT			9
169 #define RT5660_DAC_R1_VOL_MASK			(0x7f << 1)
170 #define RT5660_DAC_R1_VOL_SFT			1
171 
172 /* ADC Digital Volume Control (0x1c) */
173 #define RT5660_ADC_L_VOL_MASK			(0x3f << 9)
174 #define RT5660_ADC_L_VOL_SFT			9
175 #define RT5660_ADC_R_VOL_MASK			(0x3f << 1)
176 #define RT5660_ADC_R_VOL_SFT			1
177 
178 /* ADC Boost Volume Control (0x1e) */
179 #define RT5660_STO1_ADC_L_BST_MASK		(0x3 << 14)
180 #define RT5660_STO1_ADC_L_BST_SFT		14
181 #define RT5660_STO1_ADC_R_BST_MASK		(0x3 << 12)
182 #define RT5660_STO1_ADC_R_BST_SFT		12
183 
184 /* Stereo ADC Mixer Control (0x27) */
185 #define RT5660_M_ADC_L1				(0x1 << 14)
186 #define RT5660_M_ADC_L1_SFT			14
187 #define RT5660_M_ADC_L2				(0x1 << 13)
188 #define RT5660_M_ADC_L2_SFT			13
189 #define RT5660_M_ADC_R1				(0x1 << 6)
190 #define RT5660_M_ADC_R1_SFT			6
191 #define RT5660_M_ADC_R2				(0x1 << 5)
192 #define RT5660_M_ADC_R2_SFT			5
193 
194 /* ADC Mixer to DAC Mixer Control (0x29) */
195 #define RT5660_M_ADCMIX_L			(0x1 << 15)
196 #define RT5660_M_ADCMIX_L_SFT			15
197 #define RT5660_M_DAC1_L				(0x1 << 14)
198 #define RT5660_M_DAC1_L_SFT			14
199 #define RT5660_M_ADCMIX_R			(0x1 << 7)
200 #define RT5660_M_ADCMIX_R_SFT			7
201 #define RT5660_M_DAC1_R				(0x1 << 6)
202 #define RT5660_M_DAC1_R_SFT			6
203 
204 /* Stereo DAC Mixer Control (0x2a) */
205 #define RT5660_M_DAC_L1				(0x1 << 14)
206 #define RT5660_M_DAC_L1_SFT			14
207 #define RT5660_DAC_L1_STO_L_VOL_MASK		(0x1 << 13)
208 #define RT5660_DAC_L1_STO_L_VOL_SFT		13
209 #define RT5660_M_DAC_R1_STO_L			(0x1 << 9)
210 #define RT5660_M_DAC_R1_STO_L_SFT		9
211 #define RT5660_DAC_R1_STO_L_VOL_MASK		(0x1 << 8)
212 #define RT5660_DAC_R1_STO_L_VOL_SFT		8
213 #define RT5660_M_DAC_R1				(0x1 << 6)
214 #define RT5660_M_DAC_R1_SFT			6
215 #define RT5660_DAC_R1_STO_R_VOL_MASK		(0x1 << 5)
216 #define RT5660_DAC_R1_STO_R_VOL_SFT		5
217 #define RT5660_M_DAC_L1_STO_R			(0x1 << 1)
218 #define RT5660_M_DAC_L1_STO_R_SFT		1
219 #define RT5660_DAC_L1_STO_R_VOL_MASK		(0x1)
220 #define RT5660_DAC_L1_STO_R_VOL_SFT		0
221 
222 /* Digital Interface Data Control (0x2f) */
223 #define RT5660_IF1_DAC_IN_SEL			(0x3 << 14)
224 #define RT5660_IF1_DAC_IN_SFT			14
225 #define RT5660_IF1_ADC_IN_SEL			(0x3 << 12)
226 #define RT5660_IF1_ADC_IN_SFT			12
227 
228 /* REC Left Mixer Control 1 (0x3b) */
229 #define RT5660_G_BST3_RM_L_MASK			(0x7 << 4)
230 #define RT5660_G_BST3_RM_L_SFT			4
231 #define RT5660_G_BST2_RM_L_MASK			(0x7 << 1)
232 #define RT5660_G_BST2_RM_L_SFT			1
233 
234 /* REC Left Mixer Control 2 (0x3c) */
235 #define RT5660_G_BST1_RM_L_MASK			(0x7 << 13)
236 #define RT5660_G_BST1_RM_L_SFT			13
237 #define RT5660_G_OM_L_RM_L_MASK			(0x7 << 10)
238 #define RT5660_G_OM_L_RM_L_SFT			10
239 #define RT5660_M_BST3_RM_L			(0x1 << 3)
240 #define RT5660_M_BST3_RM_L_SFT			3
241 #define RT5660_M_BST2_RM_L			(0x1 << 2)
242 #define RT5660_M_BST2_RM_L_SFT			2
243 #define RT5660_M_BST1_RM_L			(0x1 << 1)
244 #define RT5660_M_BST1_RM_L_SFT			1
245 #define RT5660_M_OM_L_RM_L			(0x1)
246 #define RT5660_M_OM_L_RM_L_SFT			0
247 
248 /* REC Right Mixer Control 1 (0x3d) */
249 #define RT5660_G_BST3_RM_R_MASK			(0x7 << 4)
250 #define RT5660_G_BST3_RM_R_SFT			4
251 #define RT5660_G_BST2_RM_R_MASK			(0x7 << 1)
252 #define RT5660_G_BST2_RM_R_SFT			1
253 
254 /* REC Right Mixer Control 2 (0x3e) */
255 #define RT5660_G_BST1_RM_R_MASK			(0x7 << 13)
256 #define RT5660_G_BST1_RM_R_SFT			13
257 #define RT5660_G_OM_R_RM_R_MASK			(0x7 << 10)
258 #define RT5660_G_OM_R_RM_R_SFT			10
259 #define RT5660_M_BST3_RM_R			(0x1 << 3)
260 #define RT5660_M_BST3_RM_R_SFT			3
261 #define RT5660_M_BST2_RM_R			(0x1 << 2)
262 #define RT5660_M_BST2_RM_R_SFT			2
263 #define RT5660_M_BST1_RM_R			(0x1 << 1)
264 #define RT5660_M_BST1_RM_R_SFT			1
265 #define RT5660_M_OM_R_RM_R			(0x1)
266 #define RT5660_M_OM_R_RM_R_SFT			0
267 
268 /* LOUTMIX Control (0x45) */
269 #define RT5660_M_DAC1_LM			(0x1 << 14)
270 #define RT5660_M_DAC1_LM_SFT			14
271 #define RT5660_M_LOVOL_M			(0x1 << 13)
272 #define RT5660_M_LOVOL_LM_SFT			13
273 
274 /* SPK Mixer Control (0x46) */
275 #define RT5660_G_BST3_SM_MASK			(0x3 << 14)
276 #define RT5660_G_BST3_SM_SFT			14
277 #define RT5660_G_BST1_SM_MASK			(0x3 << 12)
278 #define RT5660_G_BST1_SM_SFT			12
279 #define RT5660_G_DACl_SM_MASK			(0x3 << 10)
280 #define RT5660_G_DACl_SM_SFT			10
281 #define RT5660_G_DACR_SM_MASK			(0x3 << 8)
282 #define RT5660_G_DACR_SM_SFT			8
283 #define RT5660_G_OM_L_SM_MASK			(0x3 << 6)
284 #define RT5660_G_OM_L_SM_SFT			6
285 #define RT5660_M_DACR_SM			(0x1 << 5)
286 #define RT5660_M_DACR_SM_SFT			5
287 #define RT5660_M_BST1_SM			(0x1 << 4)
288 #define RT5660_M_BST1_SM_SFT			4
289 #define RT5660_M_BST3_SM			(0x1 << 3)
290 #define RT5660_M_BST3_SM_SFT			3
291 #define RT5660_M_DACL_SM			(0x1 << 2)
292 #define RT5660_M_DACL_SM_SFT			2
293 #define RT5660_M_OM_L_SM			(0x1 << 1)
294 #define RT5660_M_OM_L_SM_SFT			1
295 
296 /* SPOMIX Control (0x48) */
297 #define RT5660_M_DAC_R_SPM			(0x1 << 14)
298 #define RT5660_M_DAC_R_SPM_SFT			14
299 #define RT5660_M_DAC_L_SPM			(0x1 << 13)
300 #define RT5660_M_DAC_L_SPM_SFT			13
301 #define RT5660_M_SV_SPM				(0x1 << 12)
302 #define RT5660_M_SV_SPM_SFT			12
303 #define RT5660_M_BST1_SPM			(0x1 << 11)
304 #define RT5660_M_BST1_SPM_SFT			11
305 
306 /* Output Left Mixer Control 1 (0x4d) */
307 #define RT5660_G_BST3_OM_L_MASK			(0x7 << 13)
308 #define RT5660_G_BST3_OM_L_SFT			13
309 #define RT5660_G_BST2_OM_L_MASK			(0x7 << 10)
310 #define RT5660_G_BST2_OM_L_SFT			10
311 #define RT5660_G_BST1_OM_L_MASK			(0x7 << 7)
312 #define RT5660_G_BST1_OM_L_SFT			7
313 #define RT5660_G_RM_L_OM_L_MASK			(0x7 << 1)
314 #define RT5660_G_RM_L_OM_L_SFT			1
315 
316 /* Output Left Mixer Control 2 (0x4e) */
317 #define RT5660_G_DAC_R1_OM_L_MASK		(0x7 << 10)
318 #define RT5660_G_DAC_R1_OM_L_SFT		10
319 #define RT5660_G_DAC_L1_OM_L_MASK		(0x7 << 7)
320 #define RT5660_G_DAC_L1_OM_L_SFT		7
321 
322 /* Output Left Mixer Control 3 (0x4f) */
323 #define RT5660_M_BST3_OM_L			(0x1 << 5)
324 #define RT5660_M_BST3_OM_L_SFT			5
325 #define RT5660_M_BST2_OM_L			(0x1 << 4)
326 #define RT5660_M_BST2_OM_L_SFT			4
327 #define RT5660_M_BST1_OM_L			(0x1 << 3)
328 #define RT5660_M_BST1_OM_L_SFT			3
329 #define RT5660_M_RM_L_OM_L			(0x1 << 2)
330 #define RT5660_M_RM_L_OM_L_SFT			2
331 #define RT5660_M_DAC_R_OM_L			(0x1 << 1)
332 #define RT5660_M_DAC_R_OM_L_SFT			1
333 #define RT5660_M_DAC_L_OM_L			(0x1)
334 #define RT5660_M_DAC_L_OM_L_SFT			0
335 
336 /* Output Right Mixer Control 1 (0x50) */
337 #define RT5660_G_BST2_OM_R_MASK			(0x7 << 10)
338 #define RT5660_G_BST2_OM_R_SFT			10
339 #define RT5660_G_BST1_OM_R_MASK			(0x7 << 7)
340 #define RT5660_G_BST1_OM_R_SFT			7
341 #define RT5660_G_RM_R_OM_R_MASK			(0x7 << 1)
342 #define RT5660_G_RM_R_OM_R_SFT			1
343 
344 /* Output Right Mixer Control 2 (0x51) */
345 #define RT5660_G_DAC_L_OM_R_MASK		(0x7 << 10)
346 #define RT5660_G_DAC_L_OM_R_SFT			10
347 #define RT5660_G_DAC_R_OM_R_MASK		(0x7 << 7)
348 #define RT5660_G_DAC_R_OM_R_SFT			7
349 
350 /* Output Right Mixer Control 3 (0x52) */
351 #define RT5660_M_BST2_OM_R			(0x1 << 4)
352 #define RT5660_M_BST2_OM_R_SFT			4
353 #define RT5660_M_BST1_OM_R			(0x1 << 3)
354 #define RT5660_M_BST1_OM_R_SFT			3
355 #define RT5660_M_RM_R_OM_R			(0x1 << 2)
356 #define RT5660_M_RM_R_OM_R_SFT			2
357 #define RT5660_M_DAC_L_OM_R			(0x1 << 1)
358 #define RT5660_M_DAC_L_OM_R_SFT			1
359 #define RT5660_M_DAC_R_OM_R			(0x1)
360 #define RT5660_M_DAC_R_OM_R_SFT			0
361 
362 /* Power Management for Digital 1 (0x61) */
363 #define RT5660_PWR_I2S1				(0x1 << 15)
364 #define RT5660_PWR_I2S1_BIT			15
365 #define RT5660_PWR_DAC_L1			(0x1 << 12)
366 #define RT5660_PWR_DAC_L1_BIT			12
367 #define RT5660_PWR_DAC_R1			(0x1 << 11)
368 #define RT5660_PWR_DAC_R1_BIT			11
369 #define RT5660_PWR_ADC_L			(0x1 << 2)
370 #define RT5660_PWR_ADC_L_BIT			2
371 #define RT5660_PWR_ADC_R			(0x1 << 1)
372 #define RT5660_PWR_ADC_R_BIT			1
373 #define RT5660_PWR_CLS_D			(0x1)
374 #define RT5660_PWR_CLS_D_BIT			0
375 
376 /* Power Management for Digital 2 (0x62) */
377 #define RT5660_PWR_ADC_S1F			(0x1 << 15)
378 #define RT5660_PWR_ADC_S1F_BIT			15
379 #define RT5660_PWR_DAC_S1F			(0x1 << 11)
380 #define RT5660_PWR_DAC_S1F_BIT			11
381 
382 /* Power Management for Analog 1 (0x63) */
383 #define RT5660_PWR_VREF1			(0x1 << 15)
384 #define RT5660_PWR_VREF1_BIT			15
385 #define RT5660_PWR_FV1				(0x1 << 14)
386 #define RT5660_PWR_FV1_BIT			14
387 #define RT5660_PWR_MB				(0x1 << 13)
388 #define RT5660_PWR_MB_BIT			13
389 #define RT5660_PWR_BG				(0x1 << 11)
390 #define RT5660_PWR_BG_BIT			11
391 #define RT5660_PWR_HP_L				(0x1 << 7)
392 #define RT5660_PWR_HP_L_BIT			7
393 #define RT5660_PWR_HP_R				(0x1 << 6)
394 #define RT5660_PWR_HP_R_BIT			6
395 #define RT5660_PWR_HA				(0x1 << 5)
396 #define RT5660_PWR_HA_BIT			5
397 #define RT5660_PWR_VREF2			(0x1 << 4)
398 #define RT5660_PWR_VREF2_BIT			4
399 #define RT5660_PWR_FV2				(0x1 << 3)
400 #define RT5660_PWR_FV2_BIT			3
401 #define RT5660_PWR_LDO2				(0x1 << 2)
402 #define RT5660_PWR_LDO2_BIT			2
403 
404 /* Power Management for Analog 2 (0x64) */
405 #define RT5660_PWR_BST1				(0x1 << 15)
406 #define RT5660_PWR_BST1_BIT			15
407 #define RT5660_PWR_BST2				(0x1 << 14)
408 #define RT5660_PWR_BST2_BIT			14
409 #define RT5660_PWR_BST3				(0x1 << 13)
410 #define RT5660_PWR_BST3_BIT			13
411 #define RT5660_PWR_MB1				(0x1 << 11)
412 #define RT5660_PWR_MB1_BIT			11
413 #define RT5660_PWR_MB2				(0x1 << 10)
414 #define RT5660_PWR_MB2_BIT			10
415 #define RT5660_PWR_PLL				(0x1 << 9)
416 #define RT5660_PWR_PLL_BIT			9
417 
418 /* Power Management for Mixer (0x65) */
419 #define RT5660_PWR_OM_L				(0x1 << 15)
420 #define RT5660_PWR_OM_L_BIT			15
421 #define RT5660_PWR_OM_R				(0x1 << 14)
422 #define RT5660_PWR_OM_R_BIT			14
423 #define RT5660_PWR_SM				(0x1 << 13)
424 #define RT5660_PWR_SM_BIT			13
425 #define RT5660_PWR_RM_L				(0x1 << 11)
426 #define RT5660_PWR_RM_L_BIT			11
427 #define RT5660_PWR_RM_R				(0x1 << 10)
428 #define RT5660_PWR_RM_R_BIT			10
429 
430 /* Power Management for Volume (0x66) */
431 #define RT5660_PWR_SV				(0x1 << 15)
432 #define RT5660_PWR_SV_BIT			15
433 #define RT5660_PWR_LV_L				(0x1 << 11)
434 #define RT5660_PWR_LV_L_BIT			11
435 #define RT5660_PWR_LV_R				(0x1 << 10)
436 #define RT5660_PWR_LV_R_BIT			10
437 
438 /* I2S1 Audio Serial Data Port Control (0x70) */
439 #define RT5660_I2S_MS_MASK			(0x1 << 15)
440 #define RT5660_I2S_MS_SFT			15
441 #define RT5660_I2S_MS_M				(0x0 << 15)
442 #define RT5660_I2S_MS_S				(0x1 << 15)
443 #define RT5660_I2S_O_CP_MASK			(0x3 << 10)
444 #define RT5660_I2S_O_CP_SFT			10
445 #define RT5660_I2S_O_CP_OFF			(0x0 << 10)
446 #define RT5660_I2S_O_CP_U_LAW			(0x1 << 10)
447 #define RT5660_I2S_O_CP_A_LAW			(0x2 << 10)
448 #define RT5660_I2S_I_CP_MASK			(0x3 << 8)
449 #define RT5660_I2S_I_CP_SFT			8
450 #define RT5660_I2S_I_CP_OFF			(0x0 << 8)
451 #define RT5660_I2S_I_CP_U_LAW			(0x1 << 8)
452 #define RT5660_I2S_I_CP_A_LAW			(0x2 << 8)
453 #define RT5660_I2S_BP_MASK			(0x1 << 7)
454 #define RT5660_I2S_BP_SFT			7
455 #define RT5660_I2S_BP_NOR			(0x0 << 7)
456 #define RT5660_I2S_BP_INV			(0x1 << 7)
457 #define RT5660_I2S_DL_MASK			(0x3 << 2)
458 #define RT5660_I2S_DL_SFT			2
459 #define RT5660_I2S_DL_16			(0x0 << 2)
460 #define RT5660_I2S_DL_20			(0x1 << 2)
461 #define RT5660_I2S_DL_24			(0x2 << 2)
462 #define RT5660_I2S_DL_8				(0x3 << 2)
463 #define RT5660_I2S_DF_MASK			(0x3)
464 #define RT5660_I2S_DF_SFT			0
465 #define RT5660_I2S_DF_I2S			(0x0)
466 #define RT5660_I2S_DF_LEFT			(0x1)
467 #define RT5660_I2S_DF_PCM_A			(0x2)
468 #define RT5660_I2S_DF_PCM_B			(0x3)
469 
470 /* ADC/DAC Clock Control 1 (0x73) */
471 #define RT5660_I2S_BCLK_MS1_MASK		(0x1 << 15)
472 #define RT5660_I2S_BCLK_MS1_SFT			15
473 #define RT5660_I2S_BCLK_MS1_32			(0x0 << 15)
474 #define RT5660_I2S_BCLK_MS1_64			(0x1 << 15)
475 #define RT5660_I2S_PD1_MASK			(0x7 << 12)
476 #define RT5660_I2S_PD1_SFT			12
477 #define RT5660_I2S_PD1_1			(0x0 << 12)
478 #define RT5660_I2S_PD1_2			(0x1 << 12)
479 #define RT5660_I2S_PD1_3			(0x2 << 12)
480 #define RT5660_I2S_PD1_4			(0x3 << 12)
481 #define RT5660_I2S_PD1_6			(0x4 << 12)
482 #define RT5660_I2S_PD1_8			(0x5 << 12)
483 #define RT5660_I2S_PD1_12			(0x6 << 12)
484 #define RT5660_I2S_PD1_16			(0x7 << 12)
485 #define RT5660_DAC_OSR_MASK			(0x3 << 2)
486 #define RT5660_DAC_OSR_SFT			2
487 #define RT5660_DAC_OSR_128			(0x0 << 2)
488 #define RT5660_DAC_OSR_64			(0x1 << 2)
489 #define RT5660_DAC_OSR_32			(0x2 << 2)
490 #define RT5660_DAC_OSR_16			(0x3 << 2)
491 #define RT5660_ADC_OSR_MASK			(0x3)
492 #define RT5660_ADC_OSR_SFT			0
493 #define RT5660_ADC_OSR_128			(0x0)
494 #define RT5660_ADC_OSR_64			(0x1)
495 #define RT5660_ADC_OSR_32			(0x2)
496 #define RT5660_ADC_OSR_16			(0x3)
497 
498 /* ADC/DAC Clock Control 2 (0x74) */
499 #define RT5660_RESET_ADF			(0x1 << 13)
500 #define RT5660_RESET_ADF_SFT			13
501 #define RT5660_RESET_DAF			(0x1 << 12)
502 #define RT5660_RESET_DAF_SFT			12
503 #define RT5660_DAHPF_EN				(0x1 << 11)
504 #define RT5660_DAHPF_EN_SFT			11
505 #define RT5660_ADHPF_EN				(0x1 << 10)
506 #define RT5660_ADHPF_EN_SFT			10
507 
508 /* Digital Microphone Control (0x75) */
509 #define RT5660_DMIC_1_EN_MASK			(0x1 << 15)
510 #define RT5660_DMIC_1_EN_SFT			15
511 #define RT5660_DMIC_1_DIS			(0x0 << 15)
512 #define RT5660_DMIC_1_EN			(0x1 << 15)
513 #define RT5660_DMIC_1L_LH_MASK			(0x1 << 13)
514 #define RT5660_DMIC_1L_LH_SFT			13
515 #define RT5660_DMIC_1L_LH_RISING		(0x0 << 13)
516 #define RT5660_DMIC_1L_LH_FALLING		(0x1 << 13)
517 #define RT5660_DMIC_1R_LH_MASK			(0x1 << 12)
518 #define RT5660_DMIC_1R_LH_SFT			12
519 #define RT5660_DMIC_1R_LH_RISING		(0x0 << 12)
520 #define RT5660_DMIC_1R_LH_FALLING		(0x1 << 12)
521 #define RT5660_SEL_DMIC_DATA_MASK		(0x1 << 11)
522 #define RT5660_SEL_DMIC_DATA_SFT		11
523 #define RT5660_SEL_DMIC_DATA_GPIO2		(0x0 << 11)
524 #define RT5660_SEL_DMIC_DATA_IN1P		(0x1 << 11)
525 #define RT5660_DMIC_CLK_MASK			(0x7 << 5)
526 #define RT5660_DMIC_CLK_SFT			5
527 
528 /* Global Clock Control (0x80) */
529 #define RT5660_SCLK_SRC_MASK			(0x3 << 14)
530 #define RT5660_SCLK_SRC_SFT			14
531 #define RT5660_SCLK_SRC_MCLK			(0x0 << 14)
532 #define RT5660_SCLK_SRC_PLL1			(0x1 << 14)
533 #define RT5660_SCLK_SRC_RCCLK			(0x2 << 14)
534 #define RT5660_PLL1_SRC_MASK			(0x3 << 12)
535 #define RT5660_PLL1_SRC_SFT			12
536 #define RT5660_PLL1_SRC_MCLK			(0x0 << 12)
537 #define RT5660_PLL1_SRC_BCLK1			(0x1 << 12)
538 #define RT5660_PLL1_SRC_RCCLK			(0x2 << 12)
539 #define RT5660_PLL1_PD_MASK			(0x1 << 3)
540 #define RT5660_PLL1_PD_SFT			3
541 #define RT5660_PLL1_PD_1			(0x0 << 3)
542 #define RT5660_PLL1_PD_2			(0x1 << 3)
543 
544 #define RT5660_PLL_INP_MAX			40000000
545 #define RT5660_PLL_INP_MIN			256000
546 /* PLL M/N/K Code Control 1 (0x81) */
547 #define RT5660_PLL_N_MAX			0x1ff
548 #define RT5660_PLL_N_MASK			(RT5660_PLL_N_MAX << 7)
549 #define RT5660_PLL_N_SFT			7
550 #define RT5660_PLL_K_MAX			0x1f
551 #define RT5660_PLL_K_MASK			(RT5660_PLL_K_MAX)
552 #define RT5660_PLL_K_SFT			0
553 
554 /* PLL M/N/K Code Control 2 (0x82) */
555 #define RT5660_PLL_M_MAX			0xf
556 #define RT5660_PLL_M_MASK			(RT5660_PLL_M_MAX << 12)
557 #define RT5660_PLL_M_SFT			12
558 #define RT5660_PLL_M_BP				(0x1 << 11)
559 #define RT5660_PLL_M_BP_SFT			11
560 
561 /* Class D Over Current Control (0x8c) */
562 #define RT5660_CLSD_OC_MASK			(0x1 << 9)
563 #define RT5660_CLSD_OC_SFT			9
564 #define RT5660_CLSD_OC_PU			(0x0 << 9)
565 #define RT5660_CLSD_OC_PD			(0x1 << 9)
566 #define RT5660_AUTO_PD_MASK			(0x1 << 8)
567 #define RT5660_AUTO_PD_SFT			8
568 #define RT5660_AUTO_PD_DIS			(0x0 << 8)
569 #define RT5660_AUTO_PD_EN			(0x1 << 8)
570 #define RT5660_CLSD_OC_TH_MASK			(0x3f)
571 #define RT5660_CLSD_OC_TH_SFT			0
572 
573 /* Class D Output Control (0x8d) */
574 #define RT5660_CLSD_RATIO_MASK			(0xf << 12)
575 #define RT5660_CLSD_RATIO_SFT			12
576 
577 /* Lout Amp Control 1 (0x8e) */
578 #define RT5660_LOUT_CO_MASK			(0x1 << 4)
579 #define RT5660_LOUT_CO_SFT			4
580 #define RT5660_LOUT_CO_DIS			(0x0 << 4)
581 #define RT5660_LOUT_CO_EN			(0x1 << 4)
582 #define RT5660_LOUT_CB_MASK			(0x1)
583 #define RT5660_LOUT_CB_SFT			0
584 #define RT5660_LOUT_CB_PD			(0x0)
585 #define RT5660_LOUT_CB_PU			(0x1)
586 
587 /* SPKVDD detection control (0x92) */
588 #define RT5660_SPKVDD_DET_MASK			(0x1 << 15)
589 #define RT5660_SPKVDD_DET_SFT			15
590 #define RT5660_SPKVDD_DET_DIS			(0x0 << 15)
591 #define RT5660_SPKVDD_DET_EN			(0x1 << 15)
592 #define RT5660_SPK_AG_MASK			(0x1 << 14)
593 #define RT5660_SPK_AG_SFT			14
594 #define RT5660_SPK_AG_DIS			(0x0 << 14)
595 #define RT5660_SPK_AG_EN			(0x1 << 14)
596 
597 /* Micbias Control (0x93) */
598 #define RT5660_MIC1_BS_MASK			(0x1 << 15)
599 #define RT5660_MIC1_BS_SFT			15
600 #define RT5660_MIC1_BS_9AV			(0x0 << 15)
601 #define RT5660_MIC1_BS_75AV			(0x1 << 15)
602 #define RT5660_MIC2_BS_MASK			(0x1 << 14)
603 #define RT5660_MIC2_BS_SFT			14
604 #define RT5660_MIC2_BS_9AV			(0x0 << 14)
605 #define RT5660_MIC2_BS_75AV			(0x1 << 14)
606 #define RT5660_MIC1_OVCD_MASK			(0x1 << 11)
607 #define RT5660_MIC1_OVCD_SFT			11
608 #define RT5660_MIC1_OVCD_DIS			(0x0 << 11)
609 #define RT5660_MIC1_OVCD_EN			(0x1 << 11)
610 #define RT5660_MIC1_OVTH_MASK			(0x3 << 9)
611 #define RT5660_MIC1_OVTH_SFT			9
612 #define RT5660_MIC1_OVTH_600UA			(0x0 << 9)
613 #define RT5660_MIC1_OVTH_1500UA			(0x1 << 9)
614 #define RT5660_MIC1_OVTH_2000UA			(0x2 << 9)
615 #define RT5660_MIC2_OVCD_MASK			(0x1 << 8)
616 #define RT5660_MIC2_OVCD_SFT			8
617 #define RT5660_MIC2_OVCD_DIS			(0x0 << 8)
618 #define RT5660_MIC2_OVCD_EN			(0x1 << 8)
619 #define RT5660_MIC2_OVTH_MASK			(0x3 << 6)
620 #define RT5660_MIC2_OVTH_SFT			6
621 #define RT5660_MIC2_OVTH_600UA			(0x0 << 6)
622 #define RT5660_MIC2_OVTH_1500UA			(0x1 << 6)
623 #define RT5660_MIC2_OVTH_2000UA			(0x2 << 6)
624 #define RT5660_PWR_CLK25M_MASK			(0x1 << 4)
625 #define RT5660_PWR_CLK25M_SFT			4
626 #define RT5660_PWR_CLK25M_PD			(0x0 << 4)
627 #define RT5660_PWR_CLK25M_PU			(0x1 << 4)
628 
629 /* EQ Control 1 (0xb0) */
630 #define RT5660_EQ_SRC_MASK			(0x1 << 15)
631 #define RT5660_EQ_SRC_SFT			15
632 #define RT5660_EQ_SRC_DAC			(0x0 << 15)
633 #define RT5660_EQ_SRC_ADC			(0x1 << 15)
634 #define RT5660_EQ_UPD				(0x1 << 14)
635 #define RT5660_EQ_UPD_BIT			14
636 
637 /* Jack Detect Control (0xbb) */
638 #define RT5660_JD_MASK				(0x3 << 14)
639 #define RT5660_JD_SFT				14
640 #define RT5660_JD_DIS				(0x0 << 14)
641 #define RT5660_JD_GPIO1				(0x1 << 14)
642 #define RT5660_JD_GPIO2				(0x2 << 14)
643 #define RT5660_JD_LOUT_MASK			(0x1 << 11)
644 #define RT5660_JD_LOUT_SFT			11
645 #define RT5660_JD_LOUT_DIS			(0x0 << 11)
646 #define RT5660_JD_LOUT_EN			(0x1 << 11)
647 #define RT5660_JD_LOUT_TRG_MASK			(0x1 << 10)
648 #define RT5660_JD_LOUT_TRG_SFT			10
649 #define RT5660_JD_LOUT_TRG_LO			(0x0 << 10)
650 #define RT5660_JD_LOUT_TRG_HI			(0x1 << 10)
651 #define RT5660_JD_SPO_MASK			(0x1 << 9)
652 #define RT5660_JD_SPO_SFT			9
653 #define RT5660_JD_SPO_DIS			(0x0 << 9)
654 #define RT5660_JD_SPO_EN			(0x1 << 9)
655 #define RT5660_JD_SPO_TRG_MASK			(0x1 << 8)
656 #define RT5660_JD_SPO_TRG_SFT			8
657 #define RT5660_JD_SPO_TRG_LO			(0x0 << 8)
658 #define RT5660_JD_SPO_TRG_HI			(0x1 << 8)
659 
660 /* IRQ Control 1 (0xbd) */
661 #define RT5660_IRQ_JD_MASK			(0x1 << 15)
662 #define RT5660_IRQ_JD_SFT			15
663 #define RT5660_IRQ_JD_BP			(0x0 << 15)
664 #define RT5660_IRQ_JD_NOR			(0x1 << 15)
665 #define RT5660_IRQ_OT_MASK			(0x1 << 14)
666 #define RT5660_IRQ_OT_SFT			14
667 #define RT5660_IRQ_OT_BP			(0x0 << 14)
668 #define RT5660_IRQ_OT_NOR			(0x1 << 14)
669 #define RT5660_JD_STKY_MASK			(0x1 << 13)
670 #define RT5660_JD_STKY_SFT			13
671 #define RT5660_JD_STKY_DIS			(0x0 << 13)
672 #define RT5660_JD_STKY_EN			(0x1 << 13)
673 #define RT5660_OT_STKY_MASK			(0x1 << 12)
674 #define RT5660_OT_STKY_SFT			12
675 #define RT5660_OT_STKY_DIS			(0x0 << 12)
676 #define RT5660_OT_STKY_EN			(0x1 << 12)
677 #define RT5660_JD_P_MASK			(0x1 << 11)
678 #define RT5660_JD_P_SFT				11
679 #define RT5660_JD_P_NOR				(0x0 << 11)
680 #define RT5660_JD_P_INV				(0x1 << 11)
681 #define RT5660_OT_P_MASK			(0x1 << 10)
682 #define RT5660_OT_P_SFT				10
683 #define RT5660_OT_P_NOR				(0x0 << 10)
684 #define RT5660_OT_P_INV				(0x1 << 10)
685 
686 /* IRQ Control 2 (0xbe) */
687 #define RT5660_IRQ_MB1_OC_MASK			(0x1 << 15)
688 #define RT5660_IRQ_MB1_OC_SFT			15
689 #define RT5660_IRQ_MB1_OC_BP			(0x0 << 15)
690 #define RT5660_IRQ_MB1_OC_NOR			(0x1 << 15)
691 #define RT5660_IRQ_MB2_OC_MASK			(0x1 << 14)
692 #define RT5660_IRQ_MB2_OC_SFT			14
693 #define RT5660_IRQ_MB2_OC_BP			(0x0 << 14)
694 #define RT5660_IRQ_MB2_OC_NOR			(0x1 << 14)
695 #define RT5660_MB1_OC_STKY_MASK			(0x1 << 11)
696 #define RT5660_MB1_OC_STKY_SFT			11
697 #define RT5660_MB1_OC_STKY_DIS			(0x0 << 11)
698 #define RT5660_MB1_OC_STKY_EN			(0x1 << 11)
699 #define RT5660_MB2_OC_STKY_MASK			(0x1 << 10)
700 #define RT5660_MB2_OC_STKY_SFT			10
701 #define RT5660_MB2_OC_STKY_DIS			(0x0 << 10)
702 #define RT5660_MB2_OC_STKY_EN			(0x1 << 10)
703 #define RT5660_MB1_OC_P_MASK			(0x1 << 7)
704 #define RT5660_MB1_OC_P_SFT			7
705 #define RT5660_MB1_OC_P_NOR			(0x0 << 7)
706 #define RT5660_MB1_OC_P_INV			(0x1 << 7)
707 #define RT5660_MB2_OC_P_MASK			(0x1 << 6)
708 #define RT5660_MB2_OC_P_SFT			6
709 #define RT5660_MB2_OC_P_NOR			(0x0 << 6)
710 #define RT5660_MB2_OC_P_INV			(0x1 << 6)
711 #define RT5660_MB1_OC_CLR			(0x1 << 3)
712 #define RT5660_MB1_OC_CLR_SFT			3
713 #define RT5660_MB2_OC_CLR			(0x1 << 2)
714 #define RT5660_MB2_OC_CLR_SFT			2
715 
716 /* GPIO Control 1 (0xc0) */
717 #define RT5660_GP2_PIN_MASK			(0x1 << 14)
718 #define RT5660_GP2_PIN_SFT			14
719 #define RT5660_GP2_PIN_GPIO2			(0x0 << 14)
720 #define RT5660_GP2_PIN_DMIC1_SDA		(0x1 << 14)
721 #define RT5660_GP1_PIN_MASK			(0x3 << 12)
722 #define RT5660_GP1_PIN_SFT			12
723 #define RT5660_GP1_PIN_GPIO1			(0x0 << 12)
724 #define RT5660_GP1_PIN_DMIC1_SCL		(0x1 << 12)
725 #define RT5660_GP1_PIN_IRQ			(0x2 << 12)
726 #define RT5660_GPIO_M_MASK			(0x1 << 9)
727 #define RT5660_GPIO_M_SFT			9
728 #define RT5660_GPIO_M_FLT			(0x0 << 9)
729 #define RT5660_GPIO_M_PH			(0x1 << 9)
730 
731 /* GPIO Control 3 (0xc2) */
732 #define RT5660_GP2_PF_MASK			(0x1 << 5)
733 #define RT5660_GP2_PF_SFT			5
734 #define RT5660_GP2_PF_IN			(0x0 << 5)
735 #define RT5660_GP2_PF_OUT			(0x1 << 5)
736 #define RT5660_GP2_OUT_MASK			(0x1 << 4)
737 #define RT5660_GP2_OUT_SFT			4
738 #define RT5660_GP2_OUT_LO			(0x0 << 4)
739 #define RT5660_GP2_OUT_HI			(0x1 << 4)
740 #define RT5660_GP2_P_MASK			(0x1 << 3)
741 #define RT5660_GP2_P_SFT			3
742 #define RT5660_GP2_P_NOR			(0x0 << 3)
743 #define RT5660_GP2_P_INV			(0x1 << 3)
744 #define RT5660_GP1_PF_MASK			(0x1 << 2)
745 #define RT5660_GP1_PF_SFT			2
746 #define RT5660_GP1_PF_IN			(0x0 << 2)
747 #define RT5660_GP1_PF_OUT			(0x1 << 2)
748 #define RT5660_GP1_OUT_MASK			(0x1 << 1)
749 #define RT5660_GP1_OUT_SFT			1
750 #define RT5660_GP1_OUT_LO			(0x0 << 1)
751 #define RT5660_GP1_OUT_HI			(0x1 << 1)
752 #define RT5660_GP1_P_MASK			(0x1)
753 #define RT5660_GP1_P_SFT			0
754 #define RT5660_GP1_P_NOR			(0x0)
755 #define RT5660_GP1_P_INV			(0x1)
756 
757 /* Soft volume and zero cross control 1 (0xd9) */
758 #define RT5660_SV_MASK				(0x1 << 15)
759 #define RT5660_SV_SFT				15
760 #define RT5660_SV_DIS				(0x0 << 15)
761 #define RT5660_SV_EN				(0x1 << 15)
762 #define RT5660_SPO_SV_MASK			(0x1 << 14)
763 #define RT5660_SPO_SV_SFT			14
764 #define RT5660_SPO_SV_DIS			(0x0 << 14)
765 #define RT5660_SPO_SV_EN			(0x1 << 14)
766 #define RT5660_OUT_SV_MASK			(0x1 << 12)
767 #define RT5660_OUT_SV_SFT			12
768 #define RT5660_OUT_SV_DIS			(0x0 << 12)
769 #define RT5660_OUT_SV_EN			(0x1 << 12)
770 #define RT5660_ZCD_DIG_MASK			(0x1 << 11)
771 #define RT5660_ZCD_DIG_SFT			11
772 #define RT5660_ZCD_DIG_DIS			(0x0 << 11)
773 #define RT5660_ZCD_DIG_EN			(0x1 << 11)
774 #define RT5660_ZCD_MASK				(0x1 << 10)
775 #define RT5660_ZCD_SFT				10
776 #define RT5660_ZCD_PD				(0x0 << 10)
777 #define RT5660_ZCD_PU				(0x1 << 10)
778 #define RT5660_SV_DLY_MASK			(0xf)
779 #define RT5660_SV_DLY_SFT			0
780 
781 /* Soft volume and zero cross control 2 (0xda) */
782 #define RT5660_ZCD_SPO_MASK			(0x1 << 15)
783 #define RT5660_ZCD_SPO_SFT			15
784 #define RT5660_ZCD_SPO_DIS			(0x0 << 15)
785 #define RT5660_ZCD_SPO_EN			(0x1 << 15)
786 #define RT5660_ZCD_OMR_MASK			(0x1 << 8)
787 #define RT5660_ZCD_OMR_SFT			8
788 #define RT5660_ZCD_OMR_DIS			(0x0 << 8)
789 #define RT5660_ZCD_OMR_EN			(0x1 << 8)
790 #define RT5660_ZCD_OML_MASK			(0x1 << 7)
791 #define RT5660_ZCD_OML_SFT			7
792 #define RT5660_ZCD_OML_DIS			(0x0 << 7)
793 #define RT5660_ZCD_OML_EN			(0x1 << 7)
794 #define RT5660_ZCD_SPM_MASK			(0x1 << 6)
795 #define RT5660_ZCD_SPM_SFT			6
796 #define RT5660_ZCD_SPM_DIS			(0x0 << 6)
797 #define RT5660_ZCD_SPM_EN			(0x1 << 6)
798 #define RT5660_ZCD_RMR_MASK			(0x1 << 5)
799 #define RT5660_ZCD_RMR_SFT			5
800 #define RT5660_ZCD_RMR_DIS			(0x0 << 5)
801 #define RT5660_ZCD_RMR_EN			(0x1 << 5)
802 #define RT5660_ZCD_RML_MASK			(0x1 << 4)
803 #define RT5660_ZCD_RML_SFT			4
804 #define RT5660_ZCD_RML_DIS			(0x0 << 4)
805 #define RT5660_ZCD_RML_EN			(0x1 << 4)
806 
807 /* General Control 1 (0xfa) */
808 #define RT5660_PWR_VREF_HP			(0x1 << 11)
809 #define RT5660_PWR_VREF_HP_SFT			11
810 #define RT5660_AUTO_DIS_AMP			(0x1 << 6)
811 #define RT5660_MCLK_DET				(0x1 << 5)
812 #define RT5660_POW_CLKDET			(0x1 << 1)
813 #define RT5660_DIG_GATE_CTRL			(0x1)
814 #define RT5660_DIG_GATE_CTRL_SFT		0
815 
816 /* System Clock Source */
817 #define RT5660_SCLK_S_MCLK			0
818 #define RT5660_SCLK_S_PLL1			1
819 #define RT5660_SCLK_S_RCCLK			2
820 
821 /* PLL1 Source */
822 #define RT5660_PLL1_S_MCLK			0
823 #define RT5660_PLL1_S_BCLK			1
824 
825 enum {
826 	RT5660_AIF1,
827 	RT5660_AIFS,
828 };
829 
830 struct rt5660_priv {
831 	struct snd_soc_component *component;
832 	struct rt5660_platform_data pdata;
833 	struct regmap *regmap;
834 	struct clk *mclk;
835 
836 	int sysclk;
837 	int sysclk_src;
838 	int lrck[RT5660_AIFS];
839 	int bclk[RT5660_AIFS];
840 	int master[RT5660_AIFS];
841 
842 	int pll_src;
843 	int pll_in;
844 	int pll_out;
845 };
846 
847 #endif
848