1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MTMIPS SoCs Clock Driver
4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/clk-provider.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
13 #include <linux/slab.h>
14
15 /* Configuration registers */
16 #define SYSC_REG_SYSTEM_CONFIG 0x10
17 #define SYSC_REG_CLKCFG0 0x2c
18 #define SYSC_REG_RESET_CTRL 0x34
19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c
20 #define SYSC_REG_CPLL_CONFIG0 0x54
21 #define SYSC_REG_CPLL_CONFIG1 0x58
22
23 /* RT2880 SoC */
24 #define RT2880_CONFIG_CPUCLK_SHIFT 20
25 #define RT2880_CONFIG_CPUCLK_MASK 0x3
26 #define RT2880_CONFIG_CPUCLK_250 0x0
27 #define RT2880_CONFIG_CPUCLK_266 0x1
28 #define RT2880_CONFIG_CPUCLK_280 0x2
29 #define RT2880_CONFIG_CPUCLK_300 0x3
30
31 /* RT305X SoC */
32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18
33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1
34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0
35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1
36
37 /* RT3352 SoC */
38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8
39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1
40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0
41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
42
43 /* RT3383 SoC */
44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8
46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3
47 #define RT3883_SYSCFG0_CPUCLK_250 0x0
48 #define RT3883_SYSCFG0_CPUCLK_384 0x1
49 #define RT3883_SYSCFG0_CPUCLK_480 0x2
50 #define RT3883_SYSCFG0_CPUCLK_500 0x3
51
52 /* RT5350 SoC */
53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20)
54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8
55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3
56 #define RT5350_SYSCFG0_CPUCLK_360 0x0
57 #define RT5350_SYSCFG0_CPUCLK_320 0x2
58 #define RT5350_SYSCFG0_CPUCLK_300 0x3
59
60 /* MT7620 and MT76x8 SoCs */
61 #define MT7620_XTAL_FREQ_SEL BIT(6)
62 #define CPLL_CFG0_SW_CFG BIT(31)
63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
65 #define CPLL_CFG0_LC_CURFCK BIT(15)
66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
69 #define CPLL_CFG1_CPU_AUX1 BIT(25)
70 #define CPLL_CFG1_CPU_AUX0 BIT(24)
71 #define CLKCFG0_PERI_CLK_SEL BIT(4)
72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
87
88 /* clock scaling */
89 #define CLKCFG_FDIV_MASK 0x1f00
90 #define CLKCFG_FDIV_USB_VAL 0x0300
91 #define CLKCFG_FFRAC_MASK 0x001f
92 #define CLKCFG_FFRAC_USB_VAL 0x0003
93
94 struct mtmips_clk;
95 struct mtmips_clk_fixed;
96 struct mtmips_clk_factor;
97
98 struct mtmips_clk_data {
99 struct mtmips_clk *clk_base;
100 size_t num_clk_base;
101 struct mtmips_clk_fixed *clk_fixed;
102 size_t num_clk_fixed;
103 struct mtmips_clk_factor *clk_factor;
104 size_t num_clk_factor;
105 struct mtmips_clk *clk_periph;
106 size_t num_clk_periph;
107 };
108
109 struct mtmips_clk_priv {
110 struct regmap *sysc;
111 const struct mtmips_clk_data *data;
112 };
113
114 struct mtmips_clk {
115 struct clk_hw hw;
116 struct mtmips_clk_priv *priv;
117 };
118
119 struct mtmips_clk_fixed {
120 const char *name;
121 const char *parent;
122 unsigned long rate;
123 struct clk_hw *hw;
124 };
125
126 struct mtmips_clk_factor {
127 const char *name;
128 const char *parent;
129 int mult;
130 int div;
131 unsigned long flags;
132 struct clk_hw *hw;
133 };
134
mtmips_pherip_clk_rate(struct clk_hw * hw,unsigned long parent_rate)135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
136 unsigned long parent_rate)
137 {
138 return parent_rate;
139 }
140
141 static const struct clk_ops mtmips_periph_clk_ops = {
142 .recalc_rate = mtmips_pherip_clk_rate,
143 };
144
145 #define CLK_PERIPH(_name, _parent) { \
146 .init = &(const struct clk_init_data) { \
147 .name = _name, \
148 .ops = &mtmips_periph_clk_ops, \
149 .parent_data = &(const struct clk_parent_data) {\
150 .name = _parent, \
151 .fw_name = _parent \
152 }, \
153 .num_parents = 1, \
154 /* \
155 * There are drivers for these SoCs that are \
156 * older than clock driver and are not prepared \
157 * for the clock. We don't want the kernel to \
158 * disable anything so we add CLK_IS_CRITICAL \
159 * flag here. \
160 */ \
161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \
162 }, \
163 }
164
165 static struct mtmips_clk rt2880_pherip_clks[] = {
166 { CLK_PERIPH("300100.timer", "bus") },
167 { CLK_PERIPH("300120.watchdog", "bus") },
168 { CLK_PERIPH("300500.uart", "bus") },
169 { CLK_PERIPH("300900.i2c", "bus") },
170 { CLK_PERIPH("300c00.uartlite", "bus") },
171 { CLK_PERIPH("400000.ethernet", "bus") },
172 { CLK_PERIPH("480000.wmac", "xtal") }
173 };
174
175 static struct mtmips_clk rt305x_pherip_clks[] = {
176 { CLK_PERIPH("10000100.timer", "bus") },
177 { CLK_PERIPH("10000120.watchdog", "bus") },
178 { CLK_PERIPH("10000500.uart", "bus") },
179 { CLK_PERIPH("10000900.i2c", "bus") },
180 { CLK_PERIPH("10000a00.i2s", "bus") },
181 { CLK_PERIPH("10000b00.spi", "bus") },
182 { CLK_PERIPH("10000b40.spi", "bus") },
183 { CLK_PERIPH("10000c00.uartlite", "bus") },
184 { CLK_PERIPH("10100000.ethernet", "bus") },
185 { CLK_PERIPH("10180000.wmac", "xtal") }
186 };
187
188 static struct mtmips_clk rt5350_pherip_clks[] = {
189 { CLK_PERIPH("10000100.timer", "bus") },
190 { CLK_PERIPH("10000120.watchdog", "bus") },
191 { CLK_PERIPH("10000500.uart", "periph") },
192 { CLK_PERIPH("10000900.i2c", "periph") },
193 { CLK_PERIPH("10000a00.i2s", "periph") },
194 { CLK_PERIPH("10000b00.spi", "bus") },
195 { CLK_PERIPH("10000b40.spi", "bus") },
196 { CLK_PERIPH("10000c00.uartlite", "periph") },
197 { CLK_PERIPH("10100000.ethernet", "bus") },
198 { CLK_PERIPH("10180000.wmac", "xtal") }
199 };
200
201 static struct mtmips_clk mt7620_pherip_clks[] = {
202 { CLK_PERIPH("10000100.timer", "periph") },
203 { CLK_PERIPH("10000120.watchdog", "periph") },
204 { CLK_PERIPH("10000500.uart", "periph") },
205 { CLK_PERIPH("10000900.i2c", "periph") },
206 { CLK_PERIPH("10000a00.i2s", "periph") },
207 { CLK_PERIPH("10000b00.spi", "bus") },
208 { CLK_PERIPH("10000b40.spi", "bus") },
209 { CLK_PERIPH("10000c00.uartlite", "periph") },
210 { CLK_PERIPH("10130000.mmc", "sdhc") },
211 { CLK_PERIPH("10180000.wmac", "xtal") }
212 };
213
214 static struct mtmips_clk mt76x8_pherip_clks[] = {
215 { CLK_PERIPH("10000100.timer", "periph") },
216 { CLK_PERIPH("10000120.watchdog", "periph") },
217 { CLK_PERIPH("10000900.i2c", "periph") },
218 { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
219 { CLK_PERIPH("10000b00.spi", "bus") },
220 { CLK_PERIPH("10000b40.spi", "bus") },
221 { CLK_PERIPH("10000c00.uart0", "periph") },
222 { CLK_PERIPH("10000d00.uart1", "periph") },
223 { CLK_PERIPH("10000e00.uart2", "periph") },
224 { CLK_PERIPH("10130000.mmc", "sdhc") },
225 { CLK_PERIPH("10300000.wmac", "xtal") }
226 };
227
mtmips_register_pherip_clocks(struct device_node * np,struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)228 static int mtmips_register_pherip_clocks(struct device_node *np,
229 struct clk_hw_onecell_data *clk_data,
230 struct mtmips_clk_priv *priv)
231 {
232 struct clk_hw **hws = clk_data->hws;
233 struct mtmips_clk *sclk;
234 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
235 priv->data->num_clk_factor;
236 int ret, i;
237
238 for (i = 0; i < priv->data->num_clk_periph; i++) {
239 int idx = idx_start + i;
240
241 sclk = &priv->data->clk_periph[i];
242 ret = of_clk_hw_register(np, &sclk->hw);
243 if (ret) {
244 pr_err("Couldn't register peripheral clock %d\n", idx);
245 goto err_clk_unreg;
246 }
247
248 hws[idx] = &sclk->hw;
249 }
250
251 return 0;
252
253 err_clk_unreg:
254 while (--i >= 0) {
255 sclk = &priv->data->clk_periph[i];
256 clk_hw_unregister(&sclk->hw);
257 }
258 return ret;
259 }
260
261 #define CLK_FIXED(_name, _parent, _rate) \
262 { \
263 .name = _name, \
264 .parent = _parent, \
265 .rate = _rate \
266 }
267
268 static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
269 CLK_FIXED("xtal", NULL, 40000000),
270 CLK_FIXED("periph", "xtal", 40000000)
271 };
272
273 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
274 CLK_FIXED("periph", "xtal", 40000000)
275 };
276
277 static struct mtmips_clk_fixed mt7620_fixed_clocks[] = {
278 CLK_FIXED("bbppll", "xtal", 480000000)
279 };
280
281 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
282 CLK_FIXED("bbppll", "xtal", 480000000),
283 CLK_FIXED("pcmi2s", "bbppll", 480000000),
284 CLK_FIXED("periph", "xtal", 40000000)
285 };
286
mtmips_register_fixed_clocks(struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)287 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
288 struct mtmips_clk_priv *priv)
289 {
290 struct clk_hw **hws = clk_data->hws;
291 struct mtmips_clk_fixed *sclk;
292 size_t idx_start = priv->data->num_clk_base;
293 int ret, i;
294
295 for (i = 0; i < priv->data->num_clk_fixed; i++) {
296 int idx = idx_start + i;
297
298 sclk = &priv->data->clk_fixed[i];
299 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
300 sclk->parent, 0,
301 sclk->rate);
302 if (IS_ERR(sclk->hw)) {
303 ret = PTR_ERR(sclk->hw);
304 pr_err("Couldn't register fixed clock %d\n", idx);
305 goto err_clk_unreg;
306 }
307
308 hws[idx] = sclk->hw;
309 }
310
311 return 0;
312
313 err_clk_unreg:
314 while (--i >= 0) {
315 sclk = &priv->data->clk_fixed[i];
316 clk_hw_unregister_fixed_rate(sclk->hw);
317 }
318 return ret;
319 }
320
321 #define CLK_FACTOR(_name, _parent, _mult, _div) \
322 { \
323 .name = _name, \
324 .parent = _parent, \
325 .mult = _mult, \
326 .div = _div, \
327 .flags = CLK_SET_RATE_PARENT \
328 }
329
330 static struct mtmips_clk_factor rt2880_factor_clocks[] = {
331 CLK_FACTOR("bus", "cpu", 1, 2)
332 };
333
334 static struct mtmips_clk_factor rt305x_factor_clocks[] = {
335 CLK_FACTOR("bus", "cpu", 1, 3)
336 };
337
338 static struct mtmips_clk_factor mt7620_factor_clocks[] = {
339 CLK_FACTOR("sdhc", "bbppll", 1, 10)
340 };
341
342 static struct mtmips_clk_factor mt76x8_factor_clocks[] = {
343 CLK_FACTOR("bus", "cpu", 1, 3),
344 CLK_FACTOR("sdhc", "bbppll", 1, 10)
345 };
346
mtmips_register_factor_clocks(struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)347 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
348 struct mtmips_clk_priv *priv)
349 {
350 struct clk_hw **hws = clk_data->hws;
351 struct mtmips_clk_factor *sclk;
352 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
353 int ret, i;
354
355 for (i = 0; i < priv->data->num_clk_factor; i++) {
356 int idx = idx_start + i;
357
358 sclk = &priv->data->clk_factor[i];
359 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
360 sclk->parent, sclk->flags,
361 sclk->mult, sclk->div);
362 if (IS_ERR(sclk->hw)) {
363 ret = PTR_ERR(sclk->hw);
364 pr_err("Couldn't register factor clock %d\n", idx);
365 goto err_clk_unreg;
366 }
367
368 hws[idx] = sclk->hw;
369 }
370
371 return 0;
372
373 err_clk_unreg:
374 while (--i >= 0) {
375 sclk = &priv->data->clk_factor[i];
376 clk_hw_unregister_fixed_factor(sclk->hw);
377 }
378 return ret;
379 }
380
to_mtmips_clk(struct clk_hw * hw)381 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
382 {
383 return container_of(hw, struct mtmips_clk, hw);
384 }
385
rt2880_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)386 static unsigned long rt2880_xtal_recalc_rate(struct clk_hw *hw,
387 unsigned long parent_rate)
388 {
389 return 40000000;
390 }
391
rt5350_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)392 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
393 unsigned long parent_rate)
394 {
395 struct mtmips_clk *clk = to_mtmips_clk(hw);
396 struct regmap *sysc = clk->priv->sysc;
397 u32 val;
398
399 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
400 if (!(val & RT5350_CLKCFG0_XTAL_SEL))
401 return 20000000;
402
403 return 40000000;
404 }
405
rt5350_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)406 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
407 unsigned long xtal_clk)
408 {
409 struct mtmips_clk *clk = to_mtmips_clk(hw);
410 struct regmap *sysc = clk->priv->sysc;
411 u32 t;
412
413 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
414 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
415
416 switch (t) {
417 case RT5350_SYSCFG0_CPUCLK_360:
418 return 360000000;
419 case RT5350_SYSCFG0_CPUCLK_320:
420 return 320000000;
421 case RT5350_SYSCFG0_CPUCLK_300:
422 return 300000000;
423 default:
424 BUG();
425 }
426 }
427
rt5350_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)428 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
429 unsigned long parent_rate)
430 {
431 if (parent_rate == 320000000)
432 return parent_rate / 4;
433
434 return parent_rate / 3;
435 }
436
rt3352_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)437 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
438 unsigned long xtal_clk)
439 {
440 struct mtmips_clk *clk = to_mtmips_clk(hw);
441 struct regmap *sysc = clk->priv->sysc;
442 u32 t;
443
444 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
445 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
446
447 switch (t) {
448 case RT3352_SYSCFG0_CPUCLK_LOW:
449 return 384000000;
450 case RT3352_SYSCFG0_CPUCLK_HIGH:
451 return 400000000;
452 default:
453 BUG();
454 }
455 }
456
rt305x_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)457 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
458 unsigned long xtal_clk)
459 {
460 struct mtmips_clk *clk = to_mtmips_clk(hw);
461 struct regmap *sysc = clk->priv->sysc;
462 u32 t;
463
464 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
465 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
466
467 switch (t) {
468 case RT305X_SYSCFG_CPUCLK_LOW:
469 return 320000000;
470 case RT305X_SYSCFG_CPUCLK_HIGH:
471 return 384000000;
472 default:
473 BUG();
474 }
475 }
476
rt3883_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)477 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
478 unsigned long xtal_clk)
479 {
480 struct mtmips_clk *clk = to_mtmips_clk(hw);
481 struct regmap *sysc = clk->priv->sysc;
482 u32 t;
483
484 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
485 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
486
487 switch (t) {
488 case RT3883_SYSCFG0_CPUCLK_250:
489 return 250000000;
490 case RT3883_SYSCFG0_CPUCLK_384:
491 return 384000000;
492 case RT3883_SYSCFG0_CPUCLK_480:
493 return 480000000;
494 case RT3883_SYSCFG0_CPUCLK_500:
495 return 500000000;
496 default:
497 BUG();
498 }
499 }
500
rt3883_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)501 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
502 unsigned long parent_rate)
503 {
504 struct mtmips_clk *clk = to_mtmips_clk(hw);
505 struct regmap *sysc = clk->priv->sysc;
506 u32 ddr2;
507 u32 t;
508
509 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
510 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
511
512 switch (parent_rate) {
513 case 250000000:
514 return (ddr2) ? 125000000 : 83000000;
515 case 384000000:
516 return (ddr2) ? 128000000 : 96000000;
517 case 480000000:
518 return (ddr2) ? 160000000 : 120000000;
519 case 500000000:
520 return (ddr2) ? 166000000 : 125000000;
521 default:
522 WARN_ON_ONCE(parent_rate == 0);
523 return parent_rate / 4;
524 }
525 }
526
rt2880_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)527 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
528 unsigned long xtal_clk)
529 {
530 struct mtmips_clk *clk = to_mtmips_clk(hw);
531 struct regmap *sysc = clk->priv->sysc;
532 u32 t;
533
534 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
535 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
536
537 switch (t) {
538 case RT2880_CONFIG_CPUCLK_250:
539 return 250000000;
540 case RT2880_CONFIG_CPUCLK_266:
541 return 266000000;
542 case RT2880_CONFIG_CPUCLK_280:
543 return 280000000;
544 case RT2880_CONFIG_CPUCLK_300:
545 return 300000000;
546 default:
547 BUG();
548 }
549 }
550
mt7620_calc_rate(u32 ref_rate,u32 mul,u32 div)551 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
552 {
553 u64 t;
554
555 t = ref_rate;
556 t *= mul;
557 t = div_u64(t, div);
558
559 return t;
560 }
561
mt7620_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)562 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
563 unsigned long parent_rate)
564 {
565 static const u32 clk_divider[] = { 2, 3, 4, 8 };
566 struct mtmips_clk *clk = to_mtmips_clk(hw);
567 struct regmap *sysc = clk->priv->sysc;
568 unsigned long cpu_pll;
569 u32 t;
570 u32 mul;
571 u32 div;
572
573 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
574 if (t & CPLL_CFG0_BYPASS_REF_CLK) {
575 cpu_pll = parent_rate;
576 } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
577 cpu_pll = 600000000;
578 } else {
579 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
580 CPLL_CFG0_PLL_MULT_RATIO_MASK;
581 mul += 24;
582 if (t & CPLL_CFG0_LC_CURFCK)
583 mul *= 2;
584
585 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
586 CPLL_CFG0_PLL_DIV_RATIO_MASK;
587
588 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
589
590 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
591 }
592
593 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
594 if (t & CPLL_CFG1_CPU_AUX1)
595 return parent_rate;
596
597 if (t & CPLL_CFG1_CPU_AUX0)
598 return 480000000;
599
600 return cpu_pll;
601 }
602
mt7620_cpu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)603 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
604 unsigned long parent_rate)
605 {
606 struct mtmips_clk *clk = to_mtmips_clk(hw);
607 struct regmap *sysc = clk->priv->sysc;
608 u32 t;
609 u32 mul;
610 u32 div;
611
612 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
613 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
614 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
615 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
616
617 return mt7620_calc_rate(parent_rate, mul, div);
618 }
619
mt7620_bus_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)620 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
621 unsigned long parent_rate)
622 {
623 static const u32 ocp_dividers[16] = {
624 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
625 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
626 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
627 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
628 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
629 };
630 struct mtmips_clk *clk = to_mtmips_clk(hw);
631 struct regmap *sysc = clk->priv->sysc;
632 u32 t;
633 u32 ocp_ratio;
634 u32 div;
635
636 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
637 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
638 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
639
640 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
641 return parent_rate;
642
643 div = ocp_dividers[ocp_ratio];
644
645 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
646 return parent_rate;
647
648 return parent_rate / div;
649 }
650
mt7620_periph_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)651 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
652 unsigned long parent_rate)
653 {
654 struct mtmips_clk *clk = to_mtmips_clk(hw);
655 struct regmap *sysc = clk->priv->sysc;
656 u32 t;
657
658 regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
659 if (t & CLKCFG0_PERI_CLK_SEL)
660 return parent_rate;
661
662 return 40000000;
663 }
664
mt76x8_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)665 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
666 unsigned long parent_rate)
667 {
668 struct mtmips_clk *clk = to_mtmips_clk(hw);
669 struct regmap *sysc = clk->priv->sysc;
670 u32 t;
671
672 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
673 if (t & MT7620_XTAL_FREQ_SEL)
674 return 40000000;
675
676 return 20000000;
677 }
678
mt76x8_cpu_recalc_rate(struct clk_hw * hw,unsigned long xtal_clk)679 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
680 unsigned long xtal_clk)
681 {
682 if (xtal_clk == 40000000)
683 return 580000000;
684
685 return 575000000;
686 }
687
688 #define CLK_BASE(_name, _parent, _recalc) { \
689 .init = &(const struct clk_init_data) { \
690 .name = _name, \
691 .ops = &(const struct clk_ops) { \
692 .recalc_rate = _recalc, \
693 }, \
694 .parent_data = &(const struct clk_parent_data) { \
695 .name = _parent, \
696 .fw_name = _parent \
697 }, \
698 .num_parents = _parent ? 1 : 0 \
699 }, \
700 }
701
702 static struct mtmips_clk rt2880_clks_base[] = {
703 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
704 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
705 };
706
707 static struct mtmips_clk rt305x_clks_base[] = {
708 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
709 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
710 };
711
712 static struct mtmips_clk rt3352_clks_base[] = {
713 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
714 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
715 };
716
717 static struct mtmips_clk rt3883_clks_base[] = {
718 { CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
719 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
720 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
721 };
722
723 static struct mtmips_clk rt5350_clks_base[] = {
724 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
725 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
726 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
727 };
728
729 static struct mtmips_clk mt7620_clks_base[] = {
730 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
731 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
732 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
733 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
734 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
735 };
736
737 static struct mtmips_clk mt76x8_clks_base[] = {
738 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
739 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
740 };
741
mtmips_register_clocks(struct device_node * np,struct clk_hw_onecell_data * clk_data,struct mtmips_clk_priv * priv)742 static int mtmips_register_clocks(struct device_node *np,
743 struct clk_hw_onecell_data *clk_data,
744 struct mtmips_clk_priv *priv)
745 {
746 struct clk_hw **hws = clk_data->hws;
747 struct mtmips_clk *sclk;
748 int ret, i;
749
750 for (i = 0; i < priv->data->num_clk_base; i++) {
751 sclk = &priv->data->clk_base[i];
752 sclk->priv = priv;
753 ret = of_clk_hw_register(np, &sclk->hw);
754 if (ret) {
755 pr_err("Couldn't register top clock %i\n", i);
756 goto err_clk_unreg;
757 }
758
759 hws[i] = &sclk->hw;
760 }
761
762 return 0;
763
764 err_clk_unreg:
765 while (--i >= 0) {
766 sclk = &priv->data->clk_base[i];
767 clk_hw_unregister(&sclk->hw);
768 }
769 return ret;
770 }
771
772 static const struct mtmips_clk_data rt2880_clk_data = {
773 .clk_base = rt2880_clks_base,
774 .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
775 .clk_fixed = NULL,
776 .num_clk_fixed = 0,
777 .clk_factor = rt2880_factor_clocks,
778 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
779 .clk_periph = rt2880_pherip_clks,
780 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
781 };
782
783 static const struct mtmips_clk_data rt305x_clk_data = {
784 .clk_base = rt305x_clks_base,
785 .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
786 .clk_fixed = NULL,
787 .num_clk_fixed = 0,
788 .clk_factor = rt305x_factor_clocks,
789 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
790 .clk_periph = rt305x_pherip_clks,
791 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
792 };
793
794 static const struct mtmips_clk_data rt3352_clk_data = {
795 .clk_base = rt3352_clks_base,
796 .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
797 .clk_fixed = rt3352_fixed_clocks,
798 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
799 .clk_factor = rt305x_factor_clocks,
800 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
801 .clk_periph = rt5350_pherip_clks,
802 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
803 };
804
805 static const struct mtmips_clk_data rt3883_clk_data = {
806 .clk_base = rt3883_clks_base,
807 .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
808 .clk_fixed = rt3883_fixed_clocks,
809 .num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
810 .clk_factor = NULL,
811 .num_clk_factor = 0,
812 .clk_periph = rt5350_pherip_clks,
813 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
814 };
815
816 static const struct mtmips_clk_data rt5350_clk_data = {
817 .clk_base = rt5350_clks_base,
818 .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
819 .clk_fixed = rt3352_fixed_clocks,
820 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
821 .clk_factor = NULL,
822 .num_clk_factor = 0,
823 .clk_periph = rt5350_pherip_clks,
824 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
825 };
826
827 static const struct mtmips_clk_data mt7620_clk_data = {
828 .clk_base = mt7620_clks_base,
829 .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
830 .clk_fixed = mt7620_fixed_clocks,
831 .num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks),
832 .clk_factor = mt7620_factor_clocks,
833 .num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks),
834 .clk_periph = mt7620_pherip_clks,
835 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
836 };
837
838 static const struct mtmips_clk_data mt76x8_clk_data = {
839 .clk_base = mt76x8_clks_base,
840 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
841 .clk_fixed = mt76x8_fixed_clocks,
842 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
843 .clk_factor = mt76x8_factor_clocks,
844 .num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks),
845 .clk_periph = mt76x8_pherip_clks,
846 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
847 };
848
849 static const struct of_device_id mtmips_of_match[] = {
850 {
851 .compatible = "ralink,rt2880-reset",
852 .data = NULL,
853 },
854 {
855 .compatible = "ralink,rt2880-sysc",
856 .data = &rt2880_clk_data,
857 },
858 {
859 .compatible = "ralink,rt3050-sysc",
860 .data = &rt305x_clk_data,
861 },
862 {
863 .compatible = "ralink,rt3052-sysc",
864 .data = &rt305x_clk_data,
865 },
866 {
867 .compatible = "ralink,rt3352-sysc",
868 .data = &rt3352_clk_data,
869 },
870 {
871 .compatible = "ralink,rt3883-sysc",
872 .data = &rt3883_clk_data,
873 },
874 {
875 .compatible = "ralink,rt5350-sysc",
876 .data = &rt5350_clk_data,
877 },
878 {
879 .compatible = "ralink,mt7620-sysc",
880 .data = &mt7620_clk_data,
881 },
882 {
883 .compatible = "ralink,mt7628-sysc",
884 .data = &mt76x8_clk_data,
885 },
886 {
887 .compatible = "ralink,mt7688-sysc",
888 .data = &mt76x8_clk_data,
889 },
890 {}
891 };
892
mtmips_clk_regs_init(struct device_node * node,struct mtmips_clk_priv * priv)893 static void __init mtmips_clk_regs_init(struct device_node *node,
894 struct mtmips_clk_priv *priv)
895 {
896 u32 t;
897
898 if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
899 return;
900
901 /*
902 * When the CPU goes into sleep mode, the BUS
903 * clock will be too low for USB to function properly.
904 * Adjust the busses fractional divider to fix this
905 */
906 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
907 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
908 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
909 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
910 }
911
mtmips_clk_init(struct device_node * node)912 static void __init mtmips_clk_init(struct device_node *node)
913 {
914 const struct of_device_id *match;
915 const struct mtmips_clk_data *data;
916 struct mtmips_clk_priv *priv;
917 struct clk_hw_onecell_data *clk_data;
918 int ret, i, count;
919
920 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
921 if (!priv)
922 return;
923
924 priv->sysc = syscon_node_to_regmap(node);
925 if (IS_ERR(priv->sysc)) {
926 pr_err("Could not get sysc syscon regmap\n");
927 goto free_clk_priv;
928 }
929
930 mtmips_clk_regs_init(node, priv);
931
932 match = of_match_node(mtmips_of_match, node);
933 if (WARN_ON(!match))
934 return;
935
936 data = match->data;
937 priv->data = data;
938 count = priv->data->num_clk_base + priv->data->num_clk_fixed +
939 priv->data->num_clk_factor + priv->data->num_clk_periph;
940 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
941 if (!clk_data)
942 goto free_clk_priv;
943
944 ret = mtmips_register_clocks(node, clk_data, priv);
945 if (ret) {
946 pr_err("Couldn't register top clocks\n");
947 goto free_clk_data;
948 }
949
950 ret = mtmips_register_fixed_clocks(clk_data, priv);
951 if (ret) {
952 pr_err("Couldn't register fixed clocks\n");
953 goto unreg_clk_top;
954 }
955
956 ret = mtmips_register_factor_clocks(clk_data, priv);
957 if (ret) {
958 pr_err("Couldn't register factor clocks\n");
959 goto unreg_clk_fixed;
960 }
961
962 ret = mtmips_register_pherip_clocks(node, clk_data, priv);
963 if (ret) {
964 pr_err("Couldn't register peripheral clocks\n");
965 goto unreg_clk_factor;
966 }
967
968 clk_data->num = count;
969
970 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
971 if (ret) {
972 pr_err("Couldn't add clk hw provider\n");
973 goto unreg_clk_periph;
974 }
975
976 return;
977
978 unreg_clk_periph:
979 for (i = 0; i < priv->data->num_clk_periph; i++) {
980 struct mtmips_clk *sclk = &priv->data->clk_periph[i];
981
982 clk_hw_unregister(&sclk->hw);
983 }
984
985 unreg_clk_factor:
986 for (i = 0; i < priv->data->num_clk_factor; i++) {
987 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
988
989 clk_hw_unregister_fixed_factor(sclk->hw);
990 }
991
992 unreg_clk_fixed:
993 for (i = 0; i < priv->data->num_clk_fixed; i++) {
994 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
995
996 clk_hw_unregister_fixed_rate(sclk->hw);
997 }
998
999 unreg_clk_top:
1000 for (i = 0; i < priv->data->num_clk_base; i++) {
1001 struct mtmips_clk *sclk = &priv->data->clk_base[i];
1002
1003 clk_hw_unregister(&sclk->hw);
1004 }
1005
1006 free_clk_data:
1007 kfree(clk_data);
1008
1009 free_clk_priv:
1010 kfree(priv);
1011 }
1012 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
1013 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
1014 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
1015 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
1016 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
1017 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
1018 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
1019 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
1020 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
1021
1022 struct mtmips_rst {
1023 struct reset_controller_dev rcdev;
1024 struct regmap *sysc;
1025 };
1026
to_mtmips_rst(struct reset_controller_dev * dev)1027 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
1028 {
1029 return container_of(dev, struct mtmips_rst, rcdev);
1030 }
1031
mtmips_assert_device(struct reset_controller_dev * rcdev,unsigned long id)1032 static int mtmips_assert_device(struct reset_controller_dev *rcdev,
1033 unsigned long id)
1034 {
1035 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1036 struct regmap *sysc = data->sysc;
1037
1038 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
1039 }
1040
mtmips_deassert_device(struct reset_controller_dev * rcdev,unsigned long id)1041 static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
1042 unsigned long id)
1043 {
1044 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1045 struct regmap *sysc = data->sysc;
1046
1047 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
1048 }
1049
mtmips_reset_device(struct reset_controller_dev * rcdev,unsigned long id)1050 static int mtmips_reset_device(struct reset_controller_dev *rcdev,
1051 unsigned long id)
1052 {
1053 int ret;
1054
1055 ret = mtmips_assert_device(rcdev, id);
1056 if (ret < 0)
1057 return ret;
1058
1059 return mtmips_deassert_device(rcdev, id);
1060 }
1061
mtmips_rst_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)1062 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
1063 const struct of_phandle_args *reset_spec)
1064 {
1065 unsigned long id = reset_spec->args[0];
1066
1067 if (id == 0 || id >= rcdev->nr_resets)
1068 return -EINVAL;
1069
1070 return id;
1071 }
1072
1073 static const struct reset_control_ops reset_ops = {
1074 .reset = mtmips_reset_device,
1075 .assert = mtmips_assert_device,
1076 .deassert = mtmips_deassert_device
1077 };
1078
mtmips_reset_init(struct device * dev,struct regmap * sysc)1079 static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
1080 {
1081 struct mtmips_rst *rst_data;
1082
1083 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
1084 if (!rst_data)
1085 return -ENOMEM;
1086
1087 rst_data->sysc = sysc;
1088 rst_data->rcdev.ops = &reset_ops;
1089 rst_data->rcdev.owner = THIS_MODULE;
1090 rst_data->rcdev.nr_resets = 32;
1091 rst_data->rcdev.of_reset_n_cells = 1;
1092 rst_data->rcdev.of_xlate = mtmips_rst_xlate;
1093 rst_data->rcdev.of_node = dev_of_node(dev);
1094
1095 return devm_reset_controller_register(dev, &rst_data->rcdev);
1096 }
1097
mtmips_clk_probe(struct platform_device * pdev)1098 static int mtmips_clk_probe(struct platform_device *pdev)
1099 {
1100 struct device_node *np = pdev->dev.of_node;
1101 struct device *dev = &pdev->dev;
1102 struct mtmips_clk_priv *priv;
1103 int ret;
1104
1105 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1106 if (!priv)
1107 return -ENOMEM;
1108
1109 priv->sysc = syscon_node_to_regmap(np);
1110 if (IS_ERR(priv->sysc))
1111 return dev_err_probe(dev, PTR_ERR(priv->sysc),
1112 "Could not get sysc syscon regmap\n");
1113
1114 ret = mtmips_reset_init(dev, priv->sysc);
1115 if (ret)
1116 return dev_err_probe(dev, ret, "Could not init reset controller\n");
1117
1118 return 0;
1119 }
1120
1121 static struct platform_driver mtmips_clk_driver = {
1122 .probe = mtmips_clk_probe,
1123 .driver = {
1124 .name = "mtmips-clk",
1125 .of_match_table = mtmips_of_match,
1126 },
1127 };
1128
mtmips_clk_reset_init(void)1129 static int __init mtmips_clk_reset_init(void)
1130 {
1131 return platform_driver_register(&mtmips_clk_driver);
1132 }
1133 arch_initcall(mtmips_clk_reset_init);
1134