1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver
4 //
5 // Copyright(c) 2024 Realtek Semiconductor Corp.
6 //
7 //
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/dmi.h>
15 #include <linux/firmware.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <sound/initval.h>
21 #include <sound/tlv.h>
22 #include <sound/sdw.h>
23 #include "rt1320-sdw.h"
24 #include "rt-sdw-common.h"
25
26 /*
27 * The 'blind writes' is an SDCA term to deal with platform-specific initialization.
28 * It might include vendor-specific or SDCA control registers.
29 */
30 static const struct reg_sequence rt1320_blind_write[] = {
31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x10 },
36 { 0xc5c4, 0x12 },
37 { 0xc5c8, 0x03 },
38 { 0xc5d8, 0x0a },
39 { 0xc5f7, 0x22 },
40 { 0xc5f6, 0x22 },
41 { 0xc5d0, 0x0f },
42 { 0xc5d1, 0x89 },
43 { 0xc057, 0x51 },
44 { 0xc054, 0x35 },
45 { 0xc053, 0x55 },
46 { 0xc052, 0x55 },
47 { 0xc051, 0x13 },
48 { 0xc050, 0x15 },
49 { 0xc060, 0x77 },
50 { 0xc061, 0x55 },
51 { 0xc063, 0x55 },
52 { 0xc065, 0xa5 },
53 { 0xc06b, 0x0a },
54 { 0xca05, 0xd6 },
55 { 0xca25, 0xd6 },
56 { 0xcd00, 0x05 },
57 { 0xc604, 0x40 },
58 { 0xc609, 0x40 },
59 { 0xc046, 0xff },
60 { 0xc045, 0xff },
61 { 0xc044, 0xff },
62 { 0xc043, 0xff },
63 { 0xc042, 0xff },
64 { 0xc041, 0xff },
65 { 0xc040, 0xff },
66 { 0xcc10, 0x01 },
67 { 0xc700, 0xf0 },
68 { 0xc701, 0x13 },
69 { 0xc901, 0x04 },
70 { 0xc900, 0x73 },
71 { 0xde03, 0x05 },
72 { 0xdd0b, 0x0d },
73 { 0xdd0a, 0xff },
74 { 0xdd09, 0x0d },
75 { 0xdd08, 0xff },
76 { 0xc570, 0x08 },
77 { 0xe803, 0xbe },
78 { 0xc003, 0xc0 },
79 { 0xc081, 0xfe },
80 { 0xce31, 0x0d },
81 { 0xce30, 0xae },
82 { 0xce37, 0x0b },
83 { 0xce36, 0xd2 },
84 { 0xce39, 0x04 },
85 { 0xce38, 0x80 },
86 { 0xce3f, 0x00 },
87 { 0xce3e, 0x00 },
88 { 0xd470, 0x8b },
89 { 0xd471, 0x18 },
90 { 0xc019, 0x10 },
91 { 0xd487, 0x3f },
92 { 0xd486, 0xc3 },
93 { 0x3fc2bfc7, 0x00 },
94 { 0x3fc2bfc6, 0x00 },
95 { 0x3fc2bfc5, 0x00 },
96 { 0x3fc2bfc4, 0x01 },
97 { 0x0000d486, 0x43 },
98 { 0x1000db00, 0x02 },
99 { 0x1000db01, 0x00 },
100 { 0x1000db02, 0x11 },
101 { 0x1000db03, 0x00 },
102 { 0x1000db04, 0x00 },
103 { 0x1000db05, 0x82 },
104 { 0x1000db06, 0x04 },
105 { 0x1000db07, 0xf1 },
106 { 0x1000db08, 0x00 },
107 { 0x1000db09, 0x00 },
108 { 0x1000db0a, 0x40 },
109 { 0x0000d540, 0x01 },
110 { 0xd172, 0x2a },
111 { 0xc5d6, 0x01 },
112 { 0xd478, 0xff },
113 };
114
115 static const struct reg_sequence rt1320_vc_blind_write[] = {
116 { 0xc003, 0xe0 },
117 { 0xe80a, 0x01 },
118 { 0xc5c3, 0xf2 },
119 { 0xc5c8, 0x03 },
120 { 0xc057, 0x51 },
121 { 0xc054, 0x35 },
122 { 0xca05, 0xd6 },
123 { 0xca07, 0x07 },
124 { 0xca25, 0xd6 },
125 { 0xca27, 0x07 },
126 { 0xc604, 0x40 },
127 { 0xc609, 0x40 },
128 { 0xc046, 0xff },
129 { 0xc045, 0xff },
130 { 0xc044, 0xff },
131 { 0xc043, 0xff },
132 { 0xc042, 0xff },
133 { 0xc041, 0x7f },
134 { 0xc040, 0xff },
135 { 0xcc10, 0x01 },
136 { 0xc700, 0xf0 },
137 { 0xc701, 0x13 },
138 { 0xc901, 0x04 },
139 { 0xc900, 0x73 },
140 { 0xde03, 0x05 },
141 { 0xdd0b, 0x0d },
142 { 0xdd0a, 0xff },
143 { 0xdd09, 0x0d },
144 { 0xdd08, 0xff },
145 { 0xc570, 0x08 },
146 { 0xc086, 0x02 },
147 { 0xc085, 0x7f },
148 { 0xc084, 0x00 },
149 { 0xc081, 0xfe },
150 { 0xf084, 0x0f },
151 { 0xf083, 0xff },
152 { 0xf082, 0xff },
153 { 0xf081, 0xff },
154 { 0xf080, 0xff },
155 { 0xe801, 0x01 },
156 { 0xe802, 0xf8 },
157 { 0xe803, 0xbe },
158 { 0xc003, 0xc0 },
159 { 0xd470, 0xec },
160 { 0xd471, 0x3a },
161 { 0xd474, 0x11 },
162 { 0xd475, 0x32 },
163 { 0xd478, 0xff },
164 { 0xd479, 0x20 },
165 { 0xd47a, 0x10 },
166 { 0xd47c, 0xff },
167 { 0xc019, 0x10 },
168 { 0xd487, 0x0b },
169 { 0xd487, 0x3b },
170 { 0xd486, 0xc3 },
171 { 0xc598, 0x04 },
172 { 0xdb03, 0xf0 },
173 { 0xdb09, 0x00 },
174 { 0xdb08, 0x7a },
175 { 0xdb19, 0x02 },
176 { 0xdb07, 0x5a },
177 { 0xdb05, 0x45 },
178 { 0xd500, 0x00 },
179 { 0xd500, 0x17 },
180 { 0xd600, 0x01 },
181 { 0xd601, 0x02 },
182 { 0xd602, 0x03 },
183 { 0xd603, 0x04 },
184 { 0xd64c, 0x03 },
185 { 0xd64d, 0x03 },
186 { 0xd64e, 0x03 },
187 { 0xd64f, 0x03 },
188 { 0xd650, 0x03 },
189 { 0xd651, 0x03 },
190 { 0xd652, 0x03 },
191 { 0xd610, 0x01 },
192 { 0xd608, 0x03 },
193 { 0xd609, 0x00 },
194 { 0x3fc2bf83, 0x00 },
195 { 0x3fc2bf82, 0x00 },
196 { 0x3fc2bf81, 0x00 },
197 { 0x3fc2bf80, 0x00 },
198 { 0x3fc2bfc7, 0x00 },
199 { 0x3fc2bfc6, 0x00 },
200 { 0x3fc2bfc5, 0x00 },
201 { 0x3fc2bfc4, 0x00 },
202 { 0x3fc2bfc3, 0x00 },
203 { 0x3fc2bfc2, 0x00 },
204 { 0x3fc2bfc1, 0x00 },
205 { 0x3fc2bfc0, 0x07 },
206 { 0x1000cc46, 0x00 },
207 { 0x0000d486, 0x43 },
208 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 },
209 { 0x1000db00, 0x07 },
210 { 0x1000db01, 0x00 },
211 { 0x1000db02, 0x11 },
212 { 0x1000db03, 0x00 },
213 { 0x1000db04, 0x00 },
214 { 0x1000db05, 0x82 },
215 { 0x1000db06, 0x04 },
216 { 0x1000db07, 0xf1 },
217 { 0x1000db08, 0x00 },
218 { 0x1000db09, 0x00 },
219 { 0x1000db0a, 0x40 },
220 { 0x1000db0b, 0x02 },
221 { 0x1000db0c, 0xf2 },
222 { 0x1000db0d, 0x00 },
223 { 0x1000db0e, 0x00 },
224 { 0x1000db0f, 0xe0 },
225 { 0x1000db10, 0x00 },
226 { 0x1000db11, 0x10 },
227 { 0x1000db12, 0x00 },
228 { 0x1000db13, 0x00 },
229 { 0x1000db14, 0x45 },
230 { 0x1000db15, 0x0d },
231 { 0x1000db16, 0x01 },
232 { 0x1000db17, 0x00 },
233 { 0x1000db18, 0x00 },
234 { 0x1000db19, 0xbf },
235 { 0x1000db1a, 0x13 },
236 { 0x1000db1b, 0x09 },
237 { 0x1000db1c, 0x00 },
238 { 0x1000db1d, 0x00 },
239 { 0x1000db1e, 0x00 },
240 { 0x1000db1f, 0x12 },
241 { 0x1000db20, 0x09 },
242 { 0x1000db21, 0x00 },
243 { 0x1000db22, 0x00 },
244 { 0x1000db23, 0x00 },
245 { 0x0000d540, 0x21 },
246 { 0xc01b, 0xfc },
247 { 0xc5d1, 0x89 },
248 { 0xc5d8, 0x0a },
249 { 0xc5f7, 0x22 },
250 { 0xc5f6, 0x22 },
251 { 0xc065, 0xa5 },
252 { 0xc06b, 0x0a },
253 { 0xd172, 0x2a },
254 { 0xc5d6, 0x01 },
255 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
256 };
257
258 static const struct reg_sequence rt1321_blind_write[] = {
259 { 0x0000c003, 0xf0 },
260 { 0x0000c01b, 0xfc },
261 { 0x0000c5c3, 0xf2 },
262 { 0x0000c5c2, 0x00 },
263 { 0x0000c5c1, 0x10 },
264 { 0x0000c5c0, 0x04 },
265 { 0x0000c5c7, 0x03 },
266 { 0x0000c5c6, 0x10 },
267 { 0x0000c526, 0x47 },
268 { 0x0000c5c4, 0x12 },
269 { 0x0000c5c5, 0x60 },
270 { 0x0000c520, 0x10 },
271 { 0x0000c521, 0x32 },
272 { 0x0000c5c7, 0x00 },
273 { 0x0000c5c8, 0x03 },
274 { 0x0000c5d3, 0x08 },
275 { 0x0000c5d2, 0x0a },
276 { 0x0000c5d1, 0x49 },
277 { 0x0000c5d0, 0x0f },
278 { 0x0000c580, 0x10 },
279 { 0x0000c581, 0x32 },
280 { 0x0000c582, 0x01 },
281 { 0x0000cb00, 0x03 },
282 { 0x0000cb02, 0x52 },
283 { 0x0000cb04, 0x80 },
284 { 0x0000cb0b, 0x01 },
285 { 0x0000c682, 0x60 },
286 { 0x0000c019, 0x10 },
287 { 0x0000c5f0, 0x01 },
288 { 0x0000c5f7, 0x22 },
289 { 0x0000c5f6, 0x22 },
290 { 0x0000c057, 0x51 },
291 { 0x0000c054, 0x55 },
292 { 0x0000c053, 0x55 },
293 { 0x0000c052, 0x55 },
294 { 0x0000c051, 0x01 },
295 { 0x0000c050, 0x15 },
296 { 0x0000c060, 0x99 },
297 { 0x0000c030, 0x55 },
298 { 0x0000c061, 0x55 },
299 { 0x0000c063, 0x55 },
300 { 0x0000c065, 0xa5 },
301 { 0x0000c06b, 0x0a },
302 { 0x0000ca05, 0xd6 },
303 { 0x0000ca07, 0x07 },
304 { 0x0000ca25, 0xd6 },
305 { 0x0000ca27, 0x07 },
306 { 0x0000cd00, 0x05 },
307 { 0x0000c604, 0x40 },
308 { 0x0000c609, 0x40 },
309 { 0x0000c046, 0xf7 },
310 { 0x0000c045, 0xff },
311 { 0x0000c044, 0xff },
312 { 0x0000c043, 0xff },
313 { 0x0000c042, 0xff },
314 { 0x0000c041, 0xff },
315 { 0x0000c040, 0xff },
316 { 0x0000c049, 0xff },
317 { 0x0000c028, 0x3f },
318 { 0x0000c020, 0x3f },
319 { 0x0000c032, 0x13 },
320 { 0x0000c033, 0x01 },
321 { 0x0000cc10, 0x01 },
322 { 0x0000dc20, 0x03 },
323 { 0x0000de03, 0x05 },
324 { 0x0000dc00, 0x00 },
325 { 0x0000c700, 0xf0 },
326 { 0x0000c701, 0x13 },
327 { 0x0000c900, 0xc3 },
328 { 0x0000c570, 0x08 },
329 { 0x0000c086, 0x02 },
330 { 0x0000c085, 0x7f },
331 { 0x0000c084, 0x00 },
332 { 0x0000c081, 0xff },
333 { 0x0000f084, 0x0f },
334 { 0x0000f083, 0xff },
335 { 0x0000f082, 0xff },
336 { 0x0000f081, 0xff },
337 { 0x0000f080, 0xff },
338 { 0x20003003, 0x3f },
339 { 0x20005818, 0x81 },
340 { 0x20009018, 0x81 },
341 { 0x2000301c, 0x81 },
342 { 0x0000c003, 0xc0 },
343 { 0x0000c047, 0x80 },
344 { 0x0000d541, 0x80 },
345 { 0x0000d487, 0x0b },
346 { 0x0000d487, 0x3b },
347 { 0x0000d486, 0xc3 },
348 { 0x0000d470, 0x89 },
349 { 0x0000d471, 0x3a },
350 { 0x0000d472, 0x1d },
351 { 0x0000d478, 0xff },
352 { 0x0000d479, 0x20 },
353 { 0x0000d47a, 0x10 },
354 { 0x0000d73c, 0xb7 },
355 { 0x0000d73d, 0xd7 },
356 { 0x0000d73e, 0x00 },
357 { 0x0000d73f, 0x10 },
358 { 0x1000cd56, 0x00 },
359 { 0x3fc2dfc3, 0x00 },
360 { 0x3fc2dfc2, 0x00 },
361 { 0x3fc2dfc1, 0x00 },
362 { 0x3fc2dfc0, 0x07 },
363 { 0x3fc2dfc7, 0x00 },
364 { 0x3fc2dfc6, 0x00 },
365 { 0x3fc2dfc5, 0x00 },
366 { 0x3fc2dfc4, 0x01 },
367 { 0x3fc2df83, 0x00 },
368 { 0x3fc2df82, 0x00 },
369 { 0x3fc2df81, 0x00 },
370 { 0x3fc2df80, 0x00 },
371 { 0x0000d541, 0x40 },
372 { 0x0000d486, 0x43 },
373 { 0x1000db00, 0x03 },
374 { 0x1000db01, 0x00 },
375 { 0x1000db02, 0x10 },
376 { 0x1000db03, 0x00 },
377 { 0x1000db04, 0x00 },
378 { 0x1000db05, 0x45 },
379 { 0x1000db06, 0x12 },
380 { 0x1000db07, 0x09 },
381 { 0x1000db08, 0x00 },
382 { 0x1000db09, 0x00 },
383 { 0x1000db0a, 0x00 },
384 { 0x1000db0b, 0x13 },
385 { 0x1000db0c, 0x09 },
386 { 0x1000db0d, 0x00 },
387 { 0x1000db0e, 0x00 },
388 { 0x1000db0f, 0x00 },
389 { 0x0000d540, 0x21 },
390 { 0x41000189, 0x00 },
391 { 0x4100018a, 0x00 },
392 { 0x41001988, 0x00 },
393 { 0x41081400, 0x09 },
394 { 0x40801508, 0x03 },
395 { 0x40801588, 0x03 },
396 { 0x40801809, 0x00 },
397 { 0x4080180a, 0x00 },
398 { 0x4080180b, 0x00 },
399 { 0x4080180c, 0x00 },
400 { 0x40801b09, 0x00 },
401 { 0x40801b0a, 0x00 },
402 { 0x40801b0b, 0x00 },
403 { 0x40801b0c, 0x00 },
404 { 0x0000d714, 0x17 },
405 { 0x20009012, 0x00 },
406 { 0x0000dd0b, 0x0d },
407 { 0x0000dd0a, 0xff },
408 { 0x0000dd09, 0x0d },
409 { 0x0000dd08, 0xff },
410 { 0x0000d172, 0x2a },
411 { 0x41001988, 0x03 },
412 };
413
414 static const struct reg_default rt1320_reg_defaults[] = {
415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
421 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
422 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
428 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
429 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
430 };
431
432 static const struct reg_default rt1320_mbq_defaults[] = {
433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
435 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
436 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
437 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
438 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
439 };
440
rt1320_readable_register(struct device * dev,unsigned int reg)441 static bool rt1320_readable_register(struct device *dev, unsigned int reg)
442 {
443 switch (reg) {
444 case 0xc000 ... 0xc086:
445 case 0xc400 ... 0xc409:
446 case 0xc480 ... 0xc48f:
447 case 0xc4c0 ... 0xc4c4:
448 case 0xc4e0 ... 0xc4e7:
449 case 0xc500:
450 case 0xc560 ... 0xc56b:
451 case 0xc570:
452 case 0xc580 ... 0xc59a:
453 case 0xc5b0 ... 0xc60f:
454 case 0xc640 ... 0xc64f:
455 case 0xc670:
456 case 0xc680 ... 0xc683:
457 case 0xc700 ... 0xc76f:
458 case 0xc800 ... 0xc801:
459 case 0xc820:
460 case 0xc900 ... 0xc901:
461 case 0xc920 ... 0xc921:
462 case 0xca00 ... 0xca07:
463 case 0xca20 ... 0xca27:
464 case 0xca40 ... 0xca4b:
465 case 0xca60 ... 0xca68:
466 case 0xca80 ... 0xca88:
467 case 0xcb00 ... 0xcb0c:
468 case 0xcc00 ... 0xcc12:
469 case 0xcc80 ... 0xcc81:
470 case 0xcd00:
471 case 0xcd80 ... 0xcd82:
472 case 0xce00 ... 0xce4d:
473 case 0xcf00 ... 0xcf25:
474 case 0xd000 ... 0xd0ff:
475 case 0xd100 ... 0xd1ff:
476 case 0xd200 ... 0xd2ff:
477 case 0xd300 ... 0xd3ff:
478 case 0xd400 ... 0xd403:
479 case 0xd410 ... 0xd417:
480 case 0xd470 ... 0xd497:
481 case 0xd4dc ... 0xd50f:
482 case 0xd520 ... 0xd543:
483 case 0xd560 ... 0xd5ef:
484 case 0xd600 ... 0xd663:
485 case 0xda00 ... 0xda6e:
486 case 0xda80 ... 0xda9e:
487 case 0xdb00 ... 0xdb7f:
488 case 0xdc00:
489 case 0xdc20 ... 0xdc21:
490 case 0xdd00 ... 0xdd17:
491 case 0xde00 ... 0xde09:
492 case 0xdf00 ... 0xdf1b:
493 case 0xe000 ... 0xe847:
494 case 0xf01e:
495 case 0xf717 ... 0xf719:
496 case 0xf720 ... 0xf723:
497 case 0x1000cd91 ... 0x1000cd96:
498 case RT1321_PATCH_MAIN_VER ... RT1321_PATCH_BETA_VER:
499 case 0x1000f008:
500 case 0x1000f021:
501 case 0x2000300f:
502 case 0x2000301c:
503 case 0x2000900f:
504 case 0x20009018:
505 case 0x3fc000c0 ... 0x3fc2dfc8:
506 case 0x3fe00000 ... 0x3fe36fff:
507 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
508 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
509 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01):
510 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02):
511 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01):
512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02):
513 /* 0x40880900/0x40880980 */
514 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
515 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
516 /* 0x40881500 */
517 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
518 /* 0x41000189/0x4100018a */
519 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
520 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
521 /* 0x41001388 */
522 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
523 /* 0x41001988 */
524 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
525 /* 0x41080000 */
526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
527 /* 0x41080200 */
528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
529 /* 0x41080900 */
530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
531 /* 0x41080980 */
532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
533 /* 0x41081080 */
534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
535 /* 0x41081480/0x41081488 */
536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
537 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
538 /* 0x41081980 */
539 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
540 return true;
541 default:
542 return false;
543 }
544 }
545
rt1320_volatile_register(struct device * dev,unsigned int reg)546 static bool rt1320_volatile_register(struct device *dev, unsigned int reg)
547 {
548 switch (reg) {
549 case 0xc000:
550 case 0xc003:
551 case 0xc081:
552 case 0xc402 ... 0xc406:
553 case 0xc48c ... 0xc48f:
554 case 0xc560:
555 case 0xc5b5 ... 0xc5b7:
556 case 0xc5c3:
557 case 0xc5c8:
558 case 0xc5fc ... 0xc5ff:
559 case 0xc680 ... 0xc683:
560 case 0xc820:
561 case 0xc900:
562 case 0xc920:
563 case 0xca42:
564 case 0xca62:
565 case 0xca82:
566 case 0xcd00:
567 case 0xce03:
568 case 0xce10:
569 case 0xce14 ... 0xce17:
570 case 0xce44 ... 0xce49:
571 case 0xce4c ... 0xce4d:
572 case 0xcf0c:
573 case 0xcf10 ... 0xcf25:
574 case 0xd486 ... 0xd487:
575 case 0xd4e5 ... 0xd4e6:
576 case 0xd4e8 ... 0xd4ff:
577 case 0xd530:
578 case 0xd540 ... 0xd541:
579 case 0xd543:
580 case 0xdb58 ... 0xdb5f:
581 case 0xdb60 ... 0xdb63:
582 case 0xdb68 ... 0xdb69:
583 case 0xdb6d:
584 case 0xdb70 ... 0xdb71:
585 case 0xdb76:
586 case 0xdb7a:
587 case 0xdb7c ... 0xdb7f:
588 case 0xdd0c ... 0xdd13:
589 case 0xde02:
590 case 0xdf14 ... 0xdf1b:
591 case 0xe80b:
592 case 0xe83c ... 0xe847:
593 case 0xf01e:
594 case 0xf717 ... 0xf719:
595 case 0xf720 ... 0xf723:
596 case 0x10000000 ... 0x10008fff:
597 case 0x1000c000 ... 0x1000dfff:
598 case 0x1000f008:
599 case 0x1000f021:
600 case 0x2000300f:
601 case 0x2000301c:
602 case 0x2000900f:
603 case 0x20009018:
604 case 0x3fc2ab80 ... 0x3fc2ac4c:
605 case 0x3fc2b780:
606 case 0x3fc2bf80 ... 0x3fc2bf83:
607 case 0x3fc2bfc0 ... 0x3fc2bfc8:
608 case 0x3fc2d300 ... 0x3fc2d354:
609 case 0x3fc2dfc0 ... 0x3fc2dfc8:
610 case 0x3fe2e000 ... 0x3fe2e003:
611 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
612 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
615 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
616 return true;
617 default:
618 return false;
619 }
620 }
621
rt1320_mbq_readable_register(struct device * dev,unsigned int reg)622 static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
623 {
624 switch (reg) {
625 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
626 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
627 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
628 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
629 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
630 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
631 return true;
632 default:
633 return false;
634 }
635 }
636
637 static const struct regmap_config rt1320_sdw_regmap = {
638 .reg_bits = 32,
639 .val_bits = 8,
640 .readable_reg = rt1320_readable_register,
641 .volatile_reg = rt1320_volatile_register,
642 .max_register = 0x41081980,
643 .reg_defaults = rt1320_reg_defaults,
644 .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults),
645 .cache_type = REGCACHE_MAPLE,
646 .use_single_read = true,
647 .use_single_write = true,
648 };
649
650 static const struct regmap_config rt1320_mbq_regmap = {
651 .name = "sdw-mbq",
652 .reg_bits = 32,
653 .val_bits = 16,
654 .readable_reg = rt1320_mbq_readable_register,
655 .max_register = 0x41000192,
656 .reg_defaults = rt1320_mbq_defaults,
657 .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults),
658 .cache_type = REGCACHE_MAPLE,
659 .use_single_read = true,
660 .use_single_write = true,
661 };
662
rt1320_read_prop(struct sdw_slave * slave)663 static int rt1320_read_prop(struct sdw_slave *slave)
664 {
665 struct sdw_slave_prop *prop = &slave->prop;
666 int nval;
667 int i, j;
668 u32 bit;
669 unsigned long addr;
670 struct sdw_dpn_prop *dpn;
671
672 /*
673 * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping
674 */
675 sdw_slave_read_prop(slave);
676
677 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
678 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
679
680 prop->paging_support = true;
681 prop->lane_control_support = true;
682
683 /* first we need to allocate memory for set bits in port lists */
684 prop->source_ports = BIT(4) | BIT(8) | BIT(10);
685 prop->sink_ports = BIT(1);
686
687 nval = hweight32(prop->source_ports);
688 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
689 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
690 if (!prop->src_dpn_prop)
691 return -ENOMEM;
692
693 i = 0;
694 dpn = prop->src_dpn_prop;
695 addr = prop->source_ports;
696 for_each_set_bit(bit, &addr, 32) {
697 dpn[i].num = bit;
698 dpn[i].type = SDW_DPN_FULL;
699 dpn[i].simple_ch_prep_sm = true;
700 dpn[i].ch_prep_timeout = 10;
701 i++;
702 }
703
704 /* do this again for sink now */
705 nval = hweight32(prop->sink_ports);
706 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
707 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
708 if (!prop->sink_dpn_prop)
709 return -ENOMEM;
710
711 j = 0;
712 dpn = prop->sink_dpn_prop;
713 addr = prop->sink_ports;
714 for_each_set_bit(bit, &addr, 32) {
715 dpn[j].num = bit;
716 dpn[j].type = SDW_DPN_FULL;
717 dpn[j].simple_ch_prep_sm = true;
718 dpn[j].ch_prep_timeout = 10;
719 j++;
720 }
721
722 prop->dp0_prop = devm_kzalloc(&slave->dev, sizeof(*prop->dp0_prop), GFP_KERNEL);
723 if (!prop->dp0_prop)
724 return -ENOMEM;
725
726 prop->dp0_prop->simple_ch_prep_sm = true;
727 prop->dp0_prop->ch_prep_timeout = 10;
728
729 /* set the timeout values */
730 prop->clk_stop_timeout = 64;
731
732 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */
733 prop->wake_capable = 0;
734
735 return 0;
736 }
737
rt1320_pde_transition_delay(struct rt1320_sdw_priv * rt1320,unsigned char func,unsigned char entity,unsigned char ps)738 static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func,
739 unsigned char entity, unsigned char ps)
740 {
741 unsigned int delay = 2000, val;
742
743 pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev);
744
745 /* waiting for Actual PDE becomes to PS0/PS3 */
746 while (delay) {
747 regmap_read(rt1320->regmap,
748 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
749 if (val == ps)
750 break;
751
752 usleep_range(1000, 1500);
753 delay--;
754 }
755 if (!delay) {
756 dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
757 return -ETIMEDOUT;
758 }
759
760 return 0;
761 }
762
rt1320_data_rw(struct rt1320_sdw_priv * rt1320,unsigned int start,unsigned char * data,unsigned int size,enum rt1320_rw_type rw)763 static void rt1320_data_rw(struct rt1320_sdw_priv *rt1320, unsigned int start,
764 unsigned char *data, unsigned int size, enum rt1320_rw_type rw)
765 {
766 struct device *dev = &rt1320->sdw_slave->dev;
767 unsigned int tmp;
768 int ret = -1;
769 int i, j;
770
771 pm_runtime_set_autosuspend_delay(dev, 20000);
772 pm_runtime_mark_last_busy(dev);
773
774 switch (rw) {
775 case RT1320_BRA_WRITE:
776 case RT1320_BRA_READ:
777 ret = sdw_bpt_send_sync(rt1320->sdw_slave->bus, rt1320->sdw_slave, &rt1320->bra_msg);
778 if (ret < 0)
779 dev_err(dev, "%s: Failed to send BRA message: %d\n", __func__, ret);
780 fallthrough;
781 case RT1320_PARAM_WRITE:
782 case RT1320_PARAM_READ:
783 if (ret < 0) {
784 /* if BRA fails, we try to access by the control word */
785 if (rw == RT1320_BRA_WRITE || rw == RT1320_BRA_READ) {
786 for (i = 0; i < rt1320->bra_msg.sections; i++) {
787 pm_runtime_mark_last_busy(dev);
788 for (j = 0; j < rt1320->bra_msg.sec[i].len; j++) {
789 if (rw == RT1320_BRA_WRITE) {
790 regmap_write(rt1320->regmap,
791 rt1320->bra_msg.sec[i].addr + j, rt1320->bra_msg.sec[i].buf[j]);
792 } else {
793 regmap_read(rt1320->regmap, rt1320->bra_msg.sec[i].addr + j, &tmp);
794 rt1320->bra_msg.sec[i].buf[j] = tmp;
795 }
796 }
797 }
798 } else {
799 for (i = 0; i < size; i++) {
800 if (rw == RT1320_PARAM_WRITE)
801 regmap_write(rt1320->regmap, start + i, data[i]);
802 else {
803 regmap_read(rt1320->regmap, start + i, &tmp);
804 data[i] = tmp;
805 }
806 }
807 }
808 }
809 break;
810 }
811
812 pm_runtime_set_autosuspend_delay(dev, 3000);
813 pm_runtime_mark_last_busy(dev);
814 }
815
rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv * rt1320,unsigned int rsgain)816 static unsigned long long rt1320_rsgain_to_rsratio(struct rt1320_sdw_priv *rt1320, unsigned int rsgain)
817 {
818 unsigned long long base = 1000000000U;
819 unsigned long long step = 1960784U;
820 unsigned long long tmp, result;
821
822 if (rsgain == 0 || rsgain == 0x1ff)
823 result = 1000000000;
824 else if (rsgain & 0x100) {
825 tmp = 0xff - (rsgain & 0xff);
826 tmp = tmp * step;
827 result = base + tmp;
828 } else {
829 tmp = (rsgain & 0xff);
830 tmp = tmp * step;
831 result = base - tmp;
832 }
833
834 return result;
835 }
836
rt1320_pr_read(struct rt1320_sdw_priv * rt1320,unsigned int reg,unsigned int * val)837 static void rt1320_pr_read(struct rt1320_sdw_priv *rt1320, unsigned int reg, unsigned int *val)
838 {
839 unsigned int byte3, byte2, byte1, byte0;
840
841 regmap_write(rt1320->regmap, 0xc483, 0x80);
842 regmap_write(rt1320->regmap, 0xc482, 0x40);
843 regmap_write(rt1320->regmap, 0xc481, 0x0c);
844 regmap_write(rt1320->regmap, 0xc480, 0x10);
845
846 regmap_write(rt1320->regmap, 0xc487, ((reg & 0xff000000) >> 24));
847 regmap_write(rt1320->regmap, 0xc486, ((reg & 0x00ff0000) >> 16));
848 regmap_write(rt1320->regmap, 0xc485, ((reg & 0x0000ff00) >> 8));
849 regmap_write(rt1320->regmap, 0xc484, (reg & 0x000000ff));
850
851 regmap_write(rt1320->regmap, 0xc482, 0xc0);
852
853 regmap_read(rt1320->regmap, 0xc48f, &byte3);
854 regmap_read(rt1320->regmap, 0xc48e, &byte2);
855 regmap_read(rt1320->regmap, 0xc48d, &byte1);
856 regmap_read(rt1320->regmap, 0xc48c, &byte0);
857
858 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
859 }
860
rt1320_check_fw_ready(struct rt1320_sdw_priv * rt1320)861 static int rt1320_check_fw_ready(struct rt1320_sdw_priv *rt1320)
862 {
863 struct device *dev = &rt1320->sdw_slave->dev;
864 unsigned int tmp, retry = 0;
865 unsigned int cmd_addr;
866
867 switch (rt1320->dev_id) {
868 case RT1320_DEV_ID:
869 cmd_addr = RT1320_CMD_ID;
870 break;
871 case RT1321_DEV_ID:
872 cmd_addr = RT1321_CMD_ID;
873 break;
874 default:
875 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
876 return -EINVAL;
877 }
878
879 pm_runtime_mark_last_busy(dev);
880 /* check the value of cmd_addr becomes to zero */
881 while (retry < 500) {
882 regmap_read(rt1320->regmap, cmd_addr, &tmp);
883 if (tmp == 0)
884 break;
885 usleep_range(1000, 1100);
886 retry++;
887 }
888 if (retry == 500) {
889 dev_warn(dev, "%s FW is NOT ready!", __func__);
890 return -ETIMEDOUT;
891 }
892
893 return 0;
894 }
895
rt1320_check_power_state_ready(struct rt1320_sdw_priv * rt1320,enum rt1320_power_state ps)896 static int rt1320_check_power_state_ready(struct rt1320_sdw_priv *rt1320, enum rt1320_power_state ps)
897 {
898 struct device *dev = &rt1320->sdw_slave->dev;
899 unsigned int retry = 0, tmp;
900
901 pm_runtime_mark_last_busy(dev);
902 while (retry < 200) {
903 regmap_read(rt1320->regmap, RT1320_POWER_STATE, &tmp);
904 dev_dbg(dev, "%s, RT1320_POWER_STATE=0x%x\n", __func__, tmp);
905 if (tmp >= ps)
906 break;
907 usleep_range(1000, 1500);
908 retry++;
909 }
910 if (retry == 200) {
911 dev_warn(dev, "%s FW Power State is NOT ready!", __func__);
912 return -ETIMEDOUT;
913 }
914
915 return 0;
916 }
917
rt1320_process_fw_param(struct rt1320_sdw_priv * rt1320,unsigned char * buf,unsigned int buf_size)918 static int rt1320_process_fw_param(struct rt1320_sdw_priv *rt1320, unsigned char *buf, unsigned int buf_size)
919 {
920 struct device *dev = &rt1320->sdw_slave->dev;
921 struct rt1320_paramcmd *paramhr = (struct rt1320_paramcmd *)buf;
922 unsigned char moudleid = paramhr->moudleid;
923 unsigned char cmdtype = paramhr->commandtype;
924 unsigned int fw_param_addr;
925 unsigned int start_addr;
926 int ret = 0;
927
928 switch (rt1320->dev_id) {
929 case RT1320_DEV_ID:
930 fw_param_addr = RT1320_FW_PARAM_ADDR;
931 start_addr = RT1320_CMD_PARAM_ADDR;
932 break;
933 case RT1321_DEV_ID:
934 fw_param_addr = RT1321_FW_PARAM_ADDR;
935 start_addr = RT1321_CMD_PARAM_ADDR;
936 break;
937 default:
938 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
939 return -EINVAL;
940 }
941
942 ret = rt1320_check_fw_ready(rt1320);
943 if (ret < 0)
944 goto _timeout_;
945
946 /* don't set offset 0x0/0x1, it will be set later*/
947 paramhr->moudleid = 0;
948 paramhr->commandtype = 0;
949 rt1320_data_rw(rt1320, fw_param_addr, buf, buf_size, RT1320_PARAM_WRITE);
950
951 dev_dbg(dev, "%s, moudleid=%d, cmdtype=%d, paramid=%d, paramlength=%d\n", __func__,
952 moudleid, cmdtype, paramhr->paramid, paramhr->paramlength);
953
954 if (cmdtype == RT1320_SET_PARAM) {
955 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
956 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x01);
957 }
958 if (cmdtype == RT1320_GET_PARAM) {
959 regmap_write(rt1320->regmap, fw_param_addr, moudleid);
960 regmap_write(rt1320->regmap, fw_param_addr + 1, 0x02);
961 ret = rt1320_check_fw_ready(rt1320);
962 if (ret < 0)
963 goto _timeout_;
964
965 rt1320_data_rw(rt1320, start_addr, buf + 0x10, paramhr->commandlength, RT1320_PARAM_READ);
966 }
967 return 0;
968
969 _timeout_:
970 dev_err(&rt1320->sdw_slave->dev, "%s: FW is NOT ready for SET/GET_PARAM\n", __func__);
971 return ret;
972 }
973
rt1320_fw_param_protocol(struct rt1320_sdw_priv * rt1320,enum rt1320_fw_cmdid cmdid,unsigned int paramid,void * parambuf,unsigned int paramsize)974 static int rt1320_fw_param_protocol(struct rt1320_sdw_priv *rt1320, enum rt1320_fw_cmdid cmdid,
975 unsigned int paramid, void *parambuf, unsigned int paramsize)
976 {
977 struct device *dev = &rt1320->sdw_slave->dev;
978 unsigned char *tempbuf = NULL;
979 struct rt1320_paramcmd paramhr;
980 int ret = 0;
981
982 tempbuf = kzalloc(sizeof(paramhr) + paramsize, GFP_KERNEL);
983 if (!tempbuf)
984 return -ENOMEM;
985
986 paramhr.moudleid = 1;
987 paramhr.commandtype = cmdid;
988 /* 8 is "sizeof(paramid) + sizeof(paramlength)" */
989 paramhr.commandlength = 8 + paramsize;
990 paramhr.paramid = paramid;
991 paramhr.paramlength = paramsize;
992
993 memcpy(tempbuf, ¶mhr, sizeof(paramhr));
994 if (cmdid == RT1320_SET_PARAM)
995 memcpy(tempbuf + sizeof(paramhr), parambuf, paramsize);
996
997 ret = rt1320_process_fw_param(rt1320, tempbuf, sizeof(paramhr) + paramsize);
998 if (ret < 0) {
999 dev_err(dev, "%s: process_fw_param failed\n", __func__);
1000 goto _finish_;
1001 }
1002
1003 if (cmdid == RT1320_GET_PARAM)
1004 memcpy(parambuf, tempbuf + sizeof(paramhr), paramsize);
1005
1006 _finish_:
1007 kfree(tempbuf);
1008 return ret;
1009 }
1010
rt1320_set_advancemode(struct rt1320_sdw_priv * rt1320)1011 static void rt1320_set_advancemode(struct rt1320_sdw_priv *rt1320)
1012 {
1013 struct device *dev = &rt1320->sdw_slave->dev;
1014 struct rt1320_datafixpoint r0_data[2];
1015 unsigned short l_advancegain, r_advancegain;
1016 FwPara_Get_HwSwGain audDriverDataHwSwGain = {0};
1017 unsigned int HwAdvGain = 0;
1018 int ret;
1019
1020 /* Get new hardware advance gain by ID 1300 */
1021 ret = rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 1300,
1022 &audDriverDataHwSwGain, sizeof(audDriverDataHwSwGain));
1023 if (ret == 0) {
1024 HwAdvGain = audDriverDataHwSwGain.HwAdvGain;
1025 dev_dbg(dev, "%s, HwAdvGain=%d\n", __func__, HwAdvGain);
1026 dev_dbg(dev, "%s, HwBasGain=%d\n", __func__, audDriverDataHwSwGain.HwBasGain);
1027 dev_dbg(dev, "%s, SwAdvGain=%d\n", __func__, audDriverDataHwSwGain.SwAdvGain);
1028 dev_dbg(dev, "%s, SwBasGain=%d\n", __func__, audDriverDataHwSwGain.SwBasGain);
1029 } else {
1030 dev_dbg(dev, "%s: param 1300 not supported, ret=%d\n", __func__, ret);
1031 }
1032
1033 /* Get advance gain/r0 */
1034 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1035 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1036
1037 if (HwAdvGain != 0) {
1038 l_advancegain = HwAdvGain & 0xffff;
1039 r_advancegain = (HwAdvGain >> 16) & 0xffff;
1040 } else {
1041 l_advancegain = r0_data[0].advancegain;
1042 r_advancegain = r0_data[1].advancegain;
1043 }
1044 dev_dbg(dev, "%s, LR advanceGain=0x%x 0x%x\n", __func__, l_advancegain, r_advancegain);
1045
1046 /* set R0 and enable protection by SetParameter id 6, 7 */
1047 r0_data[0].silencedetect = 0;
1048 r0_data[0].r0 = rt1320->r0_l_reg;
1049 r0_data[1].silencedetect = 0;
1050 r0_data[1].r0 = rt1320->r0_r_reg;
1051 dev_dbg(dev, "%s, write LR r0=%d, %d\n", __func__, r0_data[0].r0, r0_data[1].r0);
1052
1053 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1054 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1055 ret = rt1320_check_fw_ready(rt1320);
1056 if (ret < 0)
1057 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1058
1059 if (l_advancegain != 0 && r_advancegain != 0) {
1060 regmap_write(rt1320->regmap, 0xdd0b, (l_advancegain & 0xff00) >> 8);
1061 regmap_write(rt1320->regmap, 0xdd0a, (l_advancegain & 0xff));
1062 regmap_write(rt1320->regmap, 0xdd09, (r_advancegain & 0xff00) >> 8);
1063 regmap_write(rt1320->regmap, 0xdd08, (r_advancegain & 0xff));
1064 dev_dbg(dev, "%s, set Advance mode gain\n", __func__);
1065 }
1066 }
1067
rt1320_invrs_load(struct rt1320_sdw_priv * rt1320)1068 static int rt1320_invrs_load(struct rt1320_sdw_priv *rt1320)
1069 {
1070 struct device *dev = &rt1320->sdw_slave->dev;
1071 unsigned long long l_rsratio, r_rsratio;
1072 unsigned int pr_1058, pr_1059, pr_105a;
1073 unsigned long long l_invrs, r_invrs;
1074 unsigned long long factor = (1 << 28);
1075 unsigned int l_rsgain, r_rsgain;
1076 struct rt1320_datafixpoint r0_data[2];
1077 int ret;
1078
1079 /* read L/Rch Rs Gain - it uses for compensating the R0 value */
1080 rt1320_pr_read(rt1320, 0x1058, &pr_1058);
1081 rt1320_pr_read(rt1320, 0x1059, &pr_1059);
1082 rt1320_pr_read(rt1320, 0x105a, &pr_105a);
1083 l_rsgain = ((pr_1059 & 0x7f) << 2) | ((pr_105a & 0xc0) >> 6);
1084 r_rsgain = ((pr_1058 & 0xff) << 1) | ((pr_1059 & 0x80) >> 7);
1085 dev_dbg(dev, "%s, LR rsgain=0x%x, 0x%x\n", __func__, l_rsgain, r_rsgain);
1086
1087 l_rsratio = rt1320_rsgain_to_rsratio(rt1320, l_rsgain);
1088 r_rsratio = rt1320_rsgain_to_rsratio(rt1320, r_rsgain);
1089 dev_dbg(dev, "%s, LR rsratio=%lld, %lld\n", __func__, l_rsratio, r_rsratio);
1090
1091 l_invrs = div_u64(l_rsratio * factor, 1000000000U);
1092 r_invrs = div_u64(r_rsratio * factor, 1000000000U);
1093
1094 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1095 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1096
1097 r0_data[0].invrs = l_invrs;
1098 r0_data[1].invrs = r_invrs;
1099 dev_dbg(dev, "%s, write DSP LR invrs=0x%x, 0x%x\n", __func__, r0_data[0].invrs, r0_data[1].invrs);
1100
1101 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 6, &r0_data[0], sizeof(struct rt1320_datafixpoint));
1102 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 7, &r0_data[1], sizeof(struct rt1320_datafixpoint));
1103 ret = rt1320_check_fw_ready(rt1320);
1104 if (ret < 0)
1105 dev_err(dev, "%s: Failed to set FW param 6,7!\n", __func__);
1106
1107 return ret;
1108 }
1109
rt1320_calc_r0(struct rt1320_sdw_priv * rt1320)1110 static void rt1320_calc_r0(struct rt1320_sdw_priv *rt1320)
1111 {
1112 struct device *dev = &rt1320->sdw_slave->dev;
1113 unsigned long long l_calir0, r_calir0, l_calir0_lo, r_calir0_lo;
1114
1115 l_calir0 = rt1320->r0_l_reg >> 27;
1116 r_calir0 = rt1320->r0_r_reg >> 27;
1117 l_calir0_lo = ((rt1320->r0_l_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1118 r_calir0_lo = ((rt1320->r0_r_reg & ((1ull << 27) - 1)) * 1000) >> 27;
1119
1120 dev_dbg(dev, "%s, l_calir0=%lld.%03lld ohm, r_calir0=%lld.%03lld ohm\n", __func__,
1121 l_calir0, l_calir0_lo, r_calir0, r_calir0_lo);
1122 }
1123
rt1320_calibrate(struct rt1320_sdw_priv * rt1320)1124 static void rt1320_calibrate(struct rt1320_sdw_priv *rt1320)
1125 {
1126 struct device *dev = &rt1320->sdw_slave->dev;
1127 struct rt1320_datafixpoint audfixpoint[2];
1128 unsigned int reg_c5fb, reg_c570, reg_cd00;
1129 unsigned int vol_reg[4], fw_ready;
1130 unsigned long long l_meanr0, r_meanr0;
1131 unsigned int fw_status_addr;
1132 int l_re[5], r_re[5];
1133 int ret, tmp;
1134 unsigned long long factor = (1 << 27);
1135 unsigned short l_advancegain, r_advancegain;
1136 unsigned int delay_s = 7; /* delay seconds for the calibration */
1137
1138 if (!rt1320->component)
1139 return;
1140
1141 switch (rt1320->dev_id) {
1142 case RT1320_DEV_ID:
1143 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1144 break;
1145 case RT1321_DEV_ID:
1146 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1147 break;
1148 default:
1149 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1150 return;
1151 }
1152
1153 /* set volume 0dB */
1154 regmap_read(rt1320->regmap, 0xdd0b, &vol_reg[3]);
1155 regmap_read(rt1320->regmap, 0xdd0a, &vol_reg[2]);
1156 regmap_read(rt1320->regmap, 0xdd09, &vol_reg[1]);
1157 regmap_read(rt1320->regmap, 0xdd08, &vol_reg[0]);
1158 regmap_write(rt1320->regmap, 0xdd0b, 0x0f);
1159 regmap_write(rt1320->regmap, 0xdd0a, 0xff);
1160 regmap_write(rt1320->regmap, 0xdd09, 0x0f);
1161 regmap_write(rt1320->regmap, 0xdd08, 0xff);
1162
1163 regmap_read(rt1320->regmap, 0xc5fb, ®_c5fb);
1164 regmap_read(rt1320->regmap, 0xc570, ®_c570);
1165 regmap_read(rt1320->regmap, 0xcd00, ®_cd00);
1166
1167 regmap_write(rt1320->regmap,
1168 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1169 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1170 if (ret < 0) {
1171 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
1172 goto _finish_;
1173 }
1174
1175 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1176 fw_ready &= 0x1;
1177 if (!fw_ready) {
1178 dev_dbg(dev, "%s, DSP FW is NOT ready. Please load DSP FW first\n", __func__);
1179 goto _finish_;
1180 }
1181
1182 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
1183 if (ret < 0) {
1184 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
1185 goto _finish_;
1186 }
1187
1188 if (rt1320->dev_id == RT1320_DEV_ID)
1189 regmap_write(rt1320->regmap, 0xc5fb, 0x00);
1190 regmap_write(rt1320->regmap, 0xc570, 0x0b);
1191 regmap_write(rt1320->regmap, 0xcd00, 0xc5);
1192
1193 /* disable silence detection */
1194 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0x00);
1195 dev_dbg(dev, "%s, disable silence detection\n", __func__);
1196
1197 ret = rt1320_check_power_state_ready(rt1320, RT1320_K_R0_STATE);
1198 if (ret < 0) {
1199 dev_dbg(dev, "%s, check class D status before k r0\n", __func__);
1200 goto _finish_;
1201 }
1202
1203 for (tmp = 0; tmp < delay_s; tmp++) {
1204 msleep(1000);
1205 pm_runtime_mark_last_busy(dev);
1206
1207 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1208 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1209
1210 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1211 dev_dbg(dev, "%s, waiting for calibration R0...%d seconds\n", __func__, tmp + 1);
1212 }
1213
1214 /* Get Calibration data */
1215 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 11, &l_re[0], sizeof(l_re));
1216 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 12, &r_re[0], sizeof(r_re));
1217 dev_dbg(dev, "%s, LR re=0x%x, 0x%x\n", __func__, l_re[4], r_re[4]);
1218
1219 /* Get advance gain/mean r0 */
1220 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 6, &audfixpoint[0], sizeof(struct rt1320_datafixpoint));
1221 l_meanr0 = audfixpoint[0].meanr0;
1222 l_advancegain = audfixpoint[0].advancegain;
1223 l_meanr0 = ((l_meanr0 * 1000U) / factor);
1224 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 7, &audfixpoint[1], sizeof(struct rt1320_datafixpoint));
1225 r_meanr0 = audfixpoint[1].meanr0;
1226 r_advancegain = audfixpoint[1].advancegain;
1227 r_meanr0 = ((r_meanr0 * 1000U) / factor);
1228 dev_dbg(dev, "%s, LR meanr0=%lld, %lld\n", __func__, l_meanr0, r_meanr0);
1229 dev_dbg(dev, "%s, LR advanceGain=0x%x, 0x%x\n", __func__, l_advancegain, r_advancegain);
1230 dev_dbg(dev, "%s, LR invrs=0x%x, 0x%x\n", __func__, audfixpoint[0].invrs, audfixpoint[1].invrs);
1231
1232 /* enable silence detection */
1233 regmap_update_bits(rt1320->regmap, 0xc044, 0xe0, 0xe0);
1234 dev_dbg(dev, "%s, enable silence detection\n", __func__);
1235
1236 regmap_write(rt1320->regmap, 0xc5fb, reg_c5fb);
1237 regmap_write(rt1320->regmap, 0xc570, reg_c570);
1238 regmap_write(rt1320->regmap, 0xcd00, reg_cd00);
1239
1240 rt1320->r0_l_reg = l_re[4];
1241 rt1320->r0_r_reg = r_re[4];
1242 rt1320->cali_done = true;
1243 rt1320_calc_r0(rt1320);
1244
1245 _finish_:
1246 regmap_write(rt1320->regmap,
1247 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1248 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1249
1250 /* advance gain will be set when R0 load, not here */
1251 regmap_write(rt1320->regmap, 0xdd0b, vol_reg[3]);
1252 regmap_write(rt1320->regmap, 0xdd0a, vol_reg[2]);
1253 regmap_write(rt1320->regmap, 0xdd09, vol_reg[1]);
1254 regmap_write(rt1320->regmap, 0xdd08, vol_reg[0]);
1255 }
1256
rt1320_r0_cali_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1257 static int rt1320_r0_cali_get(struct snd_kcontrol *kcontrol,
1258 struct snd_ctl_elem_value *ucontrol)
1259 {
1260 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1261 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1262
1263 ucontrol->value.integer.value[0] = rt1320->cali_done;
1264 return 0;
1265 }
1266
rt1320_r0_cali_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1267 static int rt1320_r0_cali_put(struct snd_kcontrol *kcontrol,
1268 struct snd_ctl_elem_value *ucontrol)
1269 {
1270 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1271 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1272 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
1273 int ret;
1274
1275 if (!rt1320->hw_init)
1276 return 0;
1277
1278 ret = pm_runtime_resume(component->dev);
1279 if (ret < 0 && ret != -EACCES)
1280 return ret;
1281
1282 rt1320->cali_done = false;
1283 snd_soc_dapm_mutex_lock(dapm);
1284 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
1285 ucontrol->value.integer.value[0]) {
1286 rt1320_calibrate(rt1320);
1287 }
1288 snd_soc_dapm_mutex_unlock(dapm);
1289
1290 return 0;
1291 }
1292
1293 /*
1294 * The 'patch code' is written to the patch code area.
1295 * The patch code area is used for SDCA register expansion flexibility.
1296 */
rt1320_load_mcu_patch(struct rt1320_sdw_priv * rt1320)1297 static void rt1320_load_mcu_patch(struct rt1320_sdw_priv *rt1320)
1298 {
1299 struct sdw_slave *slave = rt1320->sdw_slave;
1300 const struct firmware *patch;
1301 const char *filename;
1302 unsigned int addr, val, min_addr, max_addr;
1303 const unsigned char *ptr;
1304 int ret, i;
1305
1306 switch (rt1320->dev_id) {
1307 case RT1320_DEV_ID:
1308 if (rt1320->version_id <= RT1320_VB)
1309 filename = RT1320_VAB_MCU_PATCH;
1310 else
1311 filename = RT1320_VC_MCU_PATCH;
1312 min_addr = 0x10007000;
1313 max_addr = 0x10007fff;
1314 break;
1315 case RT1321_DEV_ID:
1316 filename = RT1321_VA_MCU_PATCH;
1317 min_addr = 0x10008000;
1318 max_addr = 0x10008fff;
1319 break;
1320 default:
1321 dev_err(&slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1322 return;
1323 }
1324
1325 /* load the patch code here */
1326 ret = request_firmware(&patch, filename, &slave->dev);
1327 if (ret) {
1328 dev_err(&slave->dev, "%s: Failed to load %s firmware", __func__, filename);
1329 regmap_write(rt1320->regmap, 0xc598, 0x00);
1330 regmap_write(rt1320->regmap, min_addr, 0x67);
1331 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80);
1332 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00);
1333 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00);
1334 if (rt1320->dev_id == RT1321_DEV_ID) {
1335 regmap_write(rt1320->regmap, 0xd73c, 0x67);
1336 regmap_write(rt1320->regmap, 0xd73d, 0x80);
1337 regmap_write(rt1320->regmap, 0xd73e, 0x00);
1338 regmap_write(rt1320->regmap, 0xd73f, 0x00);
1339 }
1340 } else {
1341 ptr = (const unsigned char *)patch->data;
1342 if ((patch->size % 8) == 0) {
1343 for (i = 0; i < patch->size; i += 8) {
1344 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 |
1345 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24;
1346 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 |
1347 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24;
1348
1349 if (addr > max_addr || addr < min_addr) {
1350 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr);
1351 goto _exit_;
1352 }
1353 if (val > 0xff) {
1354 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val);
1355 goto _exit_;
1356 }
1357 regmap_write(rt1320->regmap, addr, val);
1358 }
1359 }
1360 _exit_:
1361 release_firmware(patch);
1362 }
1363 }
1364
rt1320_vab_preset(struct rt1320_sdw_priv * rt1320)1365 static void rt1320_vab_preset(struct rt1320_sdw_priv *rt1320)
1366 {
1367 unsigned int i, reg, val, delay;
1368
1369 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) {
1370 reg = rt1320_blind_write[i].reg;
1371 val = rt1320_blind_write[i].def;
1372 delay = rt1320_blind_write[i].delay_us;
1373
1374 if (reg == 0x3fc2bfc7)
1375 rt1320_load_mcu_patch(rt1320);
1376
1377 regmap_write(rt1320->regmap, reg, val);
1378 if (delay)
1379 usleep_range(delay, delay + 1000);
1380 }
1381 }
1382
rt1320_t0_load(struct rt1320_sdw_priv * rt1320,unsigned int l_t0,unsigned int r_t0)1383 static void rt1320_t0_load(struct rt1320_sdw_priv *rt1320, unsigned int l_t0, unsigned int r_t0)
1384 {
1385 struct device *dev = &rt1320->sdw_slave->dev;
1386 unsigned int factor = (1 << 22), fw_ready;
1387 int l_t0_data[38], r_t0_data[38];
1388 unsigned int fw_status_addr;
1389
1390 switch (rt1320->dev_id) {
1391 case RT1320_DEV_ID:
1392 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1393 break;
1394 case RT1321_DEV_ID:
1395 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1396 break;
1397 default:
1398 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1399 return;
1400 }
1401
1402 regmap_write(rt1320->regmap,
1403 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1404 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1405 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1406
1407 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1408 fw_ready &= 0x1;
1409 if (!fw_ready) {
1410 dev_warn(dev, "%s, DSP FW is NOT ready\n", __func__);
1411 goto _exit_;
1412 }
1413
1414 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1415 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1416
1417 l_t0_data[37] = l_t0 * factor;
1418 r_t0_data[37] = r_t0 * factor;
1419
1420 dev_dbg(dev, "%s, write LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1421
1422 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1423 rt1320_fw_param_protocol(rt1320, RT1320_SET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1424 if (rt1320_check_fw_ready(rt1320) < 0)
1425 dev_err(dev, "%s: Failed to set FW param 3,4!\n", __func__);
1426
1427 rt1320->temp_l_calib = l_t0;
1428 rt1320->temp_r_calib = r_t0;
1429
1430 memset(&l_t0_data[0], 0x00, sizeof(l_t0_data));
1431 memset(&r_t0_data[0], 0x00, sizeof(r_t0_data));
1432 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 3, &l_t0_data[0], sizeof(l_t0_data));
1433 rt1320_fw_param_protocol(rt1320, RT1320_GET_PARAM, 4, &r_t0_data[0], sizeof(r_t0_data));
1434 dev_dbg(dev, "%s, read after writing LR t0=0x%x, 0x%x\n", __func__, l_t0_data[37], r_t0_data[37]);
1435
1436 _exit_:
1437 regmap_write(rt1320->regmap,
1438 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1439 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1440 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1441 }
1442
rt1320_rae_load(struct rt1320_sdw_priv * rt1320)1443 static int rt1320_rae_load(struct rt1320_sdw_priv *rt1320)
1444 {
1445 struct device *dev = &rt1320->sdw_slave->dev;
1446 static const char func_tag[] = "FUNC";
1447 static const char xu_tag[] = "XU";
1448 const struct firmware *rae_fw = NULL;
1449 unsigned int fw_offset;
1450 unsigned char *fw_data;
1451 unsigned char *param_data;
1452 unsigned int addr, size;
1453 unsigned int func, value;
1454 const char *dmi_vendor, *dmi_product, *dmi_sku;
1455 int len_vendor, len_product, len_sku;
1456 char rae_filename[512];
1457 char tag[5];
1458 int ret = 0;
1459 int retry = 200;
1460
1461 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1462 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
1463 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
1464
1465 if (dmi_vendor && dmi_product && dmi_sku) {
1466 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
1467 len_product = strchrnul(dmi_product, ' ') - dmi_product;
1468 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
1469
1470 snprintf(rae_filename, sizeof(rae_filename),
1471 "realtek/rt1320/rt1320_RAE_%.*s_%.*s_%.*s.dat",
1472 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
1473 dev_dbg(dev, "%s: try to load RAE file %s\n", __func__, rae_filename);
1474 } else {
1475 dev_warn(dev, "%s: Can't find proper RAE file name\n", __func__);
1476 return -EINVAL;
1477 }
1478
1479 regmap_write(rt1320->regmap,
1480 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1481 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1482 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1483
1484 request_firmware(&rae_fw, rae_filename, dev);
1485 if (rae_fw) {
1486
1487 /* RAE CRC clear */
1488 regmap_write(rt1320->regmap, 0xe80b, 0x0f);
1489
1490 /* RAE stop & CRC disable */
1491 regmap_update_bits(rt1320->regmap, 0xe803, 0xbc, 0x00);
1492
1493 while (--retry) {
1494 regmap_read(rt1320->regmap, 0xe83f, &value);
1495 if (value & 0x40)
1496 break;
1497 usleep_range(1000, 1100);
1498 }
1499 if (!retry && !(value & 0x40)) {
1500 dev_err(dev, "%s: RAE is not ready to load\n", __func__);
1501 release_firmware(rae_fw);
1502 return -ETIMEDOUT;
1503 }
1504
1505 dev_dbg(dev, "%s, rae_fw size=0x%zx\n", __func__, rae_fw->size);
1506 regcache_cache_bypass(rt1320->regmap, true);
1507 for (fw_offset = 0; fw_offset < rae_fw->size;) {
1508
1509 dev_dbg(dev, "%s, fw_offset=0x%x\n", __func__, fw_offset);
1510
1511 fw_data = (unsigned char *)&rae_fw->data[fw_offset];
1512
1513 memcpy(tag, fw_data, 4);
1514 tag[4] = '\0';
1515 dev_dbg(dev, "%s, tag=%s\n", __func__, tag);
1516 if (strcmp(tag, xu_tag) == 0) {
1517 dev_dbg(dev, "%s: This is a XU tag", __func__);
1518 memcpy(&addr, (fw_data + 4), 4);
1519 memcpy(&size, (fw_data + 8), 4);
1520 param_data = (unsigned char *)(fw_data + 12);
1521
1522 dev_dbg(dev, "%s: addr=0x%x, size=0x%x\n", __func__, addr, size);
1523
1524 /*
1525 * UI register ranges from 0x1000d000 to 0x1000d7ff
1526 * UI registers should be accessed by tuning tool.
1527 * So, there registers should be cached.
1528 */
1529 if (addr <= 0x1000d7ff && addr >= 0x1000d000)
1530 regcache_cache_bypass(rt1320->regmap, false);
1531
1532 rt1320_data_rw(rt1320, addr, param_data, size, RT1320_PARAM_WRITE);
1533
1534 regcache_cache_bypass(rt1320->regmap, true);
1535
1536 fw_offset += (size + 12);
1537 } else if (strcmp(tag, func_tag) == 0) {
1538 dev_err(dev, "%s: This is a FUNC tag", __func__);
1539
1540 memcpy(&func, (fw_data + 4), 4);
1541 memcpy(&value, (fw_data + 8), 4);
1542
1543 dev_dbg(dev, "%s: func=0x%x, value=0x%x\n", __func__, func, value);
1544 if (func == 1) //DelayMs
1545 msleep(value);
1546
1547 fw_offset += 12;
1548 } else {
1549 dev_err(dev, "%s: This is NOT a XU file (wrong tag)", __func__);
1550 break;
1551 }
1552 }
1553
1554 regcache_cache_bypass(rt1320->regmap, false);
1555 release_firmware(rae_fw);
1556
1557 } else {
1558 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, rae_filename);
1559 ret = -EINVAL;
1560 goto _exit_;
1561 }
1562
1563 /* RAE CRC enable */
1564 regmap_update_bits(rt1320->regmap, 0xe803, 0x0c, 0x0c);
1565
1566 /* RAE update */
1567 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x00);
1568 regmap_update_bits(rt1320->regmap, 0xe80b, 0x80, 0x80);
1569
1570 /* RAE run */
1571 regmap_update_bits(rt1320->regmap, 0xe803, 0x80, 0x80);
1572
1573 regmap_read(rt1320->regmap, 0xe80b, &value);
1574 dev_dbg(dev, "%s: CAE run => 0xe80b reg = 0x%x\n", __func__, value);
1575
1576 rt1320->rae_update_done = true;
1577
1578 _exit_:
1579 regmap_write(rt1320->regmap,
1580 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1581 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1582 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1583
1584 return ret;
1585 }
1586
rt1320_dspfw_load_code(struct rt1320_sdw_priv * rt1320)1587 static void rt1320_dspfw_load_code(struct rt1320_sdw_priv *rt1320)
1588 {
1589 struct rt1320_imageinfo {
1590 unsigned int addr;
1591 unsigned int size;
1592 };
1593
1594 struct rt1320_dspfwheader {
1595 unsigned int sync;
1596 short num;
1597 short crc;
1598 };
1599
1600 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
1601 struct device *dev = &rt1320->sdw_slave->dev;
1602 unsigned int val, i, fw_offset, fw_ready;
1603 unsigned int fw_status_addr;
1604 struct rt1320_dspfwheader *fwheader;
1605 struct rt1320_imageinfo *ptr_img;
1606 struct sdw_bpt_section sec[10];
1607 const struct firmware *fw = NULL;
1608 unsigned char *fw_data;
1609 bool dev_fw_match = false;
1610 static const char hdr_sig[] = "AFX";
1611 unsigned int hdr_size = 0;
1612 const char *dmi_vendor, *dmi_product, *dmi_sku;
1613 int len_vendor, len_product, len_sku;
1614 char filename[512];
1615
1616 switch (rt1320->dev_id) {
1617 case RT1320_DEV_ID:
1618 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
1619 break;
1620 case RT1321_DEV_ID:
1621 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
1622 break;
1623 default:
1624 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1625 return;
1626 }
1627
1628 dmi_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1629 dmi_product = dmi_get_system_info(DMI_PRODUCT_NAME);
1630 dmi_sku = dmi_get_system_info(DMI_PRODUCT_SKU);
1631
1632 if (dmi_vendor && dmi_product && dmi_sku) {
1633 len_vendor = strchrnul(dmi_vendor, ' ') - dmi_vendor;
1634 len_product = strchrnul(dmi_product, ' ') - dmi_product;
1635 len_sku = strchrnul(dmi_sku, ' ') - dmi_sku;
1636
1637 snprintf(filename, sizeof(filename),
1638 "realtek/rt1320/rt1320_%.*s_%.*s_%.*s.dat",
1639 len_vendor, dmi_vendor, len_product, dmi_product, len_sku, dmi_sku);
1640
1641 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
1642 } else if (rt1320->dspfw_name) {
1643 snprintf(filename, sizeof(filename), "rt1320_%s.dat",
1644 rt1320->dspfw_name);
1645 dev_dbg(dev, "%s: try to load FW file %s\n", __func__, filename);
1646 } else {
1647 dev_warn(dev, "%s: Can't find proper FW file name\n", __func__);
1648 return;
1649 }
1650
1651 snd_soc_dapm_mutex_lock(dapm);
1652 regmap_write(rt1320->regmap,
1653 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1654 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
1655 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
1656
1657 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
1658 fw_ready &= 0x1;
1659 if (fw_ready) {
1660 dev_dbg(dev, "%s, DSP FW was already\n", __func__);
1661 rt1320->fw_load_done = true;
1662 goto _exit_;
1663 }
1664
1665 /* change to IRAM */
1666 regmap_update_bits(rt1320->regmap, 0xf01e, 0x80, 0x00);
1667
1668 request_firmware(&fw, filename, dev);
1669 if (fw) {
1670 fwheader = (struct rt1320_dspfwheader *)fw->data;
1671 dev_dbg(dev, "%s, fw sync = 0x%x, num=%d, crc=0x%x\n", __func__,
1672 fwheader->sync, fwheader->num, fwheader->crc);
1673
1674 if (fwheader->sync != 0x0a1c5679) {
1675 dev_err(dev, "%s: FW sync error\n", __func__);
1676 release_firmware(fw);
1677 goto _exit_;
1678 }
1679
1680 fw_offset = sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * fwheader->num);
1681 dev_dbg(dev, "%s, fw_offset = 0x%x\n", __func__, fw_offset);
1682
1683 regcache_cache_bypass(rt1320->regmap, true);
1684
1685 for (i = 0; i < fwheader->num; i++) {
1686 ptr_img = (struct rt1320_imageinfo *)&fw->data[sizeof(struct rt1320_dspfwheader) + (sizeof(struct rt1320_imageinfo) * i)];
1687
1688 dev_dbg(dev, "%s, fw_offset=0x%x, load fw addr=0x%x, size=%d\n", __func__,
1689 fw_offset, ptr_img->addr, ptr_img->size);
1690
1691 fw_data = (unsigned char *)&fw->data[fw_offset];
1692
1693 /* The binary file has a header of 64 bytes */
1694 if (memcmp(fw_data, hdr_sig, sizeof(hdr_sig)) == 0)
1695 hdr_size = 64;
1696 else
1697 hdr_size = 0;
1698
1699 sec[i].addr = ptr_img->addr;
1700 sec[i].len = ptr_img->size - hdr_size;
1701 sec[i].buf = fw_data + hdr_size;
1702
1703 dev_dbg(dev, "%s, hdr_size=%d, sec[%d].buf[0]=0x%x\n",
1704 __func__, hdr_size, i, sec[i].buf[0]);
1705
1706 switch (rt1320->dev_id) {
1707 case RT1320_DEV_ID:
1708 if (ptr_img->addr == 0x3fc29d80)
1709 if (fw_data[9] == '0')
1710 dev_fw_match = true;
1711 break;
1712 case RT1321_DEV_ID:
1713 if (ptr_img->addr == 0x3fc00000)
1714 if (fw_data[9] == '1')
1715 dev_fw_match = true;
1716 break;
1717 default:
1718 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1719 goto _exit_;
1720 }
1721
1722 fw_offset += ptr_img->size;
1723 }
1724
1725 if (dev_fw_match) {
1726 dev_dbg(dev, "%s, starting BRA downloading FW..\n", __func__);
1727 rt1320->bra_msg.dev_num = rt1320->sdw_slave->dev_num;
1728 rt1320->bra_msg.flags = SDW_MSG_FLAG_WRITE;
1729 rt1320->bra_msg.sections = fwheader->num;
1730 rt1320->bra_msg.sec = &sec[0];
1731 rt1320_data_rw(rt1320, 0, NULL, 0, RT1320_BRA_WRITE);
1732 dev_dbg(dev, "%s, BRA downloading FW done..\n", __func__);
1733 }
1734
1735 regcache_cache_bypass(rt1320->regmap, false);
1736 release_firmware(fw);
1737
1738 if (!dev_fw_match) {
1739 dev_err(dev, "%s: FW file doesn't match to device\n", __func__);
1740 goto _exit_;
1741 }
1742 } else {
1743 dev_err(dev, "%s: Failed to load %s firmware\n", __func__, filename);
1744 goto _exit_;
1745 }
1746
1747 /* run RAM code */
1748 regmap_read(rt1320->regmap, 0x3fc2bfc0, &val);
1749 val |= 0x8;
1750 regmap_write(rt1320->regmap, 0x3fc2bfc0, val);
1751
1752 /* clear frame counter */
1753 switch (rt1320->dev_id) {
1754 case RT1320_DEV_ID:
1755 regmap_write(rt1320->regmap, 0x3fc2bfcb, 0x00);
1756 regmap_write(rt1320->regmap, 0x3fc2bfca, 0x00);
1757 regmap_write(rt1320->regmap, 0x3fc2bfc9, 0x00);
1758 regmap_write(rt1320->regmap, 0x3fc2bfc8, 0x00);
1759 break;
1760 case RT1321_DEV_ID:
1761 regmap_write(rt1320->regmap, 0x3fc2dfcb, 0x00);
1762 regmap_write(rt1320->regmap, 0x3fc2dfca, 0x00);
1763 regmap_write(rt1320->regmap, 0x3fc2dfc9, 0x00);
1764 regmap_write(rt1320->regmap, 0x3fc2dfc8, 0x00);
1765 break;
1766 }
1767
1768 /* enable DSP FW */
1769 regmap_write(rt1320->regmap, 0xc081, 0xfc);
1770 regmap_update_bits(rt1320->regmap, 0xf01e, 0x1, 0x0);
1771
1772 /* RsRatio should restore into DSP FW when FW was ready */
1773 rt1320_invrs_load(rt1320);
1774
1775 /* DSP clock switches to PLL */
1776 regmap_write(rt1320->regmap, 0xc081, 0xfc);
1777 /* pass DSP settings */
1778 regmap_write(rt1320->regmap, 0xc5c3, 0xf3);
1779 regmap_write(rt1320->regmap, 0xc5c8, 0x05);
1780
1781 rt1320->fw_load_done = true;
1782
1783 pm_runtime_set_autosuspend_delay(dev, 3000);
1784 pm_runtime_mark_last_busy(dev);
1785
1786 _exit_:
1787 regmap_write(rt1320->regmap,
1788 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1789 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
1790 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
1791
1792 snd_soc_dapm_mutex_unlock(dapm);
1793 }
1794
rt1320_load_dspfw_work(struct work_struct * work)1795 static void rt1320_load_dspfw_work(struct work_struct *work)
1796 {
1797 struct rt1320_sdw_priv *rt1320 =
1798 container_of(work, struct rt1320_sdw_priv, load_dspfw_work);
1799 int ret;
1800
1801 ret = pm_runtime_resume(rt1320->component->dev);
1802 if (ret < 0 && ret != -EACCES)
1803 return;
1804
1805 dev_dbg(&rt1320->sdw_slave->dev, "%s, Starting to reload DSP FW", __func__);
1806 rt1320_dspfw_load_code(rt1320);
1807 }
1808
rt1320_vc_preset(struct rt1320_sdw_priv * rt1320)1809 static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320)
1810 {
1811 struct sdw_slave *slave = rt1320->sdw_slave;
1812 unsigned int i, reg, val, delay, retry, tmp;
1813
1814 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) {
1815 reg = rt1320_vc_blind_write[i].reg;
1816 val = rt1320_vc_blind_write[i].def;
1817 delay = rt1320_vc_blind_write[i].delay_us;
1818
1819 if (reg == 0x3fc2bf83)
1820 rt1320_load_mcu_patch(rt1320);
1821
1822 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) &&
1823 (val == 0x00)) {
1824 retry = 200;
1825 while (retry) {
1826 regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp);
1827 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp);
1828 if (tmp == 0x1f)
1829 break;
1830 usleep_range(1000, 1500);
1831 retry--;
1832 }
1833 if (!retry)
1834 dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__);
1835 }
1836 regmap_write(rt1320->regmap, reg, val);
1837 if (delay)
1838 usleep_range(delay, delay + 1000);
1839
1840 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
1841 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
1842 }
1843 }
1844
rt1321_preset(struct rt1320_sdw_priv * rt1320)1845 static void rt1321_preset(struct rt1320_sdw_priv *rt1320)
1846 {
1847 unsigned int i, reg, val, delay;
1848
1849 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) {
1850 reg = rt1321_blind_write[i].reg;
1851 val = rt1321_blind_write[i].def;
1852 delay = rt1321_blind_write[i].delay_us;
1853
1854 if (reg == 0x3fc2dfc3)
1855 rt1320_load_mcu_patch(rt1320);
1856
1857 regmap_write(rt1320->regmap, reg, val);
1858
1859 if (delay)
1860 usleep_range(delay, delay + 1000);
1861
1862 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
1863 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
1864 }
1865 }
1866
rt1320_io_init(struct device * dev,struct sdw_slave * slave)1867 static int rt1320_io_init(struct device *dev, struct sdw_slave *slave)
1868 {
1869 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
1870 unsigned int amp_func_status, val, tmp;
1871
1872 if (rt1320->hw_init)
1873 return 0;
1874
1875 regcache_cache_only(rt1320->regmap, false);
1876 regcache_cache_only(rt1320->mbq_regmap, false);
1877 if (rt1320->first_hw_init) {
1878 regcache_cache_bypass(rt1320->regmap, true);
1879 regcache_cache_bypass(rt1320->mbq_regmap, true);
1880 } else {
1881 /*
1882 * PM runtime status is marked as 'active' only when a Slave reports as Attached
1883 */
1884 /* update count of parent 'active' children */
1885 pm_runtime_set_active(&slave->dev);
1886 }
1887
1888 pm_runtime_get_noresume(&slave->dev);
1889
1890 if (rt1320->version_id < 0) {
1891 regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val);
1892 rt1320->version_id = val;
1893 regmap_read(rt1320->regmap, RT1320_DEV_ID_0, &val);
1894 regmap_read(rt1320->regmap, RT1320_DEV_ID_1, &tmp);
1895 rt1320->dev_id = (val << 8) | tmp;
1896 }
1897
1898 regmap_read(rt1320->regmap,
1899 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
1900 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
1901
1902 /* initialization write */
1903 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) {
1904 switch (rt1320->dev_id) {
1905 case RT1320_DEV_ID:
1906 if (rt1320->version_id < RT1320_VC)
1907 rt1320_vab_preset(rt1320);
1908 else
1909 rt1320_vc_preset(rt1320);
1910 break;
1911 case RT1321_DEV_ID:
1912 rt1321_preset(rt1320);
1913 break;
1914 default:
1915 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
1916 }
1917
1918 regmap_write(rt1320->regmap,
1919 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
1920 FUNCTION_NEEDS_INITIALIZATION);
1921
1922 /* reload DSP FW */
1923 if (rt1320->fw_load_done)
1924 schedule_work(&rt1320->load_dspfw_work);
1925 }
1926 if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA && rt1320->dev_id == RT1320_DEV_ID) {
1927 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1928 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
1929 regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val);
1930 regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp);
1931 val = (tmp << 8) | val;
1932 regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp);
1933 val = (tmp << 16) | val;
1934 regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp);
1935 val = (tmp << 24) | val;
1936 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
1937 /*
1938 * We call the version b which has the new DSP ROM code against version a.
1939 * Therefore, we read the DSP address to check the ID.
1940 */
1941 if (val == RT1320_VER_B_ID)
1942 rt1320->version_id = RT1320_VB;
1943 regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1944 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
1945 }
1946 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id);
1947
1948 if (rt1320->first_hw_init) {
1949 regcache_cache_bypass(rt1320->regmap, false);
1950 regcache_cache_bypass(rt1320->mbq_regmap, false);
1951 regcache_mark_dirty(rt1320->regmap);
1952 regcache_mark_dirty(rt1320->mbq_regmap);
1953 }
1954
1955 /* Mark Slave initialization complete */
1956 rt1320->first_hw_init = true;
1957 rt1320->hw_init = true;
1958
1959 pm_runtime_put_autosuspend(&slave->dev);
1960
1961 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1962 return 0;
1963 }
1964
rt1320_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1965 static int rt1320_update_status(struct sdw_slave *slave,
1966 enum sdw_slave_status status)
1967 {
1968 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
1969
1970 if (status == SDW_SLAVE_UNATTACHED)
1971 rt1320->hw_init = false;
1972
1973 /*
1974 * Perform initialization only if slave status is present and
1975 * hw_init flag is false
1976 */
1977 if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED)
1978 return 0;
1979
1980 /* perform I/O transfers required for Slave initialization */
1981 return rt1320_io_init(&slave->dev, slave);
1982 }
1983
rt1320_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1984 static int rt1320_pde11_event(struct snd_soc_dapm_widget *w,
1985 struct snd_kcontrol *kcontrol, int event)
1986 {
1987 struct snd_soc_component *component =
1988 snd_soc_dapm_to_component(w->dapm);
1989 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1990 unsigned char ps0 = 0x0, ps3 = 0x3;
1991
1992 switch (event) {
1993 case SND_SOC_DAPM_POST_PMU:
1994 regmap_write(rt1320->regmap,
1995 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
1996 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1997 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0);
1998 break;
1999 case SND_SOC_DAPM_PRE_PMD:
2000 regmap_write(rt1320->regmap,
2001 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
2002 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
2003 rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3);
2004 break;
2005 default:
2006 break;
2007 }
2008
2009 return 0;
2010 }
2011
rt1320_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2012 static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
2013 struct snd_kcontrol *kcontrol, int event)
2014 {
2015 struct snd_soc_component *component =
2016 snd_soc_dapm_to_component(w->dapm);
2017 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2018 unsigned char ps0 = 0x0, ps3 = 0x3;
2019
2020 switch (event) {
2021 case SND_SOC_DAPM_POST_PMU:
2022 regmap_write(rt1320->regmap,
2023 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2024 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
2025 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0);
2026 break;
2027 case SND_SOC_DAPM_PRE_PMD:
2028 regmap_write(rt1320->regmap,
2029 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
2030 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
2031 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3);
2032 break;
2033 default:
2034 break;
2035 }
2036
2037 return 0;
2038 }
2039
rt1320_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2040 static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol,
2041 struct snd_ctl_elem_value *ucontrol)
2042 {
2043 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2044 struct soc_mixer_control *mc =
2045 (struct soc_mixer_control *)kcontrol->private_value;
2046 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2047 unsigned int gain_l_val, gain_r_val;
2048 unsigned int lvalue, rvalue;
2049 const unsigned int interval_offset = 0xc0;
2050 unsigned int changed = 0, reg_base;
2051 struct rt_sdca_dmic_kctrl_priv *p;
2052 unsigned int regvalue[4], gain_val[4], i;
2053 int err;
2054
2055 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2056 goto _dmic_vol_;
2057
2058 regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
2059 regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
2060
2061 /* L Channel */
2062 gain_l_val = ucontrol->value.integer.value[0];
2063 if (gain_l_val > mc->max)
2064 gain_l_val = mc->max;
2065 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
2066 gain_l_val &= 0xffff;
2067
2068 /* R Channel */
2069 gain_r_val = ucontrol->value.integer.value[1];
2070 if (gain_r_val > mc->max)
2071 gain_r_val = mc->max;
2072 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
2073 gain_r_val &= 0xffff;
2074
2075 if (lvalue == gain_l_val && rvalue == gain_r_val)
2076 return 0;
2077
2078 /* Lch*/
2079 regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
2080 /* Rch */
2081 regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
2082 goto _done_;
2083
2084 _dmic_vol_:
2085 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2086
2087 /* check all channels */
2088 for (i = 0; i < p->count; i++) {
2089 switch (rt1320->dev_id) {
2090 case RT1320_DEV_ID:
2091 if (i < 2) {
2092 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2093 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2094 } else {
2095 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2096 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]);
2097 }
2098 break;
2099 case RT1321_DEV_ID:
2100 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2101 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
2102 break;
2103 }
2104
2105 gain_val[i] = ucontrol->value.integer.value[i];
2106 if (gain_val[i] > p->max)
2107 gain_val[i] = p->max;
2108
2109 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
2110 gain_val[i] &= 0xffff;
2111 if (regvalue[i] != gain_val[i])
2112 changed = 1;
2113 }
2114
2115 if (!changed)
2116 return 0;
2117
2118 for (i = 0; i < p->count; i++) {
2119 switch (rt1320->dev_id) {
2120 case RT1320_DEV_ID:
2121 if (i < 2) {
2122 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2123 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2124 } else {
2125 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2126 err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]);
2127 }
2128 break;
2129 case RT1321_DEV_ID:
2130 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2131 err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
2132 break;
2133 }
2134
2135 if (err < 0)
2136 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
2137 }
2138
2139 _done_:
2140 return 1;
2141 }
2142
rt1320_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2143 static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol,
2144 struct snd_ctl_elem_value *ucontrol)
2145 {
2146 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2147 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2148 struct soc_mixer_control *mc =
2149 (struct soc_mixer_control *)kcontrol->private_value;
2150 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
2151 const unsigned int interval_offset = 0xc0;
2152 unsigned int reg_base, regvalue, ctl, i;
2153 struct rt_sdca_dmic_kctrl_priv *p;
2154
2155 if (strstr(ucontrol->id.name, "FU Capture Volume"))
2156 goto _dmic_vol_;
2157
2158 regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
2159 regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
2160
2161 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
2162
2163 if (read_l != read_r)
2164 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
2165 else
2166 ctl_r = ctl_l;
2167
2168 ucontrol->value.integer.value[0] = ctl_l;
2169 ucontrol->value.integer.value[1] = ctl_r;
2170 goto _done_;
2171
2172 _dmic_vol_:
2173 p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2174
2175 /* check all channels */
2176 for (i = 0; i < p->count; i++) {
2177 switch (rt1320->dev_id) {
2178 case RT1320_DEV_ID:
2179 if (i < 2) {
2180 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2181 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2182 } else {
2183 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2184 regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value);
2185 }
2186 break;
2187 case RT1321_DEV_ID:
2188 reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
2189 regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
2190 break;
2191 }
2192
2193 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
2194 ucontrol->value.integer.value[i] = ctl;
2195 }
2196 _done_:
2197 return 0;
2198 }
2199
rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv * rt1320)2200 static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320)
2201 {
2202 int err, i;
2203 unsigned int ch_mute;
2204
2205 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
2206 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
2207
2208 switch (rt1320->dev_id) {
2209 case RT1320_DEV_ID:
2210 if (i < 2)
2211 err = regmap_write(rt1320->regmap,
2212 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2213 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2214 else
2215 err = regmap_write(rt1320->regmap,
2216 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14,
2217 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute);
2218 break;
2219 case RT1321_DEV_ID:
2220 err = regmap_write(rt1320->regmap,
2221 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
2222 RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
2223 break;
2224 default:
2225 dev_err(&rt1320->sdw_slave->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2226 return -EINVAL;
2227 }
2228 if (err < 0)
2229 return err;
2230 }
2231
2232 return 0;
2233 }
2234
rt1320_dmic_fu_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2235 static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol,
2236 struct snd_ctl_elem_value *ucontrol)
2237 {
2238 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2239 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2240 struct rt_sdca_dmic_kctrl_priv *p =
2241 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2242 unsigned int i;
2243
2244 for (i = 0; i < p->count; i++)
2245 ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i];
2246
2247 return 0;
2248 }
2249
rt1320_dmic_fu_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2250 static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol,
2251 struct snd_ctl_elem_value *ucontrol)
2252 {
2253 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2254 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2255 struct rt_sdca_dmic_kctrl_priv *p =
2256 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2257 int err, changed = 0, i;
2258
2259 for (i = 0; i < p->count; i++) {
2260 if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i])
2261 changed = 1;
2262 rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i];
2263 }
2264
2265 err = rt1320_set_fu_capture_ctl(rt1320);
2266 if (err < 0)
2267 return err;
2268
2269 return changed;
2270 }
2271
rt1320_dmic_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2272 static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol,
2273 struct snd_ctl_elem_info *uinfo)
2274 {
2275 struct rt_sdca_dmic_kctrl_priv *p =
2276 (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
2277
2278 if (p->max == 1)
2279 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2280 else
2281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2282 uinfo->count = p->count;
2283 uinfo->value.integer.min = 0;
2284 uinfo->value.integer.max = p->max;
2285 return 0;
2286 }
2287
rt1320_dmic_fu_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2288 static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w,
2289 struct snd_kcontrol *kcontrol, int event)
2290 {
2291 struct snd_soc_component *component =
2292 snd_soc_dapm_to_component(w->dapm);
2293 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2294
2295 switch (event) {
2296 case SND_SOC_DAPM_POST_PMU:
2297 rt1320->fu_dapm_mute = false;
2298 rt1320_set_fu_capture_ctl(rt1320);
2299 break;
2300 case SND_SOC_DAPM_PRE_PMD:
2301 rt1320->fu_dapm_mute = true;
2302 rt1320_set_fu_capture_ctl(rt1320);
2303 break;
2304 }
2305 return 0;
2306 }
2307
2308 static const char * const rt1320_rx_data_ch_select[] = {
2309 "L,R",
2310 "R,L",
2311 "L,L",
2312 "R,R",
2313 "L,L+R",
2314 "R,L+R",
2315 "L+R,L",
2316 "L+R,R",
2317 "L+R,L+R",
2318 };
2319
2320 static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum,
2321 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
2322 rt1320_rx_data_ch_select);
2323
2324 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
2325 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
2326
rt1320_r0_load(struct rt1320_sdw_priv * rt1320)2327 static int rt1320_r0_load(struct rt1320_sdw_priv *rt1320)
2328 {
2329 struct device *dev = regmap_get_device(rt1320->regmap);
2330 unsigned int fw_status_addr;
2331 unsigned int fw_ready;
2332 int ret = 0;
2333
2334 if (!rt1320->r0_l_reg || !rt1320->r0_r_reg)
2335 return -EINVAL;
2336
2337 switch (rt1320->dev_id) {
2338 case RT1320_DEV_ID:
2339 fw_status_addr = RT1320_DSPFW_STATUS_ADDR;
2340 break;
2341 case RT1321_DEV_ID:
2342 fw_status_addr = RT1321_DSPFW_STATUS_ADDR;
2343 break;
2344 default:
2345 dev_err(dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2346 return -EINVAL;
2347 }
2348
2349 regmap_write(rt1320->regmap,
2350 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00);
2351 ret = rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x00);
2352 if (ret < 0) {
2353 dev_dbg(dev, "%s, PDE=PS0 is NOT ready\n", __func__);
2354 goto _timeout_;
2355 }
2356
2357 regmap_read(rt1320->regmap, fw_status_addr, &fw_ready);
2358 fw_ready &= 0x1;
2359 if (!fw_ready) {
2360 dev_dbg(dev, "%s, DSP FW is NOT ready\n", __func__);
2361 goto _timeout_;
2362 }
2363
2364 ret = rt1320_check_power_state_ready(rt1320, RT1320_NORMAL_STATE);
2365 if (ret < 0) {
2366 dev_dbg(dev, "%s, DSP FW PS is NOT ready\n", __func__);
2367 goto _timeout_;
2368 }
2369
2370 rt1320_set_advancemode(rt1320);
2371
2372 _timeout_:
2373 regmap_write(rt1320->regmap,
2374 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03);
2375 rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, 0x03);
2376
2377 return ret;
2378 }
2379
rt1320_r0_load_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2380 static int rt1320_r0_load_mode_get(struct snd_kcontrol *kcontrol,
2381 struct snd_ctl_elem_value *ucontrol)
2382 {
2383 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2384 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2385
2386 ucontrol->value.integer.value[0] = rt1320->r0_l_reg;
2387 ucontrol->value.integer.value[1] = rt1320->r0_r_reg;
2388
2389 return 0;
2390 }
2391
rt1320_r0_load_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2392 static int rt1320_r0_load_mode_put(struct snd_kcontrol *kcontrol,
2393 struct snd_ctl_elem_value *ucontrol)
2394 {
2395 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2396 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2397 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2398 int ret;
2399
2400 if (!rt1320->hw_init)
2401 return 0;
2402
2403 if (ucontrol->value.integer.value[0] == 0 ||
2404 ucontrol->value.integer.value[1] == 0)
2405 return -EINVAL;
2406
2407 ret = pm_runtime_resume(component->dev);
2408 if (ret < 0 && ret != -EACCES)
2409 return ret;
2410
2411 snd_soc_dapm_mutex_lock(dapm);
2412 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
2413 rt1320->r0_l_reg = ucontrol->value.integer.value[0];
2414 rt1320->r0_r_reg = ucontrol->value.integer.value[1];
2415 rt1320_calc_r0(rt1320);
2416 rt1320_r0_load(rt1320);
2417 }
2418 snd_soc_dapm_mutex_unlock(dapm);
2419
2420 return 0;
2421 }
2422
rt1320_t0_r0_load_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)2423 static int rt1320_t0_r0_load_info(struct snd_kcontrol *kcontrol,
2424 struct snd_ctl_elem_info *uinfo)
2425 {
2426 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2427 uinfo->count = 2;
2428 uinfo->value.integer.max = kcontrol->private_value;
2429
2430 return 0;
2431 }
2432
2433 #define RT1320_T0_R0_LOAD(xname, xmax, xhandler_get, xhandler_put) \
2434 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2435 .info = rt1320_t0_r0_load_info, \
2436 .get = xhandler_get, \
2437 .put = xhandler_put, \
2438 .private_value = xmax, \
2439 }
2440
rt1320_dspfw_load_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2441 static int rt1320_dspfw_load_get(struct snd_kcontrol *kcontrol,
2442 struct snd_ctl_elem_value *ucontrol)
2443 {
2444 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2445 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2446
2447 ucontrol->value.integer.value[0] = rt1320->fw_load_done;
2448 return 0;
2449 }
2450
rt1320_dspfw_load_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2451 static int rt1320_dspfw_load_put(struct snd_kcontrol *kcontrol,
2452 struct snd_ctl_elem_value *ucontrol)
2453 {
2454 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2455 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2456 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2457 int ret;
2458
2459 if (!rt1320->hw_init)
2460 return 0;
2461
2462 ret = pm_runtime_resume(component->dev);
2463 if (ret < 0 && ret != -EACCES)
2464 return ret;
2465
2466 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
2467 ucontrol->value.integer.value[0])
2468 rt1320_dspfw_load_code(rt1320);
2469
2470 if (!ucontrol->value.integer.value[0])
2471 rt1320->fw_load_done = false;
2472
2473 return 0;
2474 }
2475
rt1320_rae_update_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2476 static int rt1320_rae_update_get(struct snd_kcontrol *kcontrol,
2477 struct snd_ctl_elem_value *ucontrol)
2478 {
2479 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2480 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2481
2482 ucontrol->value.integer.value[0] = rt1320->rae_update_done;
2483 return 0;
2484 }
2485
rt1320_rae_update_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2486 static int rt1320_rae_update_put(struct snd_kcontrol *kcontrol,
2487 struct snd_ctl_elem_value *ucontrol)
2488 {
2489 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2490 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2491 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2492 int ret;
2493
2494 if (!rt1320->hw_init)
2495 return 0;
2496
2497 ret = pm_runtime_resume(component->dev);
2498 if (ret < 0 && ret != -EACCES)
2499 return ret;
2500
2501 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF &&
2502 ucontrol->value.integer.value[0] && rt1320->fw_load_done)
2503 rt1320_rae_load(rt1320);
2504
2505 if (!ucontrol->value.integer.value[0])
2506 rt1320->rae_update_done = false;
2507
2508 return 0;
2509 }
2510
rt1320_brown_out_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2511 static int rt1320_brown_out_put(struct snd_kcontrol *kcontrol,
2512 struct snd_ctl_elem_value *ucontrol)
2513 {
2514 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2515 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2516 int ret, changed = 0;
2517
2518 if (!rt1320->hw_init)
2519 return 0;
2520
2521 ret = pm_runtime_resume(component->dev);
2522 if (ret < 0 && ret != -EACCES)
2523 return ret;
2524
2525 if (rt1320->brown_out != ucontrol->value.integer.value[0]) {
2526 changed = 1;
2527 rt1320->brown_out = ucontrol->value.integer.value[0];
2528 }
2529
2530 if (rt1320->brown_out == 0)
2531 regmap_write(rt1320->regmap, 0xdb03, 0x00);
2532 else
2533 regmap_write(rt1320->regmap, 0xdb03, 0xf0);
2534
2535
2536 return changed;
2537 }
2538
rt1320_brown_out_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2539 static int rt1320_brown_out_get(struct snd_kcontrol *kcontrol,
2540 struct snd_ctl_elem_value *ucontrol)
2541 {
2542 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2543 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2544
2545 ucontrol->value.integer.value[0] = rt1320->brown_out;
2546
2547 return 0;
2548 }
2549
rt1320_r0_temperature_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2550 static int rt1320_r0_temperature_get(struct snd_kcontrol *kcontrol,
2551 struct snd_ctl_elem_value *ucontrol)
2552 {
2553 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2554 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2555
2556 ucontrol->value.integer.value[0] = rt1320->temp_l_calib;
2557 ucontrol->value.integer.value[1] = rt1320->temp_r_calib;
2558 return 0;
2559 }
2560
rt1320_r0_temperature_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2561 static int rt1320_r0_temperature_put(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_value *ucontrol)
2563 {
2564 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
2565 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2566 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(rt1320->component);
2567 int ret;
2568
2569 if (!rt1320->hw_init)
2570 return 0;
2571
2572 ret = pm_runtime_resume(component->dev);
2573 if (ret < 0 && ret != -EACCES)
2574 return ret;
2575
2576 snd_soc_dapm_mutex_lock(dapm);
2577 if ((snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) &&
2578 ucontrol->value.integer.value[0] && ucontrol->value.integer.value[1])
2579 rt1320_t0_load(rt1320, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1]);
2580 snd_soc_dapm_mutex_unlock(dapm);
2581
2582 return 0;
2583 }
2584
2585 static const struct snd_kcontrol_new rt1320_snd_controls[] = {
2586 SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
2587 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
2588 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
2589 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
2590 SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
2591
2592 RT_SDCA_FU_CTRL("FU Capture Switch",
2593 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01),
2594 1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put),
2595 RT_SDCA_EXT_TLV("FU Capture Volume",
2596 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
2597 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
2598
2599 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
2600 rt1320_r0_cali_get, rt1320_r0_cali_put),
2601 SOC_SINGLE_EXT("DSP FW Update", SND_SOC_NOPM, 0, 1, 0,
2602 rt1320_dspfw_load_get, rt1320_dspfw_load_put),
2603 RT1320_T0_R0_LOAD("R0 Load Mode", 0xffffffff,
2604 rt1320_r0_load_mode_get, rt1320_r0_load_mode_put),
2605 RT1320_T0_R0_LOAD("R0 Temperature", 0xff,
2606 rt1320_r0_temperature_get, rt1320_r0_temperature_put),
2607 SOC_SINGLE_EXT("RAE Update", SND_SOC_NOPM, 0, 1, 0,
2608 rt1320_rae_update_get, rt1320_rae_update_put),
2609 SOC_SINGLE_EXT("Brown Out Switch", SND_SOC_NOPM, 0, 1, 0,
2610 rt1320_brown_out_get, rt1320_brown_out_put),
2611 };
2612
2613 static const struct snd_kcontrol_new rt1320_spk_l_dac =
2614 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
2615 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01),
2616 0, 1, 1);
2617 static const struct snd_kcontrol_new rt1320_spk_r_dac =
2618 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
2619 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02),
2620 0, 1, 1);
2621
2622 static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = {
2623 /* Audio Interface */
2624 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
2625 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
2626 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
2627
2628 /* Digital Interface */
2629 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
2630 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
2631 rt1320_pde23_event,
2632 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2633 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
2634 rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2635 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
2636 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
2637 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
2638 rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2639
2640 /* Output */
2641 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
2642 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
2643 SND_SOC_DAPM_OUTPUT("SPOL"),
2644 SND_SOC_DAPM_OUTPUT("SPOR"),
2645
2646 /* Input */
2647 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
2648 SND_SOC_DAPM_SIGGEN("AEC Gen"),
2649 SND_SOC_DAPM_INPUT("DMIC1"),
2650 SND_SOC_DAPM_INPUT("DMIC2"),
2651 };
2652
2653 static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
2654 { "FU21", NULL, "DP1RX" },
2655 { "FU21", NULL, "PDE 23" },
2656 { "OT23 L", "Switch", "FU21" },
2657 { "OT23 R", "Switch", "FU21" },
2658 { "SPOL", NULL, "OT23 L" },
2659 { "SPOR", NULL, "OT23 R" },
2660
2661 { "AEC Data", NULL, "AEC Gen" },
2662 { "DP4TX", NULL, "AEC Data" },
2663
2664 {"DP8-10TX", NULL, "FU"},
2665 {"FU", NULL, "PDE 11"},
2666 {"FU", NULL, "FU 113"},
2667 {"FU", NULL, "FU 14"},
2668 {"FU 113", NULL, "DMIC1"},
2669 {"FU 14", NULL, "DMIC2"},
2670 };
2671
rt1320_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)2672 static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
2673 int direction)
2674 {
2675 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
2676 return 0;
2677 }
2678
rt1320_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2679 static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream,
2680 struct snd_soc_dai *dai)
2681 {
2682 snd_soc_dai_set_dma_data(dai, substream, NULL);
2683 }
2684
rt1320_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2685 static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream,
2686 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2687 {
2688 struct snd_soc_component *component = dai->component;
2689 struct rt1320_sdw_priv *rt1320 =
2690 snd_soc_component_get_drvdata(component);
2691 struct sdw_stream_config stream_config;
2692 struct sdw_port_config port_config;
2693 struct sdw_port_config dmic_port_config[2];
2694 struct sdw_stream_runtime *sdw_stream;
2695 int retval, num_channels;
2696 unsigned int sampling_rate;
2697
2698 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
2699 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
2700
2701 if (!sdw_stream)
2702 return -EINVAL;
2703
2704 if (!rt1320->sdw_slave)
2705 return -EINVAL;
2706
2707 /* SoundWire specific configuration */
2708 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
2709
2710 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2711 if (dai->id == RT1320_AIF1)
2712 port_config.num = 1;
2713 else
2714 return -EINVAL;
2715 } else {
2716 if (dai->id == RT1320_AIF1)
2717 port_config.num = 4;
2718 else if (dai->id == RT1320_AIF2) {
2719 switch (rt1320->dev_id) {
2720 case RT1320_DEV_ID:
2721 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
2722 dmic_port_config[0].num = 8;
2723 dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
2724 dmic_port_config[1].num = 10;
2725 break;
2726 case RT1321_DEV_ID:
2727 num_channels = params_channels(params);
2728 dmic_port_config[0].ch_mask = GENMASK(num_channels - 1, 0);
2729 dmic_port_config[0].num = 8;
2730 break;
2731 default:
2732 return -EINVAL;
2733 }
2734 } else
2735 return -EINVAL;
2736 }
2737
2738 if (dai->id == RT1320_AIF1)
2739 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2740 &port_config, 1, sdw_stream);
2741 else if (dai->id == RT1320_AIF2) {
2742 switch (rt1320->dev_id) {
2743 case RT1320_DEV_ID:
2744 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2745 dmic_port_config, 2, sdw_stream);
2746 break;
2747 case RT1321_DEV_ID:
2748 retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
2749 dmic_port_config, 1, sdw_stream);
2750 break;
2751 default:
2752 dev_err(dai->dev, "%s: Unknown device ID %d\n", __func__, rt1320->dev_id);
2753 return -EINVAL;
2754 }
2755 } else
2756 return -EINVAL;
2757 if (retval) {
2758 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
2759 return retval;
2760 }
2761
2762 /* sampling rate configuration */
2763 switch (params_rate(params)) {
2764 case 16000:
2765 sampling_rate = RT1320_SDCA_RATE_16000HZ;
2766 break;
2767 case 32000:
2768 sampling_rate = RT1320_SDCA_RATE_32000HZ;
2769 break;
2770 case 44100:
2771 sampling_rate = RT1320_SDCA_RATE_44100HZ;
2772 break;
2773 case 48000:
2774 sampling_rate = RT1320_SDCA_RATE_48000HZ;
2775 break;
2776 case 96000:
2777 sampling_rate = RT1320_SDCA_RATE_96000HZ;
2778 break;
2779 case 192000:
2780 sampling_rate = RT1320_SDCA_RATE_192000HZ;
2781 break;
2782 default:
2783 dev_err(component->dev, "%s: Rate %d is not supported\n",
2784 __func__, params_rate(params));
2785 return -EINVAL;
2786 }
2787
2788 /* set sampling frequency */
2789 if (dai->id == RT1320_AIF1)
2790 regmap_write(rt1320->regmap,
2791 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2792 sampling_rate);
2793 else {
2794 regmap_write(rt1320->regmap,
2795 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2796 sampling_rate);
2797
2798 if (rt1320->dev_id == RT1320_DEV_ID)
2799 regmap_write(rt1320->regmap,
2800 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2801 sampling_rate);
2802 }
2803
2804 return 0;
2805 }
2806
rt1320_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2807 static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
2808 struct snd_soc_dai *dai)
2809 {
2810 struct snd_soc_component *component = dai->component;
2811 struct rt1320_sdw_priv *rt1320 =
2812 snd_soc_component_get_drvdata(component);
2813 struct sdw_stream_runtime *sdw_stream =
2814 snd_soc_dai_get_dma_data(dai, substream);
2815
2816 if (!rt1320->sdw_slave)
2817 return -EINVAL;
2818
2819 sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream);
2820 return 0;
2821 }
2822
2823 /*
2824 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
2825 * port_prep are not defined for now
2826 */
2827 static const struct sdw_slave_ops rt1320_slave_ops = {
2828 .read_prop = rt1320_read_prop,
2829 .update_status = rt1320_update_status,
2830 };
2831
rt1320_sdw_component_probe(struct snd_soc_component * component)2832 static int rt1320_sdw_component_probe(struct snd_soc_component *component)
2833 {
2834 int ret;
2835 struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2836
2837 rt1320->component = component;
2838
2839 if (!rt1320->first_hw_init)
2840 return 0;
2841
2842 ret = pm_runtime_resume(component->dev);
2843 dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
2844 if (ret < 0 && ret != -EACCES)
2845 return ret;
2846
2847 /* Apply temperature and calibration data from device property */
2848 if ((rt1320->temp_l_calib <= 0xff) && (rt1320->temp_l_calib > 0) &&
2849 (rt1320->temp_r_calib <= 0xff) && (rt1320->temp_r_calib > 0))
2850 rt1320_t0_load(rt1320, rt1320->temp_l_calib, rt1320->temp_r_calib);
2851
2852 if (rt1320->r0_l_calib && rt1320->r0_r_calib) {
2853 rt1320->r0_l_reg = rt1320->r0_l_calib;
2854 rt1320->r0_r_reg = rt1320->r0_r_calib;
2855 rt1320_calc_r0(rt1320);
2856 rt1320_r0_load(rt1320);
2857 }
2858
2859 return 0;
2860 }
2861
2862 static const struct snd_soc_component_driver soc_component_sdw_rt1320 = {
2863 .probe = rt1320_sdw_component_probe,
2864 .controls = rt1320_snd_controls,
2865 .num_controls = ARRAY_SIZE(rt1320_snd_controls),
2866 .dapm_widgets = rt1320_dapm_widgets,
2867 .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets),
2868 .dapm_routes = rt1320_dapm_routes,
2869 .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes),
2870 .endianness = 1,
2871 };
2872
2873 static const struct snd_soc_dai_ops rt1320_aif_dai_ops = {
2874 .hw_params = rt1320_sdw_hw_params,
2875 .hw_free = rt1320_sdw_pcm_hw_free,
2876 .set_stream = rt1320_set_sdw_stream,
2877 .shutdown = rt1320_sdw_shutdown,
2878 };
2879
2880 #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
2881 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
2882 #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
2883 SNDRV_PCM_FMTBIT_S32_LE)
2884
2885 static struct snd_soc_dai_driver rt1320_sdw_dai[] = {
2886 {
2887 .name = "rt1320-aif1",
2888 .id = RT1320_AIF1,
2889 .playback = {
2890 .stream_name = "DP1 Playback",
2891 .channels_min = 1,
2892 .channels_max = 2,
2893 .rates = RT1320_STEREO_RATES,
2894 .formats = RT1320_FORMATS,
2895 },
2896 .capture = {
2897 .stream_name = "DP4 Capture",
2898 .channels_min = 1,
2899 .channels_max = 2,
2900 .rates = RT1320_STEREO_RATES,
2901 .formats = RT1320_FORMATS,
2902 },
2903 .ops = &rt1320_aif_dai_ops,
2904 },
2905 /* DMIC: DP8 2ch + DP10 2ch */
2906 {
2907 .name = "rt1320-aif2",
2908 .id = RT1320_AIF2,
2909 .capture = {
2910 .stream_name = "DP8-10 Capture",
2911 .channels_min = 1,
2912 .channels_max = 4,
2913 .rates = RT1320_STEREO_RATES,
2914 .formats = RT1320_FORMATS,
2915 },
2916 .ops = &rt1320_aif_dai_ops,
2917 },
2918 };
2919
rt1320_parse_dp(struct rt1320_sdw_priv * rt1320,struct device * dev)2920 static int rt1320_parse_dp(struct rt1320_sdw_priv *rt1320, struct device *dev)
2921 {
2922 device_property_read_u32(dev, "realtek,temperature_l_calib",
2923 &rt1320->temp_l_calib);
2924 device_property_read_u32(dev, "realtek,temperature_r_calib",
2925 &rt1320->temp_r_calib);
2926 device_property_read_u32(dev, "realtek,r0_l_calib",
2927 &rt1320->r0_l_calib);
2928 device_property_read_u32(dev, "realtek,r0_r_calib",
2929 &rt1320->r0_r_calib);
2930 device_property_read_string(dev, "realtek,dspfw-name",
2931 &rt1320->dspfw_name);
2932
2933 dev_dbg(dev, "%s: temp_l_calib: %d temp_r_calib: %d r0_l_calib: %d, r0_r_calib: %d",
2934 __func__, rt1320->temp_l_calib, rt1320->temp_r_calib, rt1320->r0_l_calib, rt1320->r0_r_calib);
2935 dev_dbg(dev, "%s: dspfw_name: %s", __func__, rt1320->dspfw_name);
2936
2937 return 0;
2938 }
2939
rt1320_sdw_init(struct device * dev,struct regmap * regmap,struct regmap * mbq_regmap,struct sdw_slave * slave)2940 static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
2941 struct regmap *mbq_regmap, struct sdw_slave *slave)
2942 {
2943 struct rt1320_sdw_priv *rt1320;
2944 int ret;
2945
2946 rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL);
2947 if (!rt1320)
2948 return -ENOMEM;
2949
2950 dev_set_drvdata(dev, rt1320);
2951 rt1320->sdw_slave = slave;
2952 rt1320->mbq_regmap = mbq_regmap;
2953 rt1320->regmap = regmap;
2954
2955 regcache_cache_only(rt1320->regmap, true);
2956 regcache_cache_only(rt1320->mbq_regmap, true);
2957
2958 rt1320_parse_dp(rt1320, dev);
2959
2960 /*
2961 * Mark hw_init to false
2962 * HW init will be performed when device reports present
2963 */
2964 rt1320->hw_init = false;
2965 rt1320->first_hw_init = false;
2966 rt1320->version_id = -1;
2967 rt1320->fu_dapm_mute = true;
2968 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
2969 rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true;
2970 rt1320->brown_out = 1;
2971
2972 INIT_WORK(&rt1320->load_dspfw_work, rt1320_load_dspfw_work);
2973
2974 ret = devm_snd_soc_register_component(dev,
2975 &soc_component_sdw_rt1320,
2976 rt1320_sdw_dai,
2977 ARRAY_SIZE(rt1320_sdw_dai));
2978 if (ret < 0)
2979 return ret;
2980
2981 /* set autosuspend parameters */
2982 pm_runtime_set_autosuspend_delay(dev, 3000);
2983 pm_runtime_use_autosuspend(dev);
2984
2985 /* make sure the device does not suspend immediately */
2986 pm_runtime_mark_last_busy(dev);
2987
2988 pm_runtime_enable(dev);
2989
2990 /* important note: the device is NOT tagged as 'active' and will remain
2991 * 'suspended' until the hardware is enumerated/initialized. This is required
2992 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
2993 * fail with -EACCESS because of race conditions between card creation and enumeration
2994 */
2995
2996 dev_dbg(dev, "%s\n", __func__);
2997
2998 return ret;
2999 }
3000
rt1320_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)3001 static int rt1320_sdw_probe(struct sdw_slave *slave,
3002 const struct sdw_device_id *id)
3003 {
3004 struct regmap *regmap, *mbq_regmap;
3005
3006 /* Regmap Initialization */
3007 mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap);
3008 if (IS_ERR(mbq_regmap))
3009 return PTR_ERR(mbq_regmap);
3010
3011 regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap);
3012 if (IS_ERR(regmap))
3013 return PTR_ERR(regmap);
3014
3015 return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave);
3016 }
3017
rt1320_sdw_remove(struct sdw_slave * slave)3018 static void rt1320_sdw_remove(struct sdw_slave *slave)
3019 {
3020 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
3021
3022 cancel_work_sync(&rt1320->load_dspfw_work);
3023 pm_runtime_disable(&slave->dev);
3024 }
3025
3026 /*
3027 * Version A/B will use the class id 0
3028 * The newer version than A/B will use the class id 1, so add it in advance
3029 */
3030 static const struct sdw_device_id rt1320_id[] = {
3031 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
3032 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
3033 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0),
3034 {},
3035 };
3036 MODULE_DEVICE_TABLE(sdw, rt1320_id);
3037
rt1320_dev_suspend(struct device * dev)3038 static int rt1320_dev_suspend(struct device *dev)
3039 {
3040 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
3041
3042 if (!rt1320->hw_init)
3043 return 0;
3044
3045 regcache_cache_only(rt1320->regmap, true);
3046 regcache_cache_only(rt1320->mbq_regmap, true);
3047 return 0;
3048 }
3049
3050 #define RT1320_PROBE_TIMEOUT 5000
3051
rt1320_dev_resume(struct device * dev)3052 static int rt1320_dev_resume(struct device *dev)
3053 {
3054 struct sdw_slave *slave = dev_to_sdw_dev(dev);
3055 struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
3056 unsigned long time;
3057
3058 if (!rt1320->first_hw_init)
3059 return 0;
3060
3061 if (!slave->unattach_request)
3062 goto regmap_sync;
3063
3064 time = wait_for_completion_timeout(&slave->initialization_complete,
3065 msecs_to_jiffies(RT1320_PROBE_TIMEOUT));
3066 if (!time) {
3067 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
3068 return -ETIMEDOUT;
3069 }
3070
3071 regmap_sync:
3072 slave->unattach_request = 0;
3073 regcache_cache_only(rt1320->regmap, false);
3074 regcache_sync(rt1320->regmap);
3075 regcache_cache_only(rt1320->mbq_regmap, false);
3076 regcache_sync(rt1320->mbq_regmap);
3077 return 0;
3078 }
3079
3080 static const struct dev_pm_ops rt1320_pm = {
3081 SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume)
3082 RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL)
3083 };
3084
3085 static struct sdw_driver rt1320_sdw_driver = {
3086 .driver = {
3087 .name = "rt1320-sdca",
3088 .pm = pm_ptr(&rt1320_pm),
3089 },
3090 .probe = rt1320_sdw_probe,
3091 .remove = rt1320_sdw_remove,
3092 .ops = &rt1320_slave_ops,
3093 .id_table = rt1320_id,
3094 };
3095 module_sdw_driver(rt1320_sdw_driver);
3096
3097 MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW");
3098 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
3099 MODULE_LICENSE("GPL");
3100