1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * rt1318.h -- Platform data for RT1318 4 * 5 * Copyright 2024 Realtek Semiconductor Corp. 6 */ 7 #include <sound/rt1318.h> 8 9 #ifndef __RT1318_H__ 10 #define __RT1318_H__ 11 12 struct rt1318_priv { 13 struct snd_soc_component *component; 14 struct rt1318_platform_data pdata; 15 struct work_struct cali_work; 16 struct regmap *regmap; 17 18 unsigned int r0_l_integer; 19 unsigned int r0_l_factor; 20 unsigned int r0_r_integer; 21 unsigned int r0_r_factor; 22 int rt1318_init; 23 int rt1318_dvol; 24 int sysclk_src; 25 int sysclk; 26 int lrck; 27 int bclk; 28 int master; 29 int pll_src; 30 int pll_in; 31 int pll_out; 32 }; 33 34 #define RT1318_PLL_INP_MAX 40000000 35 #define RT1318_PLL_INP_MIN 256000 36 #define RT1318_PLL_N_MAX 0x1ff 37 #define RT1318_PLL_K_MAX 0x1f 38 #define RT1318_PLL_M_MAX 0x1f 39 40 #define RT1318_LRCLK_192000 192000 41 #define RT1318_LRCLK_96000 96000 42 #define RT1318_LRCLK_48000 48000 43 #define RT1318_LRCLK_44100 44100 44 #define RT1318_LRCLK_16000 16000 45 #define RT1318_DVOL_STEP 383 46 47 #define RT1318_CLK1 0xc001 48 #define RT1318_CLK2 0xc003 49 #define RT1318_CLK3 0xc004 50 #define RT1318_CLK4 0xc005 51 #define RT1318_CLK5 0xc006 52 #define RT1318_CLK6 0xc007 53 #define RT1318_CLK7 0xc008 54 #define RT1318_PWR_STA1 0xc121 55 #define RT1318_SPK_VOL_TH 0xc130 56 #define RT1318_TCON 0xc203 57 #define RT1318_SRC_TCON 0xc204 58 #define RT1318_TCON_RELATE 0xc206 59 #define RT1318_DA_VOL_L_8 0xc20b 60 #define RT1318_DA_VOL_L_1_7 0xc20c 61 #define RT1318_DA_VOL_R_8 0xc20d 62 #define RT1318_DA_VOL_R_1_7 0xc20e 63 #define RT1318_FEEDBACK_PATH 0xc321 64 #define RT1318_STP_TEMP_L 0xdb00 65 #define RT1318_STP_SEL_L 0xdb08 66 #define RT1318_STP_R0_EN_L 0xdb12 67 #define RT1318_R0_CMP_L_FLAG 0xdb35 68 #define RT1318_PRE_R0_L_24 0xdbb5 69 #define RT1318_PRE_R0_L_23_16 0xdbb6 70 #define RT1318_PRE_R0_L_15_8 0xdbb7 71 #define RT1318_PRE_R0_L_7_0 0xdbb8 72 #define RT1318_R0_L_24 0xdbc5 73 #define RT1318_R0_L_23_16 0xdbc6 74 #define RT1318_R0_L_15_8 0xdbc7 75 #define RT1318_R0_L_7_0 0xdbc8 76 #define RT1318_STP_SEL_R 0xdd08 77 #define RT1318_STP_R0_EN_R 0xdd12 78 #define RT1318_R0_CMP_R_FLAG 0xdd35 79 #define RT1318_PRE_R0_R_24 0xddb5 80 #define RT1318_PRE_R0_R_23_16 0xddb6 81 #define RT1318_PRE_R0_R_15_8 0xddb7 82 #define RT1318_PRE_R0_R_7_0 0xddb8 83 #define RT1318_R0_R_24 0xddc5 84 #define RT1318_R0_R_23_16 0xddc6 85 #define RT1318_R0_R_15_8 0xddc7 86 #define RT1318_R0_R_7_0 0xddc8 87 #define RT1318_DEV_ID1 0xf012 88 #define RT1318_DEV_ID2 0xf013 89 #define RT1318_PLL1_K 0xf20d 90 #define RT1318_PLL1_M 0xf20f 91 #define RT1318_PLL1_N_8 0xf211 92 #define RT1318_PLL1_N_7_0 0xf212 93 #define RT1318_SINE_GEN0 0xf800 94 #define RT1318_TDM_CTRL1 0xf900 95 #define RT1318_TDM_CTRL2 0xf901 96 #define RT1318_TDM_CTRL3 0xf902 97 #define RT1318_TDM_CTRL9 0xf908 98 99 100 /* Clock-1 (0xC001) */ 101 #define RT1318_PLLIN_MASK (0x7 << 4) 102 #define RT1318_PLLIN_BCLK0 (0x0 << 4) 103 #define RT1318_PLLIN_BCLK1 (0x1 << 4) 104 #define RT1318_PLLIN_RC (0x2 << 4) 105 #define RT1318_PLLIN_MCLK (0x3 << 4) 106 #define RT1318_PLLIN_SDW1 (0x4 << 4) 107 #define RT1318_PLLIN_SDW2 (0x5 << 4) 108 #define RT1318_PLLIN_SDW3 (0x6 << 4) 109 #define RT1318_PLLIN_SDW4 (0x7 << 4) 110 #define RT1318_SYSCLK_SEL_MASK (0x7 << 0) 111 #define RT1318_SYSCLK_BCLK (0x0 << 0) 112 #define RT1318_SYSCLK_SDW (0x1 << 0) 113 #define RT1318_SYSCLK_PLL2F (0x2 << 0) 114 #define RT1318_SYSCLK_PLL2B (0x3 << 0) 115 #define RT1318_SYSCLK_MCLK (0x4 << 0) 116 #define RT1318_SYSCLK_RC1 (0x5 << 0) 117 #define RT1318_SYSCLK_RC2 (0x6 << 0) 118 #define RT1318_SYSCLK_RC3 (0x7 << 0) 119 /* Clock-2 (0xC003) */ 120 #define RT1318_DIV_AP_MASK (0x3 << 4) 121 #define RT1318_DIV_AP_SFT 4 122 #define RT1318_DIV_AP_DIV1 (0x0 << 4) 123 #define RT1318_DIV_AP_DIV2 (0x1 << 4) 124 #define RT1318_DIV_AP_DIV4 (0x2 << 4) 125 #define RT1318_DIV_AP_DIV8 (0x3 << 4) 126 #define RT1318_DIV_DAMOD_MASK (0x3 << 0) 127 #define RT1318_DIV_DAMOD_SFT 0 128 #define RT1318_DIV_DAMOD_DIV1 (0x0 << 0) 129 #define RT1318_DIV_DAMOD_DIV2 (0x1 << 0) 130 #define RT1318_DIV_DAMOD_DIV4 (0x2 << 0) 131 #define RT1318_DIV_DAMOD_DIV8 (0x3 << 0) 132 /* Clock-3 (0xC004) */ 133 #define RT1318_AD_STO1_MASK (0x7 << 4) 134 #define RT1318_AD_STO1_SFT 4 135 #define RT1318_AD_STO1_DIV1 (0x0 << 4) 136 #define RT1318_AD_STO1_DIV2 (0x1 << 4) 137 #define RT1318_AD_STO1_DIV4 (0x2 << 4) 138 #define RT1318_AD_STO1_DIV8 (0x3 << 4) 139 #define RT1318_AD_STO1_DIV16 (0x4 << 4) 140 #define RT1318_AD_STO2_MASK (0x7 << 0) 141 #define RT1318_AD_STO2_SFT 0 142 #define RT1318_AD_STO2_DIV1 (0x0 << 0) 143 #define RT1318_AD_STO2_DIV2 (0x1 << 0) 144 #define RT1318_AD_STO2_DIV4 (0x2 << 0) 145 #define RT1318_AD_STO2_DIV8 (0x3 << 0) 146 #define RT1318_AD_STO2_DIV16 (0x4 << 0) 147 #define RT1318_AD_STO2_SFT 0 148 /* Clock-4 (0xC005) */ 149 #define RT1318_AD_ANA_STO1_MASK (0x7 << 4) 150 #define RT1318_AD_ANA_STO1_SFT 4 151 #define RT1318_AD_ANA_STO1_DIV1 (0x0 << 4) 152 #define RT1318_AD_ANA_STO1_DIV2 (0x1 << 4) 153 #define RT1318_AD_ANA_STO1_DIV4 (0x2 << 4) 154 #define RT1318_AD_ANA_STO1_DIV8 (0x3 << 4) 155 #define RT1318_AD_ANA_STO1_DIV16 (0x4 << 4) 156 #define RT1318_AD_ANA_STO2_MASK (0x7 << 0) 157 #define RT1318_AD_ANA_STO2_DIV1 (0x0 << 0) 158 #define RT1318_AD_ANA_STO2_DIV2 (0x1 << 0) 159 #define RT1318_AD_ANA_STO2_DIV4 (0x2 << 0) 160 #define RT1318_AD_ANA_STO2_DIV8 (0x3 << 0) 161 #define RT1318_AD_ANA_STO2_DIV16 (0x4 << 0) 162 #define RT1318_AD_ANA_STO2_SFT 0 163 /* Clock-5 (0xC006) */ 164 #define RT1318_DIV_FIFO_IN_MASK (0x3 << 4) 165 #define RT1318_DIV_FIFO_IN_SFT 4 166 #define RT1318_DIV_FIFO_IN_DIV1 (0x0 << 4) 167 #define RT1318_DIV_FIFO_IN_DIV2 (0x1 << 4) 168 #define RT1318_DIV_FIFO_IN_DIV4 (0x2 << 4) 169 #define RT1318_DIV_FIFO_IN_DIV8 (0x3 << 4) 170 #define RT1318_DIV_FIFO_OUT_MASK (0x3 << 0) 171 #define RT1318_DIV_FIFO_OUT_DIV1 (0x0 << 0) 172 #define RT1318_DIV_FIFO_OUT_DIV2 (0x1 << 0) 173 #define RT1318_DIV_FIFO_OUT_DIV4 (0x2 << 0) 174 #define RT1318_DIV_FIFO_OUT_DIV8 (0x3 << 0) 175 #define RT1318_DIV_FIFO_OUT_SFT 0 176 /* Clock-6 (0xC007) */ 177 #define RT1318_DIV_NLMS_MASK (0x3 << 6) 178 #define RT1318_DIV_NLMS_SFT 6 179 #define RT1318_DIV_NLMS_DIV1 (0x0 << 6) 180 #define RT1318_DIV_NLMS_DIV2 (0x1 << 6) 181 #define RT1318_DIV_NLMS_DIV4 (0x2 << 6) 182 #define RT1318_DIV_NLMS_DIV8 (0x3 << 6) 183 #define RT1318_DIV_AD_MONO_MASK (0x7 << 3) 184 #define RT1318_DIV_AD_MONO_SFT 3 185 #define RT1318_DIV_AD_MONO_DIV1 (0x0 << 3) 186 #define RT1318_DIV_AD_MONO_DIV2 (0x1 << 3) 187 #define RT1318_DIV_AD_MONO_DIV4 (0x2 << 3) 188 #define RT1318_DIV_AD_MONO_DIV8 (0x3 << 3) 189 #define RT1318_DIV_AD_MONO_DIV16 (0x4 << 3) 190 #define RT1318_DIV_POST_G_MASK (0x7 << 0) 191 #define RT1318_DIV_POST_G_SFT 0 192 #define RT1318_DIV_POST_G_DIV1 (0x0 << 0) 193 #define RT1318_DIV_POST_G_DIV2 (0x1 << 0) 194 #define RT1318_DIV_POST_G_DIV4 (0x2 << 0) 195 #define RT1318_DIV_POST_G_DIV8 (0x3 << 0) 196 #define RT1318_DIV_POST_G_DIV16 (0x4 << 0) 197 /* Power Status 1 (0xC121) */ 198 #define RT1318_PDB_CTRL_MASK (0x1) 199 #define RT1318_PDB_CTRL_LOW (0x0) 200 #define RT1318_PDB_CTRL_HIGH (0x1) 201 #define RT1318_PDB_CTRL_SFT 0 202 /* SRC Tcon(0xc204) */ 203 #define RT1318_SRCIN_IN_SEL_MASK (0x3 << 6) 204 #define RT1318_SRCIN_IN_48K (0x0 << 6) 205 #define RT1318_SRCIN_IN_44P1 (0x1 << 6) 206 #define RT1318_SRCIN_IN_32K (0x2 << 6) 207 #define RT1318_SRCIN_IN_16K (0x3 << 6) 208 #define RT1318_SRCIN_F12288_MASK (0x3 << 4) 209 #define RT1318_SRCIN_TCON1 (0x0 << 4) 210 #define RT1318_SRCIN_TCON2 (0x1 << 4) 211 #define RT1318_SRCIN_TCON4 (0x2 << 4) 212 #define RT1318_SRCIN_TCON8 (0x3 << 4) 213 #define RT1318_SRCIN_DACLK_MASK (0x3 << 2) 214 #define RT1318_DACLK_TCON1 (0x0 << 2) 215 #define RT1318_DACLK_TCON2 (0x1 << 2) 216 #define RT1318_DACLK_TCON4 (0x2 << 2) 217 #define RT1318_DACLK_TCON8 (0x3 << 2) 218 /* R0 Compare Flag (0xDB35) */ 219 #define RT1318_R0_RANGE_MASK (0x1) 220 #define RT1318_R0_OUTOFRANGE (0x0) 221 #define RT1318_R0_INRANGE (0x1) 222 /* PLL internal setting (0xF20D), K value */ 223 #define RT1318_K_PLL1_MASK (0x1f << 0) 224 /* PLL internal setting (0xF20F), M value */ 225 #define RT1318_M_PLL1_MASK (0x1f << 0) 226 /* PLL internal setting (0xF211), N_8 value */ 227 #define RT1318_N_8_PLL1_MASK (0x1 << 0) 228 /* PLL internal setting (0xF212), N_7_0 value */ 229 #define RT1318_N_7_0_PLL1_MASK (0xff << 0) 230 /* TDM CTRL 1 (0xf900) */ 231 #define RT1318_TDM_BCLK_MASK (0x1 << 7) 232 #define RT1318_TDM_BCLK_NORM (0x0 << 7) 233 #define RT1318_TDM_BCLK_INV (0x1 << 7) 234 #define RT1318_I2S_FMT_MASK (0x7 << 0) 235 #define RT1318_FMT_I2S (0x0 << 0) 236 #define RT1318_FMT_LEFT_J (0x1 << 0) 237 #define RT1318_FMT_PCM_A_R (0x2 << 0) 238 #define RT1318_FMT_PCM_B_R (0x3 << 0) 239 #define RT1318_FMT_PCM_A_F (0x6 << 0) 240 #define RT1318_FMT_PCM_B_F (0x7 << 0) 241 #define RT1318_I2S_FMT_SFT 0 242 /* TDM CTRL 2 (0xf901) */ 243 #define RT1318_I2S_CH_TX_MASK (0x3 << 6) 244 #define RT1318_I2S_CH_TX_2CH (0x0 << 6) 245 #define RT1318_I2S_CH_TX_4CH (0x1 << 6) 246 #define RT1318_I2S_CH_TX_6CH (0x2 << 6) 247 #define RT1318_I2S_CH_TX_8CH (0x3 << 6) 248 #define RT1318_I2S_CH_RX_MASK (0x3 << 4) 249 #define RT1318_I2S_CH_RX_2CH (0x0 << 4) 250 #define RT1318_I2S_CH_RX_4CH (0x1 << 4) 251 #define RT1318_I2S_CH_RX_6CH (0x2 << 4) 252 #define RT1318_I2S_CH_RX_8CH (0x3 << 4) 253 #define RT1318_I2S_DL_MASK 0x7 254 #define RT1318_I2S_DL_SFT 0 255 #define RT1318_I2S_DL_16 0x0 256 #define RT1318_I2S_DL_20 0x1 257 #define RT1318_I2S_DL_24 0x2 258 #define RT1318_I2S_DL_32 0x3 259 #define RT1318_I2S_DL_8 0x4 260 /* TDM CTRL 3 (0xf902) */ 261 #define RT1318_I2S_TX_CHL_MASK (0x7 << 4) 262 #define RT1318_I2S_TX_CHL_SFT 4 263 #define RT1318_I2S_TX_CHL_16 (0x0 << 4) 264 #define RT1318_I2S_TX_CHL_20 (0x1 << 4) 265 #define RT1318_I2S_TX_CHL_24 (0x2 << 4) 266 #define RT1318_I2S_TX_CHL_32 (0x3 << 4) 267 #define RT1318_I2S_TX_CHL_8 (0x4 << 4) 268 #define RT1318_I2S_RX_CHL_MASK (0x7 << 0) 269 #define RT1318_I2S_RX_CHL_SFT 0 270 #define RT1318_I2S_RX_CHL_16 (0x0 << 0) 271 #define RT1318_I2S_RX_CHL_20 (0x1 << 0) 272 #define RT1318_I2S_RX_CHL_24 (0x2 << 0) 273 #define RT1318_I2S_RX_CHL_32 (0x3 << 0) 274 #define RT1318_I2S_RX_CHL_8 (0x4 << 0) 275 /* TDM CTRL 9 (0xf908) */ 276 #define RT1318_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 4) 277 #define RT1318_TDM_I2S_TX_R_DAC1_1_MASK 0x7 278 #define RT1318_TDM_I2S_TX_L_DAC1_1_SFT 4 279 #define RT1318_TDM_I2S_TX_R_DAC1_1_SFT 0 280 281 #define RT1318_REG_DISP_LEN 23 282 283 /* System Clock Source */ 284 enum { 285 RT1318_SCLK_S_BCLK, 286 RT1318_SCLK_S_SDW, 287 RT1318_SCLK_S_PLL2F, 288 RT1318_SCLK_S_PLL2B, 289 RT1318_SCLK_S_MCLK, 290 RT1318_SCLK_S_RC0, 291 RT1318_SCLK_S_RC1, 292 RT1318_SCLK_S_RC2, 293 }; 294 295 /* PLL Source */ 296 enum { 297 RT1318_PLL_S_BCLK0, 298 RT1318_PLL_S_BCLK1, 299 RT1318_PLL_S_RC, 300 RT1318_PLL_S_MCLK, 301 RT1318_PLL_S_SDW_IN_PLL, 302 RT1318_PLL_S_SDW_0, 303 RT1318_PLL_S_SDW_1, 304 RT1318_PLL_S_SDW_2, 305 }; 306 307 /* TDM channel */ 308 enum { 309 RT1318_2CH, 310 RT1318_4CH, 311 RT1318_6CH, 312 RT1318_8CH, 313 }; 314 315 /* R0 calibration result */ 316 enum { 317 RT1318_R0_OUT_OF_RANGE, 318 RT1318_R0_IN_RANGE, 319 RT1318_R0_CALIB_NOT_DONE, 320 }; 321 322 /* PLL pre-defined M/N/K */ 323 324 struct pll_calc_map { 325 unsigned int pll_in; 326 unsigned int pll_out; 327 int k; 328 int n; 329 int m; 330 bool m_bp; 331 bool k_bp; 332 }; 333 334 struct rt1318_pll_code { 335 bool m_bp; /* Indicates bypass m code or not. */ 336 bool k_bp; /* Indicates bypass k code or not. */ 337 int m_code; 338 int n_code; 339 int k_code; 340 }; 341 342 #endif /* __RT1318_H__ */ 343