1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/spi/spi.h>
9 #include <linux/crc7.h>
10 #include <linux/crc-itu-t.h>
11 #include <linux/gpio/consumer.h>
12
13 #include "netdev.h"
14 #include "cfg80211.h"
15
16 #define SPI_MODALIAS "wilc1000_spi"
17
18 static bool enable_crc7; /* protect SPI commands with CRC7 */
19 module_param(enable_crc7, bool, 0644);
20 MODULE_PARM_DESC(enable_crc7,
21 "Enable CRC7 checksum to protect command transfers\n"
22 "\t\t\tagainst corruption during the SPI transfer.\n"
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
24 "\t\t\tof enabling this is small.");
25
26 static bool enable_crc16; /* protect SPI data with CRC16 */
27 module_param(enable_crc16, bool, 0644);
28 MODULE_PARM_DESC(enable_crc16,
29 "Enable CRC16 checksum to protect data transfers\n"
30 "\t\t\tagainst corruption during the SPI transfer.\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
32 "\t\t\tof enabling this may be substantial.");
33
34 /*
35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
36 * more zero bytes between the command response and the DATA Start tag
37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
39 * zero bytes when the SPI bus operates at 48MHz and none when it
40 * operates at 1MHz.
41 */
42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8
43
44 struct wilc_spi {
45 bool isinit; /* true if wilc_spi_init was successful */
46 bool probing_crc; /* true if we're probing chip's CRC config */
47 bool crc7_enabled; /* true if crc7 is currently enabled */
48 bool crc16_enabled; /* true if crc16 is currently enabled */
49 struct wilc_gpios {
50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */
51 struct gpio_desc *reset; /* RESET GPIO or NULL */
52 } gpios;
53 };
54
55 static const struct wilc_hif_func wilc_hif_spi;
56
57 static int wilc_spi_reset(struct wilc *wilc);
58 static int wilc_spi_configure_bus_protocol(struct wilc *wilc);
59 static int wilc_validate_chipid(struct wilc *wilc);
60
61 /********************************************
62 *
63 * Spi protocol Function
64 *
65 ********************************************/
66
67 #define CMD_DMA_WRITE 0xc1
68 #define CMD_DMA_READ 0xc2
69 #define CMD_INTERNAL_WRITE 0xc3
70 #define CMD_INTERNAL_READ 0xc4
71 #define CMD_TERMINATE 0xc5
72 #define CMD_REPEAT 0xc6
73 #define CMD_DMA_EXT_WRITE 0xc7
74 #define CMD_DMA_EXT_READ 0xc8
75 #define CMD_SINGLE_WRITE 0xc9
76 #define CMD_SINGLE_READ 0xca
77 #define CMD_RESET 0xcf
78
79 #define SPI_RETRY_MAX_LIMIT 10
80 #define SPI_ENABLE_VMM_RETRY_LIMIT 2
81
82 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
83 #define RSP_START_FIELD GENMASK(7, 4)
84 #define RSP_TYPE_FIELD GENMASK(3, 0)
85
86 /* SPI response values for the response fields: */
87 #define RSP_START_TAG 0xc
88 #define RSP_TYPE_FIRST_PACKET 0x1
89 #define RSP_TYPE_INNER_PACKET 0x2
90 #define RSP_TYPE_LAST_PACKET 0x3
91 #define RSP_STATE_NO_ERROR 0x00
92
93 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4)
94 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3)
95 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2)
96
97 /*
98 * The SPI data packet size may be any integer power of two in the
99 * range from 256 to 8192 bytes.
100 */
101 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */
102 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */
103
104 /*
105 * Select the data packet size (log2 of number of bytes): Use the
106 * maximum data packet size. We only retransmit complete packets, so
107 * there is no benefit from using smaller data packets.
108 */
109 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX
110 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ)
111
112 #define WILC_SPI_COMMAND_STAT_SUCCESS 0
113 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
114
115 struct wilc_spi_cmd {
116 u8 cmd_type;
117 union {
118 struct {
119 u8 addr[3];
120 u8 crc[];
121 } __packed simple_cmd;
122 struct {
123 u8 addr[3];
124 u8 size[2];
125 u8 crc[];
126 } __packed dma_cmd;
127 struct {
128 u8 addr[3];
129 u8 size[3];
130 u8 crc[];
131 } __packed dma_cmd_ext;
132 struct {
133 u8 addr[2];
134 __be32 data;
135 u8 crc[];
136 } __packed internal_w_cmd;
137 struct {
138 u8 addr[3];
139 __be32 data;
140 u8 crc[];
141 } __packed w_cmd;
142 } u;
143 } __packed;
144
145 struct wilc_spi_read_rsp_data {
146 u8 header;
147 u8 data[4];
148 u8 crc[];
149 } __packed;
150
151 struct wilc_spi_rsp_data {
152 u8 rsp_cmd_type;
153 u8 status;
154 u8 data[];
155 } __packed;
156
157 struct wilc_spi_special_cmd_rsp {
158 u8 skip_byte;
159 u8 rsp_cmd_type;
160 u8 status;
161 } __packed;
162
wilc_parse_gpios(struct wilc * wilc)163 static int wilc_parse_gpios(struct wilc *wilc)
164 {
165 struct spi_device *spi = to_spi_device(wilc->dev);
166 struct wilc_spi *spi_priv = wilc->bus_data;
167 struct wilc_gpios *gpios = &spi_priv->gpios;
168
169 /* get ENABLE pin and deassert it (if it is defined): */
170 gpios->enable = devm_gpiod_get_optional(&spi->dev,
171 "enable", GPIOD_OUT_LOW);
172 /* get RESET pin and assert it (if it is defined): */
173 if (gpios->enable) {
174 /* if enable pin exists, reset must exist as well */
175 gpios->reset = devm_gpiod_get(&spi->dev,
176 "reset", GPIOD_OUT_HIGH);
177 if (IS_ERR(gpios->reset)) {
178 dev_err(&spi->dev, "missing reset gpio.\n");
179 return PTR_ERR(gpios->reset);
180 }
181 } else {
182 gpios->reset = devm_gpiod_get_optional(&spi->dev,
183 "reset", GPIOD_OUT_HIGH);
184 }
185 return 0;
186 }
187
wilc_wlan_power(struct wilc * wilc,bool on)188 static void wilc_wlan_power(struct wilc *wilc, bool on)
189 {
190 struct wilc_spi *spi_priv = wilc->bus_data;
191 struct wilc_gpios *gpios = &spi_priv->gpios;
192
193 if (on) {
194 /* assert ENABLE: */
195 gpiod_set_value(gpios->enable, 1);
196 mdelay(5);
197 /* deassert RESET: */
198 gpiod_set_value(gpios->reset, 0);
199 } else {
200 /* assert RESET: */
201 gpiod_set_value(gpios->reset, 1);
202 /* deassert ENABLE: */
203 gpiod_set_value(gpios->enable, 0);
204 }
205 }
206
wilc_bus_probe(struct spi_device * spi)207 static int wilc_bus_probe(struct spi_device *spi)
208 {
209 struct wilc_spi *spi_priv;
210 struct wilc_vif *vif;
211 struct wilc *wilc;
212 int ret;
213
214 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
215 if (!spi_priv)
216 return -ENOMEM;
217
218 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
219 if (ret)
220 goto free;
221
222 spi_set_drvdata(spi, wilc);
223 wilc->dev = &spi->dev;
224 wilc->bus_data = spi_priv;
225 wilc->dev_irq_num = spi->irq;
226
227 ret = wilc_parse_gpios(wilc);
228 if (ret < 0)
229 goto netdev_cleanup;
230
231 wilc->rtc_clk = devm_clk_get_optional_enabled(&spi->dev, "rtc");
232 if (IS_ERR(wilc->rtc_clk)) {
233 ret = PTR_ERR(wilc->rtc_clk);
234 goto netdev_cleanup;
235 }
236
237 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n",
238 enable_crc7 ? "on" : "off", enable_crc16 ? "on" : "off");
239
240 /* we need power to configure the bus protocol and to read the chip id: */
241
242 wilc_wlan_power(wilc, true);
243
244 ret = wilc_spi_configure_bus_protocol(wilc);
245 if (ret)
246 goto power_down;
247
248 ret = wilc_get_chipid(wilc);
249 if (ret)
250 goto power_down;
251
252 ret = wilc_cfg80211_register(wilc);
253 if (ret)
254 goto power_down;
255
256 ret = wilc_load_mac_from_nv(wilc);
257 if (ret) {
258 pr_err("Can not retrieve MAC address from chip\n");
259 goto power_down;
260 }
261
262 wilc_wlan_power(wilc, false);
263 vif = wilc_netdev_ifc_init(wilc, "wlan%d", WILC_STATION_MODE,
264 NL80211_IFTYPE_STATION, false);
265 if (IS_ERR(vif)) {
266 ret = PTR_ERR(vif);
267 goto power_down;
268 }
269 return 0;
270
271 power_down:
272 wilc_wlan_power(wilc, false);
273 netdev_cleanup:
274 wilc_netdev_cleanup(wilc);
275 free:
276 kfree(spi_priv);
277 return ret;
278 }
279
wilc_bus_remove(struct spi_device * spi)280 static void wilc_bus_remove(struct spi_device *spi)
281 {
282 struct wilc *wilc = spi_get_drvdata(spi);
283 struct wilc_spi *spi_priv = wilc->bus_data;
284
285 wilc_netdev_cleanup(wilc);
286 kfree(spi_priv);
287 }
288
289 static const struct of_device_id wilc_of_match[] = {
290 { .compatible = "microchip,wilc1000", },
291 { /* sentinel */ }
292 };
293 MODULE_DEVICE_TABLE(of, wilc_of_match);
294
295 static const struct spi_device_id wilc_spi_id[] = {
296 { "wilc1000", 0 },
297 { /* sentinel */ }
298 };
299 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
300
301 static struct spi_driver wilc_spi_driver = {
302 .driver = {
303 .name = SPI_MODALIAS,
304 .of_match_table = wilc_of_match,
305 },
306 .id_table = wilc_spi_id,
307 .probe = wilc_bus_probe,
308 .remove = wilc_bus_remove,
309 };
310 module_spi_driver(wilc_spi_driver);
311 MODULE_DESCRIPTION("Atmel WILC1000 SPI wireless driver");
312 MODULE_LICENSE("GPL");
313
wilc_spi_tx(struct wilc * wilc,u8 * b,u32 len)314 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
315 {
316 struct spi_device *spi = to_spi_device(wilc->dev);
317 int ret;
318 struct spi_message msg;
319
320 if (len > 0 && b) {
321 struct spi_transfer tr = {
322 .tx_buf = b,
323 .len = len,
324 .delay = {
325 .value = 0,
326 .unit = SPI_DELAY_UNIT_USECS
327 },
328 };
329 char *r_buffer = kzalloc(len, GFP_KERNEL);
330
331 if (!r_buffer)
332 return -ENOMEM;
333
334 tr.rx_buf = r_buffer;
335 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
336
337 memset(&msg, 0, sizeof(msg));
338 spi_message_init(&msg);
339 spi_message_add_tail(&tr, &msg);
340
341 ret = spi_sync(spi, &msg);
342 if (ret < 0)
343 dev_err(&spi->dev, "SPI transaction failed\n");
344
345 kfree(r_buffer);
346 } else {
347 dev_err(&spi->dev,
348 "can't write data with the following length: %d\n",
349 len);
350 ret = -EINVAL;
351 }
352
353 return ret;
354 }
355
wilc_spi_rx(struct wilc * wilc,u8 * rb,u32 rlen)356 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
357 {
358 struct spi_device *spi = to_spi_device(wilc->dev);
359 int ret;
360
361 if (rlen > 0) {
362 struct spi_message msg;
363 struct spi_transfer tr = {
364 .rx_buf = rb,
365 .len = rlen,
366 .delay = {
367 .value = 0,
368 .unit = SPI_DELAY_UNIT_USECS
369 },
370
371 };
372 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
373
374 if (!t_buffer)
375 return -ENOMEM;
376
377 tr.tx_buf = t_buffer;
378
379 memset(&msg, 0, sizeof(msg));
380 spi_message_init(&msg);
381 spi_message_add_tail(&tr, &msg);
382
383 ret = spi_sync(spi, &msg);
384 if (ret < 0)
385 dev_err(&spi->dev, "SPI transaction failed\n");
386 kfree(t_buffer);
387 } else {
388 dev_err(&spi->dev,
389 "can't read data with the following length: %u\n",
390 rlen);
391 ret = -EINVAL;
392 }
393
394 return ret;
395 }
396
wilc_spi_tx_rx(struct wilc * wilc,u8 * wb,u8 * rb,u32 rlen)397 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
398 {
399 struct spi_device *spi = to_spi_device(wilc->dev);
400 int ret;
401
402 if (rlen > 0) {
403 struct spi_message msg;
404 struct spi_transfer tr = {
405 .rx_buf = rb,
406 .tx_buf = wb,
407 .len = rlen,
408 .bits_per_word = 8,
409 .delay = {
410 .value = 0,
411 .unit = SPI_DELAY_UNIT_USECS
412 },
413
414 };
415
416 memset(&msg, 0, sizeof(msg));
417 spi_message_init(&msg);
418 spi_message_add_tail(&tr, &msg);
419 ret = spi_sync(spi, &msg);
420 if (ret < 0)
421 dev_err(&spi->dev, "SPI transaction failed\n");
422 } else {
423 dev_err(&spi->dev,
424 "can't read data with the following length: %u\n",
425 rlen);
426 ret = -EINVAL;
427 }
428
429 return ret;
430 }
431
spi_data_write(struct wilc * wilc,u8 * b,u32 sz)432 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
433 {
434 struct spi_device *spi = to_spi_device(wilc->dev);
435 struct wilc_spi *spi_priv = wilc->bus_data;
436 int ix, nbytes;
437 int result = 0;
438 u8 cmd, order, crc[2];
439 u16 crc_calc;
440
441 /*
442 * Data
443 */
444 ix = 0;
445 do {
446 if (sz <= DATA_PKT_SZ) {
447 nbytes = sz;
448 order = 0x3;
449 } else {
450 nbytes = DATA_PKT_SZ;
451 if (ix == 0)
452 order = 0x1;
453 else
454 order = 0x02;
455 }
456
457 /*
458 * Write command
459 */
460 cmd = 0xf0;
461 cmd |= order;
462
463 if (wilc_spi_tx(wilc, &cmd, 1)) {
464 dev_err(&spi->dev,
465 "Failed data block cmd write, bus error...\n");
466 result = -EINVAL;
467 break;
468 }
469
470 /*
471 * Write data
472 */
473 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
474 dev_err(&spi->dev,
475 "Failed data block write, bus error...\n");
476 result = -EINVAL;
477 break;
478 }
479
480 /*
481 * Write CRC
482 */
483 if (spi_priv->crc16_enabled) {
484 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
485 crc[0] = crc_calc >> 8;
486 crc[1] = crc_calc;
487 if (wilc_spi_tx(wilc, crc, 2)) {
488 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
489 result = -EINVAL;
490 break;
491 }
492 }
493
494 /*
495 * No need to wait for response
496 */
497 ix += nbytes;
498 sz -= nbytes;
499 } while (sz);
500
501 return result;
502 }
503
504 /********************************************
505 *
506 * Spi Internal Read/Write Function
507 *
508 ********************************************/
wilc_get_crc7(u8 * buffer,u32 len)509 static u8 wilc_get_crc7(u8 *buffer, u32 len)
510 {
511 return crc7_be(0xfe, buffer, len) | 0x01;
512 }
513
wilc_spi_single_read(struct wilc * wilc,u8 cmd,u32 adr,void * b,u8 clockless)514 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
515 u8 clockless)
516 {
517 struct spi_device *spi = to_spi_device(wilc->dev);
518 struct wilc_spi *spi_priv = wilc->bus_data;
519 u8 wb[32], rb[32];
520 int cmd_len, resp_len, i;
521 u16 crc_calc, crc_recv;
522 struct wilc_spi_cmd *c;
523 struct wilc_spi_rsp_data *r;
524 struct wilc_spi_read_rsp_data *r_data;
525
526 memset(wb, 0x0, sizeof(wb));
527 memset(rb, 0x0, sizeof(rb));
528 c = (struct wilc_spi_cmd *)wb;
529 c->cmd_type = cmd;
530 if (cmd == CMD_SINGLE_READ) {
531 c->u.simple_cmd.addr[0] = adr >> 16;
532 c->u.simple_cmd.addr[1] = adr >> 8;
533 c->u.simple_cmd.addr[2] = adr;
534 } else if (cmd == CMD_INTERNAL_READ) {
535 c->u.simple_cmd.addr[0] = adr >> 8;
536 if (clockless == 1)
537 c->u.simple_cmd.addr[0] |= BIT(7);
538 c->u.simple_cmd.addr[1] = adr;
539 c->u.simple_cmd.addr[2] = 0x0;
540 } else {
541 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
542 return -EINVAL;
543 }
544
545 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
546 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
547
548 if (spi_priv->crc7_enabled) {
549 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
550 cmd_len += 1;
551 resp_len += 2;
552 }
553
554 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
555 dev_err(&spi->dev,
556 "spi buffer size too small (%d) (%d) (%zu)\n",
557 cmd_len, resp_len, ARRAY_SIZE(wb));
558 return -EINVAL;
559 }
560
561 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
562 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
563 return -EINVAL;
564 }
565
566 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
567 if (r->rsp_cmd_type != cmd && !clockless) {
568 if (!spi_priv->probing_crc)
569 dev_err(&spi->dev,
570 "Failed cmd, cmd (%02x), resp (%02x)\n",
571 cmd, r->rsp_cmd_type);
572 return -EINVAL;
573 }
574
575 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
576 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
577 r->status);
578 return -EINVAL;
579 }
580
581 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
582 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
583 break;
584
585 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
586 dev_err(&spi->dev, "Error, data start missing\n");
587 return -EINVAL;
588 }
589
590 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
591
592 if (b)
593 memcpy(b, r_data->data, 4);
594
595 if (!clockless && spi_priv->crc16_enabled) {
596 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
597 crc_calc = crc_itu_t(0xffff, r_data->data, 4);
598 if (crc_recv != crc_calc) {
599 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
600 "(calculated 0x%04x)\n", __func__,
601 crc_recv, crc_calc);
602 return -EINVAL;
603 }
604 }
605
606 return 0;
607 }
608
wilc_spi_write_cmd(struct wilc * wilc,u8 cmd,u32 adr,u32 data,u8 clockless)609 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
610 u8 clockless)
611 {
612 struct spi_device *spi = to_spi_device(wilc->dev);
613 struct wilc_spi *spi_priv = wilc->bus_data;
614 u8 wb[32], rb[32];
615 int cmd_len, resp_len;
616 struct wilc_spi_cmd *c;
617 struct wilc_spi_rsp_data *r;
618
619 memset(wb, 0x0, sizeof(wb));
620 memset(rb, 0x0, sizeof(rb));
621 c = (struct wilc_spi_cmd *)wb;
622 c->cmd_type = cmd;
623 if (cmd == CMD_INTERNAL_WRITE) {
624 c->u.internal_w_cmd.addr[0] = adr >> 8;
625 if (clockless == 1)
626 c->u.internal_w_cmd.addr[0] |= BIT(7);
627
628 c->u.internal_w_cmd.addr[1] = adr;
629 c->u.internal_w_cmd.data = cpu_to_be32(data);
630 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
631 if (spi_priv->crc7_enabled)
632 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
633 } else if (cmd == CMD_SINGLE_WRITE) {
634 c->u.w_cmd.addr[0] = adr >> 16;
635 c->u.w_cmd.addr[1] = adr >> 8;
636 c->u.w_cmd.addr[2] = adr;
637 c->u.w_cmd.data = cpu_to_be32(data);
638 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
639 if (spi_priv->crc7_enabled)
640 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
641 } else {
642 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
643 return -EINVAL;
644 }
645
646 if (spi_priv->crc7_enabled)
647 cmd_len += 1;
648
649 resp_len = sizeof(*r);
650
651 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
652 dev_err(&spi->dev,
653 "spi buffer size too small (%d) (%d) (%zu)\n",
654 cmd_len, resp_len, ARRAY_SIZE(wb));
655 return -EINVAL;
656 }
657
658 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
659 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
660 return -EINVAL;
661 }
662
663 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
664 /*
665 * Clockless registers operations might return unexptected responses,
666 * even if successful.
667 */
668 if (r->rsp_cmd_type != cmd && !clockless) {
669 dev_err(&spi->dev,
670 "Failed cmd response, cmd (%02x), resp (%02x)\n",
671 cmd, r->rsp_cmd_type);
672 return -EINVAL;
673 }
674
675 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
676 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
677 r->status);
678 return -EINVAL;
679 }
680
681 return 0;
682 }
683
wilc_spi_dma_rw(struct wilc * wilc,u8 cmd,u32 adr,u8 * b,u32 sz)684 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
685 {
686 struct spi_device *spi = to_spi_device(wilc->dev);
687 struct wilc_spi *spi_priv = wilc->bus_data;
688 u16 crc_recv, crc_calc;
689 u8 wb[32], rb[32];
690 int cmd_len, resp_len;
691 int retry, ix = 0;
692 u8 crc[2];
693 struct wilc_spi_cmd *c;
694 struct wilc_spi_rsp_data *r;
695
696 memset(wb, 0x0, sizeof(wb));
697 memset(rb, 0x0, sizeof(rb));
698 c = (struct wilc_spi_cmd *)wb;
699 c->cmd_type = cmd;
700 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
701 c->u.dma_cmd.addr[0] = adr >> 16;
702 c->u.dma_cmd.addr[1] = adr >> 8;
703 c->u.dma_cmd.addr[2] = adr;
704 c->u.dma_cmd.size[0] = sz >> 8;
705 c->u.dma_cmd.size[1] = sz;
706 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
707 if (spi_priv->crc7_enabled)
708 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
709 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
710 c->u.dma_cmd_ext.addr[0] = adr >> 16;
711 c->u.dma_cmd_ext.addr[1] = adr >> 8;
712 c->u.dma_cmd_ext.addr[2] = adr;
713 c->u.dma_cmd_ext.size[0] = sz >> 16;
714 c->u.dma_cmd_ext.size[1] = sz >> 8;
715 c->u.dma_cmd_ext.size[2] = sz;
716 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
717 if (spi_priv->crc7_enabled)
718 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
719 } else {
720 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
721 cmd);
722 return -EINVAL;
723 }
724 if (spi_priv->crc7_enabled)
725 cmd_len += 1;
726
727 resp_len = sizeof(*r);
728
729 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
730 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
731 cmd_len, resp_len, ARRAY_SIZE(wb));
732 return -EINVAL;
733 }
734
735 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
736 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
737 return -EINVAL;
738 }
739
740 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
741 if (r->rsp_cmd_type != cmd) {
742 dev_err(&spi->dev,
743 "Failed cmd response, cmd (%02x), resp (%02x)\n",
744 cmd, r->rsp_cmd_type);
745 return -EINVAL;
746 }
747
748 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
749 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
750 r->status);
751 return -EINVAL;
752 }
753
754 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
755 return 0;
756
757 while (sz > 0) {
758 int nbytes;
759 u8 rsp;
760
761 nbytes = min_t(u32, sz, DATA_PKT_SZ);
762
763 /*
764 * Data Response header
765 */
766 retry = 100;
767 do {
768 if (wilc_spi_rx(wilc, &rsp, 1)) {
769 dev_err(&spi->dev,
770 "Failed resp read, bus err\n");
771 return -EINVAL;
772 }
773 if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
774 break;
775 } while (retry--);
776
777 /*
778 * Read bytes
779 */
780 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
781 dev_err(&spi->dev,
782 "Failed block read, bus err\n");
783 return -EINVAL;
784 }
785
786 /*
787 * Read CRC
788 */
789 if (spi_priv->crc16_enabled) {
790 if (wilc_spi_rx(wilc, crc, 2)) {
791 dev_err(&spi->dev,
792 "Failed block CRC read, bus err\n");
793 return -EINVAL;
794 }
795 crc_recv = (crc[0] << 8) | crc[1];
796 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
797 if (crc_recv != crc_calc) {
798 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
799 "(calculated 0x%04x)\n", __func__,
800 crc_recv, crc_calc);
801 return -EINVAL;
802 }
803 }
804
805 ix += nbytes;
806 sz -= nbytes;
807 }
808 return 0;
809 }
810
wilc_spi_special_cmd(struct wilc * wilc,u8 cmd)811 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
812 {
813 struct spi_device *spi = to_spi_device(wilc->dev);
814 struct wilc_spi *spi_priv = wilc->bus_data;
815 u8 wb[32], rb[32];
816 int cmd_len, resp_len = 0;
817 struct wilc_spi_cmd *c;
818 struct wilc_spi_special_cmd_rsp *r;
819
820 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
821 return -EINVAL;
822
823 memset(wb, 0x0, sizeof(wb));
824 memset(rb, 0x0, sizeof(rb));
825 c = (struct wilc_spi_cmd *)wb;
826 c->cmd_type = cmd;
827
828 if (cmd == CMD_RESET)
829 memset(c->u.simple_cmd.addr, 0xFF, 3);
830
831 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
832 resp_len = sizeof(*r);
833
834 if (spi_priv->crc7_enabled) {
835 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
836 cmd_len += 1;
837 }
838 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
839 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
840 cmd_len, resp_len, ARRAY_SIZE(wb));
841 return -EINVAL;
842 }
843
844 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
845 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
846 return -EINVAL;
847 }
848
849 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
850 if (r->rsp_cmd_type != cmd) {
851 if (!spi_priv->probing_crc)
852 dev_err(&spi->dev,
853 "Failed cmd response, cmd (%02x), resp (%02x)\n",
854 cmd, r->rsp_cmd_type);
855 return -EINVAL;
856 }
857
858 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
859 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
860 r->status);
861 return -EINVAL;
862 }
863 return 0;
864 }
865
wilc_spi_reset_cmd_sequence(struct wilc * wl,u8 attempt,u32 addr)866 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr)
867 {
868 struct spi_device *spi = to_spi_device(wl->dev);
869 struct wilc_spi *spi_priv = wl->bus_data;
870
871 if (!spi_priv->probing_crc)
872 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr);
873
874 usleep_range(1000, 1100);
875 wilc_spi_reset(wl);
876 usleep_range(1000, 1100);
877 }
878
wilc_spi_read_reg(struct wilc * wilc,u32 addr,u32 * data)879 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
880 {
881 struct spi_device *spi = to_spi_device(wilc->dev);
882 int result;
883 u8 cmd = CMD_SINGLE_READ;
884 u8 clockless = 0;
885 u8 i;
886
887 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
888 /* Clockless register */
889 cmd = CMD_INTERNAL_READ;
890 clockless = 1;
891 }
892
893 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
894 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
895 if (!result) {
896 le32_to_cpus(data);
897 return 0;
898 }
899
900 /* retry is not applicable for clockless registers */
901 if (clockless)
902 break;
903
904 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
905 wilc_spi_reset_cmd_sequence(wilc, i, addr);
906 }
907
908 return result;
909 }
910
wilc_spi_read(struct wilc * wilc,u32 addr,u8 * buf,u32 size)911 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
912 {
913 struct spi_device *spi = to_spi_device(wilc->dev);
914 int result;
915 u8 i;
916
917 if (size <= 4)
918 return -EINVAL;
919
920 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
921 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr,
922 buf, size);
923 if (!result)
924 return 0;
925
926 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
927
928 wilc_spi_reset_cmd_sequence(wilc, i, addr);
929 }
930
931 return result;
932 }
933
spi_internal_write(struct wilc * wilc,u32 adr,u32 dat)934 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
935 {
936 struct spi_device *spi = to_spi_device(wilc->dev);
937 int result;
938 u8 i;
939
940 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
941 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr,
942 dat, 0);
943 if (!result)
944 return 0;
945 dev_err(&spi->dev, "Failed internal write cmd...\n");
946
947 wilc_spi_reset_cmd_sequence(wilc, i, adr);
948 }
949
950 return result;
951 }
952
spi_internal_read(struct wilc * wilc,u32 adr,u32 * data)953 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
954 {
955 struct spi_device *spi = to_spi_device(wilc->dev);
956 struct wilc_spi *spi_priv = wilc->bus_data;
957 int result;
958 u8 i;
959
960 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
961 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr,
962 data, 0);
963 if (!result) {
964 le32_to_cpus(data);
965 return 0;
966 }
967 if (!spi_priv->probing_crc)
968 dev_err(&spi->dev, "Failed internal read cmd...\n");
969
970 wilc_spi_reset_cmd_sequence(wilc, i, adr);
971 }
972
973 return result;
974 }
975
976 /********************************************
977 *
978 * Spi interfaces
979 *
980 ********************************************/
981
wilc_spi_write_reg(struct wilc * wilc,u32 addr,u32 data)982 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
983 {
984 struct spi_device *spi = to_spi_device(wilc->dev);
985 int result;
986 u8 cmd = CMD_SINGLE_WRITE;
987 u8 clockless = 0;
988 u8 i;
989
990 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
991 /* Clockless register */
992 cmd = CMD_INTERNAL_WRITE;
993 clockless = 1;
994 }
995
996 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
997 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
998 if (!result)
999 return 0;
1000
1001 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
1002
1003 if (clockless)
1004 break;
1005
1006 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1007 }
1008 return result;
1009 }
1010
spi_data_rsp(struct wilc * wilc,u8 cmd)1011 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
1012 {
1013 struct spi_device *spi = to_spi_device(wilc->dev);
1014 int result, i;
1015 u8 rsp[4];
1016
1017 /*
1018 * The response to data packets is two bytes long. For
1019 * efficiency's sake, wilc_spi_write() wisely ignores the
1020 * responses for all packets but the final one. The downside
1021 * of that optimization is that when the final data packet is
1022 * short, we may receive (part of) the response to the
1023 * second-to-last packet before the one for the final packet.
1024 * To handle this, we always read 4 bytes and then search for
1025 * the last byte that contains the "Response Start" code (0xc
1026 * in the top 4 bits). We then know that this byte is the
1027 * first response byte of the final data packet.
1028 */
1029 result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
1030 if (result) {
1031 dev_err(&spi->dev, "Failed bus error...\n");
1032 return result;
1033 }
1034
1035 for (i = sizeof(rsp) - 2; i >= 0; --i)
1036 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
1037 break;
1038
1039 if (i < 0) {
1040 dev_err(&spi->dev,
1041 "Data packet response missing (%02x %02x %02x %02x)\n",
1042 rsp[0], rsp[1], rsp[2], rsp[3]);
1043 return -1;
1044 }
1045
1046 /* rsp[i] is the last response start byte */
1047
1048 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
1049 || rsp[i + 1] != RSP_STATE_NO_ERROR) {
1050 dev_err(&spi->dev, "Data response error (%02x %02x)\n",
1051 rsp[i], rsp[i + 1]);
1052 return -1;
1053 }
1054 return 0;
1055 }
1056
wilc_spi_write(struct wilc * wilc,u32 addr,u8 * buf,u32 size)1057 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
1058 {
1059 struct spi_device *spi = to_spi_device(wilc->dev);
1060 int result;
1061 u8 i;
1062
1063 /*
1064 * has to be greated than 4
1065 */
1066 if (size <= 4)
1067 return -EINVAL;
1068
1069 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) {
1070 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr,
1071 NULL, size);
1072 if (result) {
1073 dev_err(&spi->dev,
1074 "Failed cmd, write block (%08x)...\n", addr);
1075 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1076 continue;
1077 }
1078
1079 /*
1080 * Data
1081 */
1082 result = spi_data_write(wilc, buf, size);
1083 if (result) {
1084 dev_err(&spi->dev, "Failed block data write...\n");
1085 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1086 continue;
1087 }
1088
1089 /*
1090 * Data response
1091 */
1092 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1093 if (result) {
1094 dev_err(&spi->dev, "Failed block data rsp...\n");
1095 wilc_spi_reset_cmd_sequence(wilc, i, addr);
1096 continue;
1097 }
1098 break;
1099 }
1100 return result;
1101 }
1102
1103 /********************************************
1104 *
1105 * Bus interfaces
1106 *
1107 ********************************************/
1108
wilc_spi_reset(struct wilc * wilc)1109 static int wilc_spi_reset(struct wilc *wilc)
1110 {
1111 struct spi_device *spi = to_spi_device(wilc->dev);
1112 struct wilc_spi *spi_priv = wilc->bus_data;
1113 int result;
1114
1115 result = wilc_spi_special_cmd(wilc, CMD_RESET);
1116 if (result && !spi_priv->probing_crc)
1117 dev_err(&spi->dev, "Failed cmd reset\n");
1118
1119 return result;
1120 }
1121
wilc_spi_is_init(struct wilc * wilc)1122 static bool wilc_spi_is_init(struct wilc *wilc)
1123 {
1124 struct wilc_spi *spi_priv = wilc->bus_data;
1125
1126 return spi_priv->isinit;
1127 }
1128
wilc_spi_deinit(struct wilc * wilc)1129 static int wilc_spi_deinit(struct wilc *wilc)
1130 {
1131 struct wilc_spi *spi_priv = wilc->bus_data;
1132
1133 spi_priv->isinit = false;
1134 wilc_wlan_power(wilc, false);
1135 return 0;
1136 }
1137
wilc_spi_init(struct wilc * wilc,bool resume)1138 static int wilc_spi_init(struct wilc *wilc, bool resume)
1139 {
1140 struct wilc_spi *spi_priv = wilc->bus_data;
1141 int ret;
1142
1143 if (spi_priv->isinit) {
1144 /* Confirm we can read chipid register without error: */
1145 if (wilc_validate_chipid(wilc) == 0)
1146 return 0;
1147 }
1148
1149 wilc_wlan_power(wilc, true);
1150
1151 ret = wilc_spi_configure_bus_protocol(wilc);
1152 if (ret) {
1153 wilc_wlan_power(wilc, false);
1154 return ret;
1155 }
1156
1157 spi_priv->isinit = true;
1158
1159 return 0;
1160 }
1161
wilc_spi_configure_bus_protocol(struct wilc * wilc)1162 static int wilc_spi_configure_bus_protocol(struct wilc *wilc)
1163 {
1164 struct spi_device *spi = to_spi_device(wilc->dev);
1165 struct wilc_spi *spi_priv = wilc->bus_data;
1166 u32 reg;
1167 int ret, i;
1168
1169 /*
1170 * Infer the CRC settings that are currently in effect. This
1171 * is necessary because we can't be sure that the chip has
1172 * been RESET (e.g, after module unload and reload).
1173 */
1174 spi_priv->probing_crc = true;
1175 spi_priv->crc7_enabled = enable_crc7;
1176 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1177 for (i = 0; i < 2; ++i) {
1178 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1179 if (ret == 0)
1180 break;
1181 spi_priv->crc7_enabled = !enable_crc7;
1182 }
1183 if (ret) {
1184 dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1185 return ret;
1186 }
1187
1188 /* set up the desired CRC configuration: */
1189 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1190 if (enable_crc7)
1191 reg |= PROTOCOL_REG_CRC7_MASK;
1192 if (enable_crc16)
1193 reg |= PROTOCOL_REG_CRC16_MASK;
1194
1195 /* set up the data packet size: */
1196 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1197 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1198 reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1199 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1200 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1201
1202 /* establish the new setup: */
1203 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1204 if (ret) {
1205 dev_err(&spi->dev,
1206 "[wilc spi %d]: Failed internal write reg\n",
1207 __LINE__);
1208 return ret;
1209 }
1210 /* update our state to match new protocol settings: */
1211 spi_priv->crc7_enabled = enable_crc7;
1212 spi_priv->crc16_enabled = enable_crc16;
1213
1214 /* re-read to make sure new settings are in effect: */
1215 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1216
1217 spi_priv->probing_crc = false;
1218
1219 return 0;
1220 }
1221
wilc_validate_chipid(struct wilc * wilc)1222 static int wilc_validate_chipid(struct wilc *wilc)
1223 {
1224 struct spi_device *spi = to_spi_device(wilc->dev);
1225 u32 chipid;
1226 int ret;
1227
1228 /*
1229 * make sure can read chip id without protocol error
1230 */
1231 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1232 if (ret) {
1233 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1234 return ret;
1235 }
1236 if (!is_wilc1000(chipid) && !is_wilc3000(chipid)) {
1237 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid);
1238 return -ENODEV;
1239 }
1240 return 0;
1241 }
1242
wilc_spi_read_size(struct wilc * wilc,u32 * size)1243 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1244 {
1245 int ret;
1246
1247 ret = spi_internal_read(wilc,
1248 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1249 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1250
1251 return ret;
1252 }
1253
wilc_spi_read_int(struct wilc * wilc,u32 * int_status)1254 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1255 {
1256 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1257 int_status);
1258 }
1259
wilc_spi_clear_int_ext(struct wilc * wilc,u32 val)1260 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1261 {
1262 int ret;
1263 int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1264 u32 check;
1265
1266 while (retry) {
1267 ret = spi_internal_write(wilc,
1268 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1269 val);
1270 if (ret)
1271 break;
1272
1273 ret = spi_internal_read(wilc,
1274 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1275 &check);
1276 if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1277 break;
1278
1279 retry--;
1280 }
1281 return ret;
1282 }
1283
wilc_spi_sync_ext(struct wilc * wilc,int nint)1284 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1285 {
1286 struct spi_device *spi = to_spi_device(wilc->dev);
1287 u32 reg;
1288 int ret, i;
1289
1290 if (nint > MAX_NUM_INT) {
1291 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1292 return -EINVAL;
1293 }
1294
1295 /*
1296 * interrupt pin mux select
1297 */
1298 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1299 if (ret) {
1300 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1301 WILC_PIN_MUX_0);
1302 return ret;
1303 }
1304 reg |= BIT(8);
1305 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1306 if (ret) {
1307 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1308 WILC_PIN_MUX_0);
1309 return ret;
1310 }
1311
1312 /*
1313 * interrupt enable
1314 */
1315 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1316 if (ret) {
1317 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1318 WILC_INTR_ENABLE);
1319 return ret;
1320 }
1321
1322 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1323 reg |= (BIT((27 + i)));
1324
1325 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1326 if (ret) {
1327 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1328 WILC_INTR_ENABLE);
1329 return ret;
1330 }
1331 if (nint) {
1332 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1333 if (ret) {
1334 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1335 WILC_INTR2_ENABLE);
1336 return ret;
1337 }
1338
1339 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1340 reg |= BIT(i);
1341
1342 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1343 if (ret) {
1344 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1345 WILC_INTR2_ENABLE);
1346 return ret;
1347 }
1348 }
1349
1350 return 0;
1351 }
1352
1353 /* Global spi HIF function table */
1354 static const struct wilc_hif_func wilc_hif_spi = {
1355 .hif_init = wilc_spi_init,
1356 .hif_deinit = wilc_spi_deinit,
1357 .hif_read_reg = wilc_spi_read_reg,
1358 .hif_write_reg = wilc_spi_write_reg,
1359 .hif_block_rx = wilc_spi_read,
1360 .hif_block_tx = wilc_spi_write,
1361 .hif_read_int = wilc_spi_read_int,
1362 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1363 .hif_read_size = wilc_spi_read_size,
1364 .hif_block_tx_ext = wilc_spi_write,
1365 .hif_block_rx_ext = wilc_spi_read,
1366 .hif_sync_ext = wilc_spi_sync_ext,
1367 .hif_reset = wilc_spi_reset,
1368 .hif_is_init = wilc_spi_is_init,
1369 };
1370