1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */ 2 /* 3 * Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike 4 * other architectures, the ebreak instruction has no immediate field for 5 * distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. 6 * "csrw mhartid, x0" can also satisfy the RSEQ requirement because it 7 * is an uncommon instruction and will raise an illegal instruction 8 * exception when executed in all modes. 9 */ 10 #include <endian.h> 11 #include <asm/fence.h> 12 13 #if defined(__BYTE_ORDER) ? (__BYTE_ORDER == __LITTLE_ENDIAN) : defined(__LITTLE_ENDIAN) 14 #define RSEQ_SIG 0xf1401073 /* csrr mhartid, x0 */ 15 #else 16 #error "Currently, RSEQ only supports Little-Endian version" 17 #endif 18 19 #if __riscv_xlen == 64 20 #define __REG_SEL(a, b) a 21 #elif __riscv_xlen == 32 22 #define __REG_SEL(a, b) b 23 #endif 24 25 #define REG_L __REG_SEL("ld ", "lw ") 26 #define REG_S __REG_SEL("sd ", "sw ") 27 28 #define rseq_smp_mb() RISCV_FENCE(rw, rw) 29 #define rseq_smp_rmb() RISCV_FENCE(r, r) 30 #define rseq_smp_wmb() RISCV_FENCE(w, w) 31 #define RSEQ_ASM_TMP_REG_1 "t6" 32 #define RSEQ_ASM_TMP_REG_2 "t5" 33 #define RSEQ_ASM_TMP_REG_3 "t4" 34 #define RSEQ_ASM_TMP_REG_4 "t3" 35 36 #define rseq_smp_load_acquire(p) \ 37 __extension__ ({ \ 38 rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \ 39 RISCV_FENCE(r, rw); \ 40 ____p1; \ 41 }) 42 43 #define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb() 44 45 #define rseq_smp_store_release(p, v) \ 46 do { \ 47 RISCV_FENCE(rw, w); \ 48 RSEQ_WRITE_ONCE(*(p), v); \ 49 } while (0) 50 51 #define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \ 52 post_commit_offset, abort_ip) \ 53 ".pushsection __rseq_cs, \"aw\"\n" \ 54 ".balign 32\n" \ 55 __rseq_str(label) ":\n" \ 56 ".long " __rseq_str(version) ", " __rseq_str(flags) "\n" \ 57 ".quad " __rseq_str(start_ip) ", " \ 58 __rseq_str(post_commit_offset) ", " \ 59 __rseq_str(abort_ip) "\n" \ 60 ".popsection\n\t" \ 61 ".pushsection __rseq_cs_ptr_array, \"aw\"\n" \ 62 ".quad " __rseq_str(label) "b\n" \ 63 ".popsection\n" 64 65 #define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \ 66 __RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \ 67 ((post_commit_ip) - (start_ip)), abort_ip) 68 69 /* 70 * Exit points of a rseq critical section consist of all instructions outside 71 * of the critical section where a critical section can either branch to or 72 * reach through the normal course of its execution. The abort IP and the 73 * post-commit IP are already part of the __rseq_cs section and should not be 74 * explicitly defined as additional exit points. Knowing all exit points is 75 * useful to assist debuggers stepping over the critical section. 76 */ 77 #define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \ 78 ".pushsection __rseq_exit_point_array, \"aw\"\n" \ 79 ".quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \ 80 ".popsection\n" 81 82 #define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \ 83 RSEQ_INJECT_ASM(1) \ 84 "la " RSEQ_ASM_TMP_REG_1 ", " __rseq_str(cs_label) "\n" \ 85 REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(rseq_cs) "]\n" \ 86 __rseq_str(label) ":\n" 87 88 #define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \ 89 "j 222f\n" \ 90 ".balign 4\n" \ 91 ".long " __rseq_str(RSEQ_SIG) "\n" \ 92 __rseq_str(label) ":\n" \ 93 "j %l[" __rseq_str(abort_label) "]\n" \ 94 "222:\n" 95 96 #define RSEQ_ASM_OP_STORE(value, var) \ 97 REG_S "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n" 98 99 #define RSEQ_ASM_OP_CMPEQ(var, expect, label) \ 100 REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ 101 "bne " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ 102 __rseq_str(label) "\n" 103 104 #define RSEQ_ASM_OP_CMPEQ32(var, expect, label) \ 105 "lw " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ 106 "bne " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ 107 __rseq_str(label) "\n" 108 109 #define RSEQ_ASM_OP_CMPNE(var, expect, label) \ 110 REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ 111 "beq " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "] ," \ 112 __rseq_str(label) "\n" 113 114 #define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \ 115 RSEQ_INJECT_ASM(2) \ 116 RSEQ_ASM_OP_CMPEQ32(current_cpu_id, cpu_id, label) 117 118 #define RSEQ_ASM_OP_R_LOAD(var) \ 119 REG_L RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" 120 121 #define RSEQ_ASM_OP_R_STORE(var) \ 122 REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" 123 124 #define RSEQ_ASM_OP_R_LOAD_OFF(offset) \ 125 "add " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(offset) "], " \ 126 RSEQ_ASM_TMP_REG_1 "\n" \ 127 REG_L RSEQ_ASM_TMP_REG_1 ", (" RSEQ_ASM_TMP_REG_1 ")\n" 128 129 #define RSEQ_ASM_OP_R_ADD(count) \ 130 "add " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \ 131 ", %[" __rseq_str(count) "]\n" 132 133 #define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \ 134 RSEQ_ASM_OP_STORE(value, var) \ 135 __rseq_str(post_commit_label) ":\n" 136 137 #define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \ 138 "fence rw, w\n" \ 139 RSEQ_ASM_OP_STORE(value, var) \ 140 __rseq_str(post_commit_label) ":\n" 141 142 #define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \ 143 REG_S RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \ 144 __rseq_str(post_commit_label) ":\n" 145 146 #define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \ 147 "beqz %[" __rseq_str(len) "], 333f\n" \ 148 "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "]\n" \ 149 "mv " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "]\n" \ 150 "mv " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "]\n" \ 151 "222:\n" \ 152 "lb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n" \ 153 "sb " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_3 ")\n" \ 154 "addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n" \ 155 "addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n" \ 156 "addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n" \ 157 "bnez " RSEQ_ASM_TMP_REG_1 ", 222b\n" \ 158 "333:\n" 159 160 #define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \ 161 "mv " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "]\n" \ 162 RSEQ_ASM_OP_R_ADD(off) \ 163 REG_L RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \ 164 RSEQ_ASM_OP_R_ADD(inc) \ 165 __rseq_str(post_commit_label) ":\n" 166 167 /* Per-cpu-id indexing. */ 168 169 #define RSEQ_TEMPLATE_CPU_ID 170 #define RSEQ_TEMPLATE_MO_RELAXED 171 #include "rseq-riscv-bits.h" 172 #undef RSEQ_TEMPLATE_MO_RELAXED 173 174 #define RSEQ_TEMPLATE_MO_RELEASE 175 #include "rseq-riscv-bits.h" 176 #undef RSEQ_TEMPLATE_MO_RELEASE 177 #undef RSEQ_TEMPLATE_CPU_ID 178 179 /* Per-mm-cid indexing. */ 180 181 #define RSEQ_TEMPLATE_MM_CID 182 #define RSEQ_TEMPLATE_MO_RELAXED 183 #include "rseq-riscv-bits.h" 184 #undef RSEQ_TEMPLATE_MO_RELAXED 185 186 #define RSEQ_TEMPLATE_MO_RELEASE 187 #include "rseq-riscv-bits.h" 188 #undef RSEQ_TEMPLATE_MO_RELEASE 189 #undef RSEQ_TEMPLATE_MM_CID 190 191 /* APIs which are not based on cpu ids. */ 192 193 #define RSEQ_TEMPLATE_CPU_ID_NONE 194 #define RSEQ_TEMPLATE_MO_RELAXED 195 #include "rseq-riscv-bits.h" 196 #undef RSEQ_TEMPLATE_MO_RELAXED 197 #undef RSEQ_TEMPLATE_CPU_ID_NONE 198