xref: /linux/drivers/net/ethernet/atheros/alx/hw.h (revision 9095bf25ea08135a5b74875dd0e3eeaddc4218a0) 
1 /*
2  * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
3  *
4  *  This file is free software: you may copy, redistribute and/or modify it
5  *  under the terms of the GNU General Public License as published by the
6  *  Free Software Foundation, either version 2 of the License, or (at your
7  *  option) any later version.
8  *
9  *  This file is distributed in the hope that it will be useful, but
10  *  WITHOUT ANY WARRANTY; without even the implied warranty of
11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12  *  General Public License for more details.
13  *
14  *  You should have received a copy of the GNU General Public License
15  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  *
17  * This file incorporates work covered by the following copyright and
18  * permission notice:
19  *
20  * Copyright (c) 2012 Qualcomm Atheros, Inc.
21  *
22  * Permission to use, copy, modify, and/or distribute this software for any
23  * purpose with or without fee is hereby granted, provided that the above
24  * copyright notice and this permission notice appear in all copies.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
33  */
34 
35 #ifndef ALX_HW_H_
36 #define ALX_HW_H_
37 #include <linux/types.h>
38 #include <linux/mdio.h>
39 #include <linux/pci.h>
40 #include <linux/if_vlan.h>
41 #include "reg.h"
42 
43 /* Transmit Packet Descriptor, contains 4 32-bit words.
44  *
45  *   31               16               0
46  *   +----------------+----------------+
47  *   |    vlan-tag    |   buf length   |
48  *   +----------------+----------------+
49  *   |              Word 1             |
50  *   +----------------+----------------+
51  *   |      Word 2: buf addr lo        |
52  *   +----------------+----------------+
53  *   |      Word 3: buf addr hi        |
54  *   +----------------+----------------+
55  *
56  * Word 2 and 3 combine to form a 64-bit buffer address
57  *
58  * Word 1 has three forms, depending on the state of bit 8/12/13:
59  * if bit8 =='1', the definition is just for custom checksum offload.
60  * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
61  *     for the skb is special for LSO V2, Word 2 become total skb length ,
62  *     Word 3 is meaningless.
63  * other condition, the definition is for general skb or ip/tcp/udp
64  *     checksum or LSO(TSO) offload.
65  *
66  * Here is the depiction:
67  *
68  *   0-+                                  0-+
69  *   1 |                                  1 |
70  *   2 |                                  2 |
71  *   3 |    Payload offset                3 |    L4 header offset
72  *   4 |        (7:0)                     4 |        (7:0)
73  *   5 |                                  5 |
74  *   6 |                                  6 |
75  *   7-+                                  7-+
76  *   8      Custom csum enable = 1        8      Custom csum enable = 0
77  *   9      General IPv4 checksum         9      General IPv4 checksum
78  *   10     General TCP checksum          10     General TCP checksum
79  *   11     General UDP checksum          11     General UDP checksum
80  *   12     Large Send Segment enable     12     Large Send Segment enable
81  *   13     Large Send Segment type       13     Large Send Segment type
82  *   14     VLAN tagged                   14     VLAN tagged
83  *   15     Insert VLAN tag               15     Insert VLAN tag
84  *   16     IPv4 packet                   16     IPv4 packet
85  *   17     Ethernet frame type           17     Ethernet frame type
86  *   18-+                                 18-+
87  *   19 |                                 19 |
88  *   20 |                                 20 |
89  *   21 |   Custom csum offset            21 |
90  *   22 |       (25:18)                   22 |
91  *   23 |                                 23 |   MSS (30:18)
92  *   24 |                                 24 |
93  *   25-+                                 25 |
94  *   26-+                                 26 |
95  *   27 |                                 27 |
96  *   28 |   Reserved                      28 |
97  *   29 |                                 29 |
98  *   30-+                                 30-+
99  *   31     End of packet                 31     End of packet
100  */
101 struct alx_txd {
102 	__le16 len;
103 	__le16 vlan_tag;
104 	__le32 word1;
105 	union {
106 		__le64 addr;
107 		struct {
108 			__le32 pkt_len;
109 			__le32 resvd;
110 		} l;
111 	} adrl;
112 } __packed;
113 
114 /* tpd word 1 */
115 #define TPD_CXSUMSTART_MASK		0x00FF
116 #define TPD_CXSUMSTART_SHIFT		0
117 #define TPD_L4HDROFFSET_MASK		0x00FF
118 #define TPD_L4HDROFFSET_SHIFT		0
119 #define TPD_CXSUM_EN_MASK		0x0001
120 #define TPD_CXSUM_EN_SHIFT		8
121 #define TPD_IP_XSUM_MASK		0x0001
122 #define TPD_IP_XSUM_SHIFT		9
123 #define TPD_TCP_XSUM_MASK		0x0001
124 #define TPD_TCP_XSUM_SHIFT		10
125 #define TPD_UDP_XSUM_MASK		0x0001
126 #define TPD_UDP_XSUM_SHIFT		11
127 #define TPD_LSO_EN_MASK			0x0001
128 #define TPD_LSO_EN_SHIFT		12
129 #define TPD_LSO_V2_MASK			0x0001
130 #define TPD_LSO_V2_SHIFT		13
131 #define TPD_VLTAGGED_MASK		0x0001
132 #define TPD_VLTAGGED_SHIFT		14
133 #define TPD_INS_VLTAG_MASK		0x0001
134 #define TPD_INS_VLTAG_SHIFT		15
135 #define TPD_IPV4_MASK			0x0001
136 #define TPD_IPV4_SHIFT			16
137 #define TPD_ETHTYPE_MASK		0x0001
138 #define TPD_ETHTYPE_SHIFT		17
139 #define TPD_CXSUMOFFSET_MASK		0x00FF
140 #define TPD_CXSUMOFFSET_SHIFT		18
141 #define TPD_MSS_MASK			0x1FFF
142 #define TPD_MSS_SHIFT			18
143 #define TPD_EOP_MASK			0x0001
144 #define TPD_EOP_SHIFT			31
145 
146 #define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
147 
148 /* Receive Free Descriptor */
149 struct alx_rfd {
150 	__le64 addr;		/* data buffer address, length is
151 				 * declared in register --- every
152 				 * buffer has the same size
153 				 */
154 } __packed;
155 
156 /* Receive Return Descriptor, contains 4 32-bit words.
157  *
158  *   31               16               0
159  *   +----------------+----------------+
160  *   |              Word 0             |
161  *   +----------------+----------------+
162  *   |     Word 1: RSS Hash value      |
163  *   +----------------+----------------+
164  *   |              Word 2             |
165  *   +----------------+----------------+
166  *   |              Word 3             |
167  *   +----------------+----------------+
168  *
169  * Word 0 depiction         &            Word 2 depiction:
170  *
171  *   0--+                                 0--+
172  *   1  |                                 1  |
173  *   2  |                                 2  |
174  *   3  |                                 3  |
175  *   4  |                                 4  |
176  *   5  |                                 5  |
177  *   6  |                                 6  |
178  *   7  |    IP payload checksum          7  |     VLAN tag
179  *   8  |         (15:0)                  8  |      (15:0)
180  *   9  |                                 9  |
181  *   10 |                                 10 |
182  *   11 |                                 11 |
183  *   12 |                                 12 |
184  *   13 |                                 13 |
185  *   14 |                                 14 |
186  *   15-+                                 15-+
187  *   16-+                                 16-+
188  *   17 |     Number of RFDs              17 |
189  *   18 |        (19:16)                  18 |
190  *   19-+                                 19 |     Protocol ID
191  *   20-+                                 20 |      (23:16)
192  *   21 |                                 21 |
193  *   22 |                                 22 |
194  *   23 |                                 23-+
195  *   24 |                                 24 |     Reserved
196  *   25 |     Start index of RFD-ring     25-+
197  *   26 |         (31:20)                 26 |     RSS Q-num (27:25)
198  *   27 |                                 27-+
199  *   28 |                                 28-+
200  *   29 |                                 29 |     RSS Hash algorithm
201  *   30 |                                 30 |      (31:28)
202  *   31-+                                 31-+
203  *
204  * Word 3 depiction:
205  *
206  *   0--+
207  *   1  |
208  *   2  |
209  *   3  |
210  *   4  |
211  *   5  |
212  *   6  |
213  *   7  |    Packet length (include FCS)
214  *   8  |         (13:0)
215  *   9  |
216  *   10 |
217  *   11 |
218  *   12 |
219  *   13-+
220  *   14      L4 Header checksum error
221  *   15      IPv4 checksum error
222  *   16      VLAN tagged
223  *   17-+
224  *   18 |    Protocol ID (19:17)
225  *   19-+
226  *   20      Receive error summary
227  *   21      FCS(CRC) error
228  *   22      Frame alignment error
229  *   23      Truncated packet
230  *   24      Runt packet
231  *   25      Incomplete packet due to insufficient rx-desc
232  *   26      Broadcast packet
233  *   27      Multicast packet
234  *   28      Ethernet type (EII or 802.3)
235  *   29      FIFO overflow
236  *   30      Length error (for 802.3, length field mismatch with actual len)
237  *   31      Updated, indicate to driver that this RRD is refreshed.
238  */
239 struct alx_rrd {
240 	__le32 word0;
241 	__le32 rss_hash;
242 	__le32 word2;
243 	__le32 word3;
244 } __packed;
245 
246 /* rrd word 0 */
247 #define RRD_XSUM_MASK		0xFFFF
248 #define RRD_XSUM_SHIFT		0
249 #define RRD_NOR_MASK		0x000F
250 #define RRD_NOR_SHIFT		16
251 #define RRD_SI_MASK		0x0FFF
252 #define RRD_SI_SHIFT		20
253 
254 /* rrd word 2 */
255 #define RRD_VLTAG_MASK		0xFFFF
256 #define RRD_VLTAG_SHIFT		0
257 #define RRD_PID_MASK		0x00FF
258 #define RRD_PID_SHIFT		16
259 /* non-ip packet */
260 #define RRD_PID_NONIP		0
261 /* ipv4(only) */
262 #define RRD_PID_IPV4		1
263 /* tcp/ipv6 */
264 #define RRD_PID_IPV6TCP		2
265 /* tcp/ipv4 */
266 #define RRD_PID_IPV4TCP		3
267 /* udp/ipv6 */
268 #define RRD_PID_IPV6UDP		4
269 /* udp/ipv4 */
270 #define RRD_PID_IPV4UDP		5
271 /* ipv6(only) */
272 #define RRD_PID_IPV6		6
273 /* LLDP packet */
274 #define RRD_PID_LLDP		7
275 /* 1588 packet */
276 #define RRD_PID_1588		8
277 #define RRD_RSSQ_MASK		0x0007
278 #define RRD_RSSQ_SHIFT		25
279 #define RRD_RSSALG_MASK		0x000F
280 #define RRD_RSSALG_SHIFT	28
281 #define RRD_RSSALG_TCPV6	0x1
282 #define RRD_RSSALG_IPV6		0x2
283 #define RRD_RSSALG_TCPV4	0x4
284 #define RRD_RSSALG_IPV4		0x8
285 
286 /* rrd word 3 */
287 #define RRD_PKTLEN_MASK		0x3FFF
288 #define RRD_PKTLEN_SHIFT	0
289 #define RRD_ERR_L4_MASK		0x0001
290 #define RRD_ERR_L4_SHIFT	14
291 #define RRD_ERR_IPV4_MASK	0x0001
292 #define RRD_ERR_IPV4_SHIFT	15
293 #define RRD_VLTAGGED_MASK	0x0001
294 #define RRD_VLTAGGED_SHIFT	16
295 #define RRD_OLD_PID_MASK	0x0007
296 #define RRD_OLD_PID_SHIFT	17
297 #define RRD_ERR_RES_MASK	0x0001
298 #define RRD_ERR_RES_SHIFT	20
299 #define RRD_ERR_FCS_MASK	0x0001
300 #define RRD_ERR_FCS_SHIFT	21
301 #define RRD_ERR_FAE_MASK	0x0001
302 #define RRD_ERR_FAE_SHIFT	22
303 #define RRD_ERR_TRUNC_MASK	0x0001
304 #define RRD_ERR_TRUNC_SHIFT	23
305 #define RRD_ERR_RUNT_MASK	0x0001
306 #define RRD_ERR_RUNT_SHIFT	24
307 #define RRD_ERR_ICMP_MASK	0x0001
308 #define RRD_ERR_ICMP_SHIFT	25
309 #define RRD_BCAST_MASK		0x0001
310 #define RRD_BCAST_SHIFT		26
311 #define RRD_MCAST_MASK		0x0001
312 #define RRD_MCAST_SHIFT		27
313 #define RRD_ETHTYPE_MASK	0x0001
314 #define RRD_ETHTYPE_SHIFT	28
315 #define RRD_ERR_FIFOV_MASK	0x0001
316 #define RRD_ERR_FIFOV_SHIFT	29
317 #define RRD_ERR_LEN_MASK	0x0001
318 #define RRD_ERR_LEN_SHIFT	30
319 #define RRD_UPDATED_MASK	0x0001
320 #define RRD_UPDATED_SHIFT	31
321 
322 
323 #define ALX_MAX_SETUP_LNK_CYCLE	50
324 
325 /* for FlowControl */
326 #define ALX_FC_RX		0x01
327 #define ALX_FC_TX		0x02
328 #define ALX_FC_ANEG		0x04
329 
330 /* for sleep control */
331 #define ALX_SLEEP_WOL_PHY	0x00000001
332 #define ALX_SLEEP_WOL_MAGIC	0x00000002
333 #define ALX_SLEEP_CIFS		0x00000004
334 #define ALX_SLEEP_ACTIVE	(ALX_SLEEP_WOL_PHY | \
335 				 ALX_SLEEP_WOL_MAGIC | \
336 				 ALX_SLEEP_CIFS)
337 
338 /* for RSS hash type */
339 #define ALX_RSS_HASH_TYPE_IPV4		0x1
340 #define ALX_RSS_HASH_TYPE_IPV4_TCP	0x2
341 #define ALX_RSS_HASH_TYPE_IPV6		0x4
342 #define ALX_RSS_HASH_TYPE_IPV6_TCP	0x8
343 #define ALX_RSS_HASH_TYPE_ALL		(ALX_RSS_HASH_TYPE_IPV4 | \
344 					 ALX_RSS_HASH_TYPE_IPV4_TCP | \
345 					 ALX_RSS_HASH_TYPE_IPV6 | \
346 					 ALX_RSS_HASH_TYPE_IPV6_TCP)
347 #define ALX_FRAME_PAD		16
348 #define ALX_RAW_MTU(_mtu)	(_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
349 #define ALX_MAX_FRAME_LEN(_mtu)	(ALIGN((ALX_RAW_MTU(_mtu) + ALX_FRAME_PAD), 8))
350 #define ALX_DEF_RXBUF_SIZE	ALX_MAX_FRAME_LEN(1500)
351 #define ALX_MAX_JUMBO_PKT_SIZE	(9*1024)
352 #define ALX_MAX_TSO_PKT_SIZE	(7*1024)
353 #define ALX_MAX_FRAME_SIZE	ALX_MAX_JUMBO_PKT_SIZE
354 
355 #define ALX_MAX_RX_QUEUES	8
356 #define ALX_MAX_TX_QUEUES	4
357 #define ALX_MAX_HANDLED_INTRS	5
358 
359 #define ALX_ISR_MISC		(ALX_ISR_PCIE_LNKDOWN | \
360 				 ALX_ISR_DMAW | \
361 				 ALX_ISR_DMAR | \
362 				 ALX_ISR_SMB | \
363 				 ALX_ISR_MANU | \
364 				 ALX_ISR_TIMER)
365 
366 #define ALX_ISR_FATAL		(ALX_ISR_PCIE_LNKDOWN | \
367 				 ALX_ISR_DMAW | ALX_ISR_DMAR)
368 
369 #define ALX_ISR_ALERT		(ALX_ISR_RXF_OV | \
370 				 ALX_ISR_TXF_UR | \
371 				 ALX_ISR_RFD_UR)
372 
373 #define ALX_ISR_ALL_QUEUES	(ALX_ISR_TX_Q0 | \
374 				 ALX_ISR_TX_Q1 | \
375 				 ALX_ISR_TX_Q2 | \
376 				 ALX_ISR_TX_Q3 | \
377 				 ALX_ISR_RX_Q0 | \
378 				 ALX_ISR_RX_Q1 | \
379 				 ALX_ISR_RX_Q2 | \
380 				 ALX_ISR_RX_Q3 | \
381 				 ALX_ISR_RX_Q4 | \
382 				 ALX_ISR_RX_Q5 | \
383 				 ALX_ISR_RX_Q6 | \
384 				 ALX_ISR_RX_Q7)
385 
386 /* Statistics counters collected by the MAC
387  *
388  * The order of the fields must match the strings in alx_gstrings_stats
389  * All stats fields should be u64
390  * See ethtool.c
391  */
392 struct alx_hw_stats {
393 	/* rx */
394 	u64 rx_ok;		/* good RX packets */
395 	u64 rx_bcast;		/* good RX broadcast packets */
396 	u64 rx_mcast;		/* good RX multicast packets */
397 	u64 rx_pause;		/* RX pause frames */
398 	u64 rx_ctrl;		/* RX control packets other than pause frames */
399 	u64 rx_fcs_err;		/* RX packets with bad FCS */
400 	u64 rx_len_err;		/* RX packets with length != actual size */
401 	u64 rx_byte_cnt;	/* good bytes received. FCS is NOT included */
402 	u64 rx_runt;		/* RX packets < 64 bytes with good FCS */
403 	u64 rx_frag;		/* RX packets < 64 bytes with bad FCS */
404 	u64 rx_sz_64B;		/* 64 byte RX packets */
405 	u64 rx_sz_127B;		/* 65-127 byte RX packets */
406 	u64 rx_sz_255B;		/* 128-255 byte RX packets */
407 	u64 rx_sz_511B;		/* 256-511 byte RX packets */
408 	u64 rx_sz_1023B;	/* 512-1023 byte RX packets */
409 	u64 rx_sz_1518B;	/* 1024-1518 byte RX packets */
410 	u64 rx_sz_max;		/* 1519 byte to MTU RX packets */
411 	u64 rx_ov_sz;		/* truncated RX packets, size > MTU */
412 	u64 rx_ov_rxf;		/* frames dropped due to RX FIFO overflow */
413 	u64 rx_ov_rrd;		/* frames dropped due to RRD overflow */
414 	u64 rx_align_err;	/* alignment errors */
415 	u64 rx_bc_byte_cnt;	/* RX broadcast bytes, excluding FCS */
416 	u64 rx_mc_byte_cnt;	/* RX multicast bytes, excluding FCS */
417 	u64 rx_err_addr;	/* packets dropped due to address filtering */
418 
419 	/* tx */
420 	u64 tx_ok;		/* good TX packets */
421 	u64 tx_bcast;		/* good TX broadcast packets */
422 	u64 tx_mcast;		/* good TX multicast packets */
423 	u64 tx_pause;		/* TX pause frames */
424 	u64 tx_exc_defer;	/* TX packets deferred excessively */
425 	u64 tx_ctrl;		/* TX control frames, excluding pause frames */
426 	u64 tx_defer;		/* TX packets deferred */
427 	u64 tx_byte_cnt;	/* bytes transmitted, FCS is NOT included */
428 	u64 tx_sz_64B;		/* 64 byte TX packets */
429 	u64 tx_sz_127B;		/* 65-127 byte TX packets */
430 	u64 tx_sz_255B;		/* 128-255 byte TX packets */
431 	u64 tx_sz_511B;		/* 256-511 byte TX packets */
432 	u64 tx_sz_1023B;	/* 512-1023 byte TX packets */
433 	u64 tx_sz_1518B;	/* 1024-1518 byte TX packets */
434 	u64 tx_sz_max;		/* 1519 byte to MTU TX packets */
435 	u64 tx_single_col;	/* packets TX after a single collision */
436 	u64 tx_multi_col;	/* packets TX after multiple collisions */
437 	u64 tx_late_col;	/* TX packets with late collisions */
438 	u64 tx_abort_col;	/* TX packets aborted w/excessive collisions */
439 	u64 tx_underrun;	/* TX packets aborted due to TX FIFO underrun
440 				 * or TRD FIFO underrun
441 				 */
442 	u64 tx_trd_eop;		/* reads beyond the EOP into the next frame
443 				 * when TRD was not written timely
444 				 */
445 	u64 tx_len_err;		/* TX packets where length != actual size */
446 	u64 tx_trunc;		/* TX packets truncated due to size > MTU */
447 	u64 tx_bc_byte_cnt;	/* broadcast bytes transmitted, excluding FCS */
448 	u64 tx_mc_byte_cnt;	/* multicast bytes transmitted, excluding FCS */
449 	u64 update;
450 };
451 
452 
453 /* maximum interrupt vectors for msix */
454 #define ALX_MAX_MSIX_INTRS	16
455 
456 #define ALX_GET_FIELD(_data, _field)					\
457 	(((_data) >> _field ## _SHIFT) & _field ## _MASK)
458 
459 #define ALX_SET_FIELD(_data, _field, _value)	do {			\
460 		(_data) &= ~(_field ## _MASK << _field ## _SHIFT);	\
461 		(_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
462 	} while (0)
463 
464 struct alx_hw {
465 	struct pci_dev *pdev;
466 	u8 __iomem *hw_addr;
467 
468 	/* current & permanent mac addr */
469 	u8 mac_addr[ETH_ALEN];
470 	u8 perm_addr[ETH_ALEN];
471 
472 	u16 mtu;
473 	u16 imt;
474 	u8 dma_chnl;
475 	u8 max_dma_chnl;
476 	/* tpd threshold to trig INT */
477 	u32 ith_tpd;
478 	u32 rx_ctrl;
479 	u32 mc_hash[2];
480 
481 	u32 smb_timer;
482 	/* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
483 	int link_speed;
484 	u8 duplex;
485 
486 	/* auto-neg advertisement or force mode config */
487 	u8 flowctrl;
488 	u32 adv_cfg;
489 
490 	spinlock_t mdio_lock;
491 	struct mdio_if_info mdio;
492 	u16 phy_id[2];
493 
494 	/* PHY link patch flag */
495 	bool lnk_patch;
496 
497 	/* cumulated stats from the hardware (registers are cleared on read) */
498 	struct alx_hw_stats stats;
499 };
500 
alx_hw_revision(struct alx_hw * hw)501 static inline int alx_hw_revision(struct alx_hw *hw)
502 {
503 	return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
504 }
505 
alx_hw_with_cr(struct alx_hw * hw)506 static inline bool alx_hw_with_cr(struct alx_hw *hw)
507 {
508 	return hw->pdev->revision & 1;
509 }
510 
alx_hw_giga(struct alx_hw * hw)511 static inline bool alx_hw_giga(struct alx_hw *hw)
512 {
513 	return hw->pdev->device & 1;
514 }
515 
alx_write_mem8(struct alx_hw * hw,u32 reg,u8 val)516 static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
517 {
518 	writeb(val, hw->hw_addr + reg);
519 }
520 
alx_write_mem16(struct alx_hw * hw,u32 reg,u16 val)521 static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
522 {
523 	writew(val, hw->hw_addr + reg);
524 }
525 
alx_read_mem16(struct alx_hw * hw,u32 reg)526 static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
527 {
528 	return readw(hw->hw_addr + reg);
529 }
530 
alx_write_mem32(struct alx_hw * hw,u32 reg,u32 val)531 static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
532 {
533 	writel(val, hw->hw_addr + reg);
534 }
535 
alx_read_mem32(struct alx_hw * hw,u32 reg)536 static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
537 {
538 	return readl(hw->hw_addr + reg);
539 }
540 
alx_post_write(struct alx_hw * hw)541 static inline void alx_post_write(struct alx_hw *hw)
542 {
543 	readl(hw->hw_addr);
544 }
545 
546 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
547 void alx_reset_phy(struct alx_hw *hw);
548 void alx_reset_pcie(struct alx_hw *hw);
549 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
550 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
551 void alx_post_phy_link(struct alx_hw *hw);
552 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
553 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
554 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
555 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
556 int alx_read_phy_link(struct alx_hw *hw);
557 int alx_clear_phy_intr(struct alx_hw *hw);
558 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
559 void alx_start_mac(struct alx_hw *hw);
560 int alx_reset_mac(struct alx_hw *hw);
561 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
562 bool alx_phy_configured(struct alx_hw *hw);
563 void alx_configure_basic(struct alx_hw *hw);
564 void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
565 void alx_disable_rss(struct alx_hw *hw);
566 bool alx_get_phy_info(struct alx_hw *hw);
567 void alx_update_hw_stats(struct alx_hw *hw);
568 
alx_speed_to_ethadv(int speed,u8 duplex)569 static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
570 {
571 	if (speed == SPEED_1000 && duplex == DUPLEX_FULL)
572 		return ADVERTISED_1000baseT_Full;
573 	if (speed == SPEED_100 && duplex == DUPLEX_FULL)
574 		return ADVERTISED_100baseT_Full;
575 	if (speed == SPEED_100 && duplex== DUPLEX_HALF)
576 		return ADVERTISED_100baseT_Half;
577 	if (speed == SPEED_10 && duplex == DUPLEX_FULL)
578 		return ADVERTISED_10baseT_Full;
579 	if (speed == SPEED_10 && duplex == DUPLEX_HALF)
580 		return ADVERTISED_10baseT_Half;
581 	return 0;
582 }
583 
584 #endif
585