xref: /linux/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2 /* Copyright (c) 2023 Imagination Technologies Ltd. */
3 
4 #ifndef PVR_ROGUE_HEAP_CONFIG_H
5 #define PVR_ROGUE_HEAP_CONFIG_H
6 
7 #include <linux/sizes.h>
8 
9 /*
10  * ROGUE Device Virtual Address Space Definitions
11  *
12  * This file defines the ROGUE virtual address heaps that are used in
13  * application memory contexts. It also shows where the Firmware memory heap
14  * fits into this, but the firmware heap is only ever created in the
15  * kernel driver and never exposed to userspace.
16  *
17  * ROGUE_PDSCODEDATA_HEAP_BASE and ROGUE_USCCODE_HEAP_BASE will be programmed,
18  * on a global basis, into ROGUE_CR_PDS_EXEC_BASE and ROGUE_CR_USC_CODE_BASE_*
19  * respectively. Therefore if client drivers use multiple configs they must
20  * still be consistent with their definitions for these heaps.
21  *
22  * Base addresses have to be a multiple of 4MiB.
23  * Heaps must not start at 0x0000000000, as this is reserved for internal
24  * use within the driver.
25  * Range comments, those starting in column 0 below are a section heading of
26  * sorts and are above the heaps in that range. Often this is the reserved
27  * size of the heap within the range.
28  */
29 
30 /* 0x00_0000_0000 ************************************************************/
31 
32 /* 0x00_0000_0000 - 0x00_0040_0000 */
33 /* 0 MiB to 4 MiB, size of 4 MiB : RESERVED */
34 
35 /* 0x00_0040_0000 - 0x7F_FFC0_0000 **/
36 /* 4 MiB to 512 GiB, size of 512 GiB less 4 MiB : RESERVED **/
37 
38 /* 0x80_0000_0000 ************************************************************/
39 
40 /* 0x80_0000_0000 - 0x9F_FFFF_FFFF **/
41 /* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP **/
42 #define ROGUE_GENERAL_HEAP_BASE 0x8000000000ull
43 #define ROGUE_GENERAL_HEAP_SIZE SZ_128G
44 
45 /* 0xA0_0000_0000 - 0xAF_FFFF_FFFF */
46 /* 640 GiB to 704 GiB, size of 64 GiB : FREE */
47 
48 /* B0_0000_0000 - 0xB7_FFFF_FFFF */
49 /* 704 GiB to 736 GiB, size of 32 GiB : FREE */
50 
51 /* 0xB8_0000_0000 - 0xBF_FFFF_FFFF */
52 /* 736 GiB to 768 GiB, size of 32 GiB : RESERVED */
53 
54 /* 0xC0_0000_0000 ************************************************************/
55 
56 /* 0xC0_0000_0000 - 0xD9_FFFF_FFFF */
57 /* 768 GiB to 872 GiB, size of 104 GiB : FREE */
58 
59 /* 0xDA_0000_0000 - 0xDA_FFFF_FFFF */
60 /* 872 GiB to 876 GiB, size of 4 GiB : PDSCODEDATA_HEAP */
61 #define ROGUE_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
62 #define ROGUE_PDSCODEDATA_HEAP_SIZE SZ_4G
63 
64 /* 0xDB_0000_0000 - 0xDB_FFFF_FFFF */
65 /* 876 GiB to 880 GiB, size of 256 MiB (reserved 4GiB) : BRN **/
66 /*
67  * The BRN63142 quirk workaround requires Region Header memory to be at the top
68  * of a 16GiB aligned range. This is so when masked with 0x03FFFFFFFF the
69  * address will avoid aliasing PB addresses. Start at 879.75GiB. Size of 256MiB.
70  */
71 #define ROGUE_RGNHDR_HEAP_BASE 0xDBF0000000ull
72 #define ROGUE_RGNHDR_HEAP_SIZE SZ_256M
73 
74 /* 0xDC_0000_0000 - 0xDF_FFFF_FFFF */
75 /* 880 GiB to 896 GiB, size of 16 GiB : FREE */
76 
77 /* 0xE0_0000_0000 - 0xE0_FFFF_FFFF */
78 /* 896 GiB to 900 GiB, size of 4 GiB : USCCODE_HEAP */
79 #define ROGUE_USCCODE_HEAP_BASE 0xE000000000ull
80 #define ROGUE_USCCODE_HEAP_SIZE SZ_4G
81 
82 /* 0xE1_0000_0000 - 0xE1_BFFF_FFFF */
83 /* 900 GiB to 903 GiB, size of 3 GiB : RESERVED */
84 
85 /* 0xE1_C000_000 - 0xE1_FFFF_FFFF */
86 /* 903 GiB to 904 GiB, reserved 1 GiB, : FIRMWARE_HEAP */
87 #define ROGUE_FW_HEAP_BASE 0xE1C0000000ull
88 
89 /* 0xE2_0000_0000 - 0xE3_FFFF_FFFF */
90 /* 904 GiB to 912 GiB, size of 8 GiB : FREE */
91 
92 /* 0xE4_0000_0000 - 0xE7_FFFF_FFFF */
93 /* 912 GiB to 968 GiB, size of 16 GiB : TRANSFER_FRAG */
94 #define ROGUE_TRANSFER_FRAG_HEAP_BASE 0xE400000000ull
95 #define ROGUE_TRANSFER_FRAG_HEAP_SIZE SZ_16G
96 
97 /* 0xE8_0000_0000 - 0xF1_FFFF_FFFF */
98 /* 928 GiB to 968 GiB, size of 40 GiB : RESERVED */
99 
100 /* 0xF2_0000_0000 - 0xF2_001F_FFFF **/
101 /* 968 GiB to 969 GiB, size of 2 MiB : VISTEST_HEAP */
102 #define ROGUE_VISTEST_HEAP_BASE 0xF200000000ull
103 #define ROGUE_VISTEST_HEAP_SIZE SZ_2M
104 
105 /* 0xF2_4000_0000 - 0xF2_FFFF_FFFF */
106 /* 969 GiB to 972 GiB, size of 3 GiB : FREE */
107 
108 /* 0xF3_0000_0000 - 0xFF_FFFF_FFFF */
109 /* 972 GiB to 1024 GiB, size of 52 GiB : FREE */
110 
111 /* 0xFF_FFFF_FFFF ************************************************************/
112 
113 #endif /* PVR_ROGUE_HEAP_CONFIG_H */
114