1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #ifndef PVR_ROGUE_DEFS_H 5 #define PVR_ROGUE_DEFS_H 6 7 #include "pvr_rogue_cr_defs.h" 8 9 #include <linux/bits.h> 10 11 /* 12 ****************************************************************************** 13 * ROGUE Defines 14 ****************************************************************************** 15 */ 16 17 #define ROGUE_FW_MAX_NUM_OS (8U) 18 #define ROGUE_FW_HOST_OS (0U) 19 #define ROGUE_FW_GUEST_OSID_START (1U) 20 21 #define ROGUE_FW_THREAD_0 (0U) 22 #define ROGUE_FW_THREAD_1 (1U) 23 24 #define GET_ROGUE_CACHE_LINE_SIZE(x) ((((s32)(x)) > 0) ? ((x) / 8) : (0)) 25 26 #define MAX_HW_GEOM_FRAG_CONTEXTS 2U 27 28 #define ROGUE_CR_CLK_CTRL_ALL_ON \ 29 (0x5555555555555555ull & ROGUE_CR_CLK_CTRL_MASKFULL) 30 #define ROGUE_CR_CLK_CTRL_ALL_AUTO \ 31 (0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL_MASKFULL) 32 #define ROGUE_CR_CLK_CTRL2_ALL_ON \ 33 (0x5555555555555555ull & ROGUE_CR_CLK_CTRL2_MASKFULL) 34 #define ROGUE_CR_CLK_CTRL2_ALL_AUTO \ 35 (0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL2_MASKFULL) 36 37 #define ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN \ 38 (ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN | \ 39 ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN | \ 40 ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN | \ 41 ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN | \ 42 ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN | \ 43 ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN | \ 44 ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN | \ 45 ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN) 46 47 /* SOFT_RESET Rascal and DUSTs bits */ 48 #define ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN \ 49 (ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN | \ 50 ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN) 51 52 /* SOFT_RESET steps as defined in the TRM */ 53 #define ROGUE_S7_SOFT_RESET_DUSTS (ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN) 54 55 #define ROGUE_S7_SOFT_RESET_JONES \ 56 (ROGUE_CR_SOFT_RESET_PM_EN | ROGUE_CR_SOFT_RESET_VDM_EN | \ 57 ROGUE_CR_SOFT_RESET_ISP_EN) 58 59 #define ROGUE_S7_SOFT_RESET_JONES_ALL \ 60 (ROGUE_S7_SOFT_RESET_JONES | ROGUE_CR_SOFT_RESET_BIF_EN | \ 61 ROGUE_CR_SOFT_RESET_SLC_EN | ROGUE_CR_SOFT_RESET_GARTEN_EN) 62 63 #define ROGUE_S7_SOFT_RESET2 \ 64 (ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN | ROGUE_CR_SOFT_RESET2_PIXEL_EN | \ 65 ROGUE_CR_SOFT_RESET2_CDM_EN | ROGUE_CR_SOFT_RESET2_VERTEX_EN) 66 67 #define ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT (12U) 68 #define ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE \ 69 BIT(ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT) 70 71 #define ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT (14U) 72 #define ROGUE_BIF_PM_VIRTUAL_PAGE_SIZE BIT(ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT) 73 74 #define ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE (16U) 75 76 /* 77 * To get the number of required Dusts, divide the number of 78 * clusters by 2 and round up 79 */ 80 #define ROGUE_REQ_NUM_DUSTS(CLUSTERS) (((CLUSTERS) + 1U) / 2U) 81 82 /* 83 * To get the number of required Bernado/Phantom(s), divide 84 * the number of clusters by 4 and round up 85 */ 86 #define ROGUE_REQ_NUM_PHANTOMS(CLUSTERS) (((CLUSTERS) + 3U) / 4U) 87 #define ROGUE_REQ_NUM_BERNADOS(CLUSTERS) (((CLUSTERS) + 3U) / 4U) 88 #define ROGUE_REQ_NUM_BLACKPEARLS(CLUSTERS) (((CLUSTERS) + 3U) / 4U) 89 90 /* 91 * FW MMU contexts 92 */ 93 #define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */ 94 #define MMU_CONTEXT_MAPPING_FWIF (0x0) /* Host/FW data */ 95 96 /* 97 * Utility macros to calculate CAT_BASE register addresses 98 */ 99 #define BIF_CAT_BASEX(n) \ 100 (ROGUE_CR_BIF_CAT_BASE0 + \ 101 (n) * (ROGUE_CR_BIF_CAT_BASE1 - ROGUE_CR_BIF_CAT_BASE0)) 102 103 #define FWCORE_MEM_CAT_BASEX(n) \ 104 (ROGUE_CR_FWCORE_MEM_CAT_BASE0 + \ 105 (n) * (ROGUE_CR_FWCORE_MEM_CAT_BASE1 - \ 106 ROGUE_CR_FWCORE_MEM_CAT_BASE0)) 107 108 /* 109 * FWCORE wrapper register defines 110 */ 111 #define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT \ 112 ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 113 #define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_CLRMSK \ 114 ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 115 #define FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT (12U) 116 117 #define ROGUE_MAX_COMPUTE_SHARED_REGISTERS (2 * 1024) 118 #define ROGUE_MAX_VERTEX_SHARED_REGISTERS 1024 119 #define ROGUE_MAX_PIXEL_SHARED_REGISTERS 1024 120 #define ROGUE_CSRM_LINE_SIZE_IN_DWORDS (64 * 4 * 4) 121 122 #define ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE 64 123 #define ROGUE_CDMCTRL_USC_COMMON_SIZE_UPPER 256 124 125 /* 126 * The maximum amount of local memory which can be allocated by a single kernel 127 * (in dwords/32-bit registers). 128 * 129 * ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE is in bytes so we divide by four. 130 */ 131 #define ROGUE_MAX_PER_KERNEL_LOCAL_MEM_SIZE_REGS ((ROGUE_CDMCTRL_USC_COMMON_SIZE_ALIGNSIZE * \ 132 ROGUE_CDMCTRL_USC_COMMON_SIZE_UPPER) >> 2) 133 134 /* 135 ****************************************************************************** 136 * WA HWBRNs 137 ****************************************************************************** 138 */ 139 140 /* GPU CR timer tick in GPU cycles */ 141 #define ROGUE_CRTIME_TICK_IN_CYCLES (256U) 142 143 /* for nohw multicore return max cores possible to client */ 144 #define ROGUE_MULTICORE_MAX_NOHW_CORES (4U) 145 146 /* 147 * If the size of the SLC is less than this value then the TPU bypasses the SLC. 148 */ 149 #define ROGUE_TPU_CACHED_SLC_SIZE_THRESHOLD (128U * 1024U) 150 151 /* 152 * If the size of the SLC is bigger than this value then the TCU must not be 153 * bypassed in the SLC. 154 * In XE_MEMORY_HIERARCHY cores, the TCU is bypassed by default. 155 */ 156 #define ROGUE_TCU_CACHED_SLC_SIZE_THRESHOLD (32U * 1024U) 157 158 /* 159 * Register used by the FW to track the current boot stage (not used in MIPS) 160 */ 161 #define ROGUE_FW_BOOT_STAGE_REGISTER (ROGUE_CR_POWER_ESTIMATE_RESULT) 162 163 /* 164 * Virtualisation definitions 165 */ 166 #define ROGUE_VIRTUALISATION_REG_SIZE_PER_OS \ 167 (ROGUE_CR_MTS_SCHEDULE1 - ROGUE_CR_MTS_SCHEDULE) 168 169 /* 170 * Macro used to indicate which version of HWPerf is active 171 */ 172 #define ROGUE_FEATURE_HWPERF_ROGUE 173 174 /* 175 * Maximum number of cores supported by TRP 176 */ 177 #define ROGUE_TRP_MAX_NUM_CORES (4U) 178 179 #endif /* PVR_ROGUE_DEFS_H */ 180