xref: /linux/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2 /* Copyright (c) 2023 Imagination Technologies Ltd. */
3 
4 /*  *** Autogenerated C -- do not edit ***  */
5 
6 #ifndef PVR_ROGUE_CR_DEFS_H
7 #define PVR_ROGUE_CR_DEFS_H
8 
9 /* clang-format off */
10 
11 #define ROGUE_CR_DEFS_REVISION 1
12 
13 /* Register ROGUE_CR_RASTERISATION_INDIRECT */
14 #define ROGUE_CR_RASTERISATION_INDIRECT 0x8238U
15 #define ROGUE_CR_RASTERISATION_INDIRECT_MASKFULL 0x000000000000000FULL
16 #define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U
17 #define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
18 
19 /* Register ROGUE_CR_PBE_INDIRECT */
20 #define ROGUE_CR_PBE_INDIRECT 0x83E0U
21 #define ROGUE_CR_PBE_INDIRECT_MASKFULL 0x000000000000000FULL
22 #define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U
23 #define ROGUE_CR_PBE_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
24 
25 /* Register ROGUE_CR_PBE_PERF_INDIRECT */
26 #define ROGUE_CR_PBE_PERF_INDIRECT 0x83D8U
27 #define ROGUE_CR_PBE_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
28 #define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U
29 #define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
30 
31 /* Register ROGUE_CR_TPU_PERF_INDIRECT */
32 #define ROGUE_CR_TPU_PERF_INDIRECT 0x83F0U
33 #define ROGUE_CR_TPU_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
34 #define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U
35 #define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
36 
37 /* Register ROGUE_CR_RASTERISATION_PERF_INDIRECT */
38 #define ROGUE_CR_RASTERISATION_PERF_INDIRECT 0x8318U
39 #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
40 #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U
41 #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
42 
43 /* Register ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT */
44 #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT 0x8028U
45 #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
46 #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U
47 #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
48 
49 /* Register ROGUE_CR_USC_PERF_INDIRECT */
50 #define ROGUE_CR_USC_PERF_INDIRECT 0x8030U
51 #define ROGUE_CR_USC_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
52 #define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U
53 #define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
54 
55 /* Register ROGUE_CR_BLACKPEARL_INDIRECT */
56 #define ROGUE_CR_BLACKPEARL_INDIRECT 0x8388U
57 #define ROGUE_CR_BLACKPEARL_INDIRECT_MASKFULL 0x0000000000000003ULL
58 #define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U
59 #define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
60 
61 /* Register ROGUE_CR_BLACKPEARL_PERF_INDIRECT */
62 #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT 0x83F8U
63 #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
64 #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U
65 #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
66 
67 /* Register ROGUE_CR_TEXAS3_PERF_INDIRECT */
68 #define ROGUE_CR_TEXAS3_PERF_INDIRECT 0x83D0U
69 #define ROGUE_CR_TEXAS3_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
70 #define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U
71 #define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
72 
73 /* Register ROGUE_CR_TEXAS_PERF_INDIRECT */
74 #define ROGUE_CR_TEXAS_PERF_INDIRECT 0x8288U
75 #define ROGUE_CR_TEXAS_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
76 #define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U
77 #define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
78 
79 /* Register ROGUE_CR_BX_TU_PERF_INDIRECT */
80 #define ROGUE_CR_BX_TU_PERF_INDIRECT 0xC900U
81 #define ROGUE_CR_BX_TU_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
82 #define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U
83 #define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
84 
85 /* Register ROGUE_CR_CLK_CTRL */
86 #define ROGUE_CR_CLK_CTRL 0x0000U
87 #define ROGUE_CR_CLK_CTRL__PBE2_XE__MASKFULL 0xFFFFFF003F3FFFFFULL
88 #define ROGUE_CR_CLK_CTRL__S7_TOP__MASKFULL 0xCFCF03000F3F3F0FULL
89 #define ROGUE_CR_CLK_CTRL_MASKFULL 0xFFFFFF003F3FFFFFULL
90 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U
91 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_CLRMSK 0x3FFFFFFFFFFFFFFFULL
92 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_OFF 0x0000000000000000ULL
93 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_ON 0x4000000000000000ULL
94 #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_AUTO 0x8000000000000000ULL
95 #define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U
96 #define ROGUE_CR_CLK_CTRL_IPP_CLRMSK 0xCFFFFFFFFFFFFFFFULL
97 #define ROGUE_CR_CLK_CTRL_IPP_OFF 0x0000000000000000ULL
98 #define ROGUE_CR_CLK_CTRL_IPP_ON 0x1000000000000000ULL
99 #define ROGUE_CR_CLK_CTRL_IPP_AUTO 0x2000000000000000ULL
100 #define ROGUE_CR_CLK_CTRL_FBC_SHIFT 58U
101 #define ROGUE_CR_CLK_CTRL_FBC_CLRMSK 0xF3FFFFFFFFFFFFFFULL
102 #define ROGUE_CR_CLK_CTRL_FBC_OFF 0x0000000000000000ULL
103 #define ROGUE_CR_CLK_CTRL_FBC_ON 0x0400000000000000ULL
104 #define ROGUE_CR_CLK_CTRL_FBC_AUTO 0x0800000000000000ULL
105 #define ROGUE_CR_CLK_CTRL_FBDC_SHIFT 56U
106 #define ROGUE_CR_CLK_CTRL_FBDC_CLRMSK 0xFCFFFFFFFFFFFFFFULL
107 #define ROGUE_CR_CLK_CTRL_FBDC_OFF 0x0000000000000000ULL
108 #define ROGUE_CR_CLK_CTRL_FBDC_ON 0x0100000000000000ULL
109 #define ROGUE_CR_CLK_CTRL_FBDC_AUTO 0x0200000000000000ULL
110 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_SHIFT 54U
111 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_CLRMSK 0xFF3FFFFFFFFFFFFFULL
112 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_OFF 0x0000000000000000ULL
113 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_ON 0x0040000000000000ULL
114 #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_AUTO 0x0080000000000000ULL
115 #define ROGUE_CR_CLK_CTRL_USCS_SHIFT 52U
116 #define ROGUE_CR_CLK_CTRL_USCS_CLRMSK 0xFFCFFFFFFFFFFFFFULL
117 #define ROGUE_CR_CLK_CTRL_USCS_OFF 0x0000000000000000ULL
118 #define ROGUE_CR_CLK_CTRL_USCS_ON 0x0010000000000000ULL
119 #define ROGUE_CR_CLK_CTRL_USCS_AUTO 0x0020000000000000ULL
120 #define ROGUE_CR_CLK_CTRL_PBE_SHIFT 50U
121 #define ROGUE_CR_CLK_CTRL_PBE_CLRMSK 0xFFF3FFFFFFFFFFFFULL
122 #define ROGUE_CR_CLK_CTRL_PBE_OFF 0x0000000000000000ULL
123 #define ROGUE_CR_CLK_CTRL_PBE_ON 0x0004000000000000ULL
124 #define ROGUE_CR_CLK_CTRL_PBE_AUTO 0x0008000000000000ULL
125 #define ROGUE_CR_CLK_CTRL_MCU_L1_SHIFT 48U
126 #define ROGUE_CR_CLK_CTRL_MCU_L1_CLRMSK 0xFFFCFFFFFFFFFFFFULL
127 #define ROGUE_CR_CLK_CTRL_MCU_L1_OFF 0x0000000000000000ULL
128 #define ROGUE_CR_CLK_CTRL_MCU_L1_ON 0x0001000000000000ULL
129 #define ROGUE_CR_CLK_CTRL_MCU_L1_AUTO 0x0002000000000000ULL
130 #define ROGUE_CR_CLK_CTRL_CDM_SHIFT 46U
131 #define ROGUE_CR_CLK_CTRL_CDM_CLRMSK 0xFFFF3FFFFFFFFFFFULL
132 #define ROGUE_CR_CLK_CTRL_CDM_OFF 0x0000000000000000ULL
133 #define ROGUE_CR_CLK_CTRL_CDM_ON 0x0000400000000000ULL
134 #define ROGUE_CR_CLK_CTRL_CDM_AUTO 0x0000800000000000ULL
135 #define ROGUE_CR_CLK_CTRL_SIDEKICK_SHIFT 44U
136 #define ROGUE_CR_CLK_CTRL_SIDEKICK_CLRMSK 0xFFFFCFFFFFFFFFFFULL
137 #define ROGUE_CR_CLK_CTRL_SIDEKICK_OFF 0x0000000000000000ULL
138 #define ROGUE_CR_CLK_CTRL_SIDEKICK_ON 0x0000100000000000ULL
139 #define ROGUE_CR_CLK_CTRL_SIDEKICK_AUTO 0x0000200000000000ULL
140 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_SHIFT 42U
141 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_CLRMSK 0xFFFFF3FFFFFFFFFFULL
142 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_OFF 0x0000000000000000ULL
143 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_ON 0x0000040000000000ULL
144 #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_AUTO 0x0000080000000000ULL
145 #define ROGUE_CR_CLK_CTRL_BIF_SHIFT 40U
146 #define ROGUE_CR_CLK_CTRL_BIF_CLRMSK 0xFFFFFCFFFFFFFFFFULL
147 #define ROGUE_CR_CLK_CTRL_BIF_OFF 0x0000000000000000ULL
148 #define ROGUE_CR_CLK_CTRL_BIF_ON 0x0000010000000000ULL
149 #define ROGUE_CR_CLK_CTRL_BIF_AUTO 0x0000020000000000ULL
150 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_SHIFT 28U
151 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFCFFFFFFFULL
152 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_OFF 0x0000000000000000ULL
153 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_ON 0x0000000010000000ULL
154 #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_AUTO 0x0000000020000000ULL
155 #define ROGUE_CR_CLK_CTRL_MCU_L0_SHIFT 26U
156 #define ROGUE_CR_CLK_CTRL_MCU_L0_CLRMSK 0xFFFFFFFFF3FFFFFFULL
157 #define ROGUE_CR_CLK_CTRL_MCU_L0_OFF 0x0000000000000000ULL
158 #define ROGUE_CR_CLK_CTRL_MCU_L0_ON 0x0000000004000000ULL
159 #define ROGUE_CR_CLK_CTRL_MCU_L0_AUTO 0x0000000008000000ULL
160 #define ROGUE_CR_CLK_CTRL_TPU_SHIFT 24U
161 #define ROGUE_CR_CLK_CTRL_TPU_CLRMSK 0xFFFFFFFFFCFFFFFFULL
162 #define ROGUE_CR_CLK_CTRL_TPU_OFF 0x0000000000000000ULL
163 #define ROGUE_CR_CLK_CTRL_TPU_ON 0x0000000001000000ULL
164 #define ROGUE_CR_CLK_CTRL_TPU_AUTO 0x0000000002000000ULL
165 #define ROGUE_CR_CLK_CTRL_USC_SHIFT 20U
166 #define ROGUE_CR_CLK_CTRL_USC_CLRMSK 0xFFFFFFFFFFCFFFFFULL
167 #define ROGUE_CR_CLK_CTRL_USC_OFF 0x0000000000000000ULL
168 #define ROGUE_CR_CLK_CTRL_USC_ON 0x0000000000100000ULL
169 #define ROGUE_CR_CLK_CTRL_USC_AUTO 0x0000000000200000ULL
170 #define ROGUE_CR_CLK_CTRL_TLA_SHIFT 18U
171 #define ROGUE_CR_CLK_CTRL_TLA_CLRMSK 0xFFFFFFFFFFF3FFFFULL
172 #define ROGUE_CR_CLK_CTRL_TLA_OFF 0x0000000000000000ULL
173 #define ROGUE_CR_CLK_CTRL_TLA_ON 0x0000000000040000ULL
174 #define ROGUE_CR_CLK_CTRL_TLA_AUTO 0x0000000000080000ULL
175 #define ROGUE_CR_CLK_CTRL_SLC_SHIFT 16U
176 #define ROGUE_CR_CLK_CTRL_SLC_CLRMSK 0xFFFFFFFFFFFCFFFFULL
177 #define ROGUE_CR_CLK_CTRL_SLC_OFF 0x0000000000000000ULL
178 #define ROGUE_CR_CLK_CTRL_SLC_ON 0x0000000000010000ULL
179 #define ROGUE_CR_CLK_CTRL_SLC_AUTO 0x0000000000020000ULL
180 #define ROGUE_CR_CLK_CTRL_UVS_SHIFT 14U
181 #define ROGUE_CR_CLK_CTRL_UVS_CLRMSK 0xFFFFFFFFFFFF3FFFULL
182 #define ROGUE_CR_CLK_CTRL_UVS_OFF 0x0000000000000000ULL
183 #define ROGUE_CR_CLK_CTRL_UVS_ON 0x0000000000004000ULL
184 #define ROGUE_CR_CLK_CTRL_UVS_AUTO 0x0000000000008000ULL
185 #define ROGUE_CR_CLK_CTRL_PDS_SHIFT 12U
186 #define ROGUE_CR_CLK_CTRL_PDS_CLRMSK 0xFFFFFFFFFFFFCFFFULL
187 #define ROGUE_CR_CLK_CTRL_PDS_OFF 0x0000000000000000ULL
188 #define ROGUE_CR_CLK_CTRL_PDS_ON 0x0000000000001000ULL
189 #define ROGUE_CR_CLK_CTRL_PDS_AUTO 0x0000000000002000ULL
190 #define ROGUE_CR_CLK_CTRL_VDM_SHIFT 10U
191 #define ROGUE_CR_CLK_CTRL_VDM_CLRMSK 0xFFFFFFFFFFFFF3FFULL
192 #define ROGUE_CR_CLK_CTRL_VDM_OFF 0x0000000000000000ULL
193 #define ROGUE_CR_CLK_CTRL_VDM_ON 0x0000000000000400ULL
194 #define ROGUE_CR_CLK_CTRL_VDM_AUTO 0x0000000000000800ULL
195 #define ROGUE_CR_CLK_CTRL_PM_SHIFT 8U
196 #define ROGUE_CR_CLK_CTRL_PM_CLRMSK 0xFFFFFFFFFFFFFCFFULL
197 #define ROGUE_CR_CLK_CTRL_PM_OFF 0x0000000000000000ULL
198 #define ROGUE_CR_CLK_CTRL_PM_ON 0x0000000000000100ULL
199 #define ROGUE_CR_CLK_CTRL_PM_AUTO 0x0000000000000200ULL
200 #define ROGUE_CR_CLK_CTRL_GPP_SHIFT 6U
201 #define ROGUE_CR_CLK_CTRL_GPP_CLRMSK 0xFFFFFFFFFFFFFF3FULL
202 #define ROGUE_CR_CLK_CTRL_GPP_OFF 0x0000000000000000ULL
203 #define ROGUE_CR_CLK_CTRL_GPP_ON 0x0000000000000040ULL
204 #define ROGUE_CR_CLK_CTRL_GPP_AUTO 0x0000000000000080ULL
205 #define ROGUE_CR_CLK_CTRL_TE_SHIFT 4U
206 #define ROGUE_CR_CLK_CTRL_TE_CLRMSK 0xFFFFFFFFFFFFFFCFULL
207 #define ROGUE_CR_CLK_CTRL_TE_OFF 0x0000000000000000ULL
208 #define ROGUE_CR_CLK_CTRL_TE_ON 0x0000000000000010ULL
209 #define ROGUE_CR_CLK_CTRL_TE_AUTO 0x0000000000000020ULL
210 #define ROGUE_CR_CLK_CTRL_TSP_SHIFT 2U
211 #define ROGUE_CR_CLK_CTRL_TSP_CLRMSK 0xFFFFFFFFFFFFFFF3ULL
212 #define ROGUE_CR_CLK_CTRL_TSP_OFF 0x0000000000000000ULL
213 #define ROGUE_CR_CLK_CTRL_TSP_ON 0x0000000000000004ULL
214 #define ROGUE_CR_CLK_CTRL_TSP_AUTO 0x0000000000000008ULL
215 #define ROGUE_CR_CLK_CTRL_ISP_SHIFT 0U
216 #define ROGUE_CR_CLK_CTRL_ISP_CLRMSK 0xFFFFFFFFFFFFFFFCULL
217 #define ROGUE_CR_CLK_CTRL_ISP_OFF 0x0000000000000000ULL
218 #define ROGUE_CR_CLK_CTRL_ISP_ON 0x0000000000000001ULL
219 #define ROGUE_CR_CLK_CTRL_ISP_AUTO 0x0000000000000002ULL
220 
221 /* Register ROGUE_CR_CLK_STATUS */
222 #define ROGUE_CR_CLK_STATUS 0x0008U
223 #define ROGUE_CR_CLK_STATUS__PBE2_XE__MASKFULL 0x00000001FFF077FFULL
224 #define ROGUE_CR_CLK_STATUS__S7_TOP__MASKFULL 0x00000001B3101773ULL
225 #define ROGUE_CR_CLK_STATUS_MASKFULL 0x00000001FFF077FFULL
226 #define ROGUE_CR_CLK_STATUS_MCU_FBTC_SHIFT 32U
227 #define ROGUE_CR_CLK_STATUS_MCU_FBTC_CLRMSK 0xFFFFFFFEFFFFFFFFULL
228 #define ROGUE_CR_CLK_STATUS_MCU_FBTC_GATED 0x0000000000000000ULL
229 #define ROGUE_CR_CLK_STATUS_MCU_FBTC_RUNNING 0x0000000100000000ULL
230 #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_SHIFT 31U
231 #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_CLRMSK 0xFFFFFFFF7FFFFFFFULL
232 #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_GATED 0x0000000000000000ULL
233 #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_RUNNING 0x0000000080000000ULL
234 #define ROGUE_CR_CLK_STATUS_IPP_SHIFT 30U
235 #define ROGUE_CR_CLK_STATUS_IPP_CLRMSK 0xFFFFFFFFBFFFFFFFULL
236 #define ROGUE_CR_CLK_STATUS_IPP_GATED 0x0000000000000000ULL
237 #define ROGUE_CR_CLK_STATUS_IPP_RUNNING 0x0000000040000000ULL
238 #define ROGUE_CR_CLK_STATUS_FBC_SHIFT 29U
239 #define ROGUE_CR_CLK_STATUS_FBC_CLRMSK 0xFFFFFFFFDFFFFFFFULL
240 #define ROGUE_CR_CLK_STATUS_FBC_GATED 0x0000000000000000ULL
241 #define ROGUE_CR_CLK_STATUS_FBC_RUNNING 0x0000000020000000ULL
242 #define ROGUE_CR_CLK_STATUS_FBDC_SHIFT 28U
243 #define ROGUE_CR_CLK_STATUS_FBDC_CLRMSK 0xFFFFFFFFEFFFFFFFULL
244 #define ROGUE_CR_CLK_STATUS_FBDC_GATED 0x0000000000000000ULL
245 #define ROGUE_CR_CLK_STATUS_FBDC_RUNNING 0x0000000010000000ULL
246 #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_SHIFT 27U
247 #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_CLRMSK 0xFFFFFFFFF7FFFFFFULL
248 #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_GATED 0x0000000000000000ULL
249 #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_RUNNING 0x0000000008000000ULL
250 #define ROGUE_CR_CLK_STATUS_USCS_SHIFT 26U
251 #define ROGUE_CR_CLK_STATUS_USCS_CLRMSK 0xFFFFFFFFFBFFFFFFULL
252 #define ROGUE_CR_CLK_STATUS_USCS_GATED 0x0000000000000000ULL
253 #define ROGUE_CR_CLK_STATUS_USCS_RUNNING 0x0000000004000000ULL
254 #define ROGUE_CR_CLK_STATUS_PBE_SHIFT 25U
255 #define ROGUE_CR_CLK_STATUS_PBE_CLRMSK 0xFFFFFFFFFDFFFFFFULL
256 #define ROGUE_CR_CLK_STATUS_PBE_GATED 0x0000000000000000ULL
257 #define ROGUE_CR_CLK_STATUS_PBE_RUNNING 0x0000000002000000ULL
258 #define ROGUE_CR_CLK_STATUS_MCU_L1_SHIFT 24U
259 #define ROGUE_CR_CLK_STATUS_MCU_L1_CLRMSK 0xFFFFFFFFFEFFFFFFULL
260 #define ROGUE_CR_CLK_STATUS_MCU_L1_GATED 0x0000000000000000ULL
261 #define ROGUE_CR_CLK_STATUS_MCU_L1_RUNNING 0x0000000001000000ULL
262 #define ROGUE_CR_CLK_STATUS_CDM_SHIFT 23U
263 #define ROGUE_CR_CLK_STATUS_CDM_CLRMSK 0xFFFFFFFFFF7FFFFFULL
264 #define ROGUE_CR_CLK_STATUS_CDM_GATED 0x0000000000000000ULL
265 #define ROGUE_CR_CLK_STATUS_CDM_RUNNING 0x0000000000800000ULL
266 #define ROGUE_CR_CLK_STATUS_SIDEKICK_SHIFT 22U
267 #define ROGUE_CR_CLK_STATUS_SIDEKICK_CLRMSK 0xFFFFFFFFFFBFFFFFULL
268 #define ROGUE_CR_CLK_STATUS_SIDEKICK_GATED 0x0000000000000000ULL
269 #define ROGUE_CR_CLK_STATUS_SIDEKICK_RUNNING 0x0000000000400000ULL
270 #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_SHIFT 21U
271 #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_CLRMSK 0xFFFFFFFFFFDFFFFFULL
272 #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_GATED 0x0000000000000000ULL
273 #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_RUNNING 0x0000000000200000ULL
274 #define ROGUE_CR_CLK_STATUS_BIF_SHIFT 20U
275 #define ROGUE_CR_CLK_STATUS_BIF_CLRMSK 0xFFFFFFFFFFEFFFFFULL
276 #define ROGUE_CR_CLK_STATUS_BIF_GATED 0x0000000000000000ULL
277 #define ROGUE_CR_CLK_STATUS_BIF_RUNNING 0x0000000000100000ULL
278 #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_SHIFT 14U
279 #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFBFFFULL
280 #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_GATED 0x0000000000000000ULL
281 #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_RUNNING 0x0000000000004000ULL
282 #define ROGUE_CR_CLK_STATUS_MCU_L0_SHIFT 13U
283 #define ROGUE_CR_CLK_STATUS_MCU_L0_CLRMSK 0xFFFFFFFFFFFFDFFFULL
284 #define ROGUE_CR_CLK_STATUS_MCU_L0_GATED 0x0000000000000000ULL
285 #define ROGUE_CR_CLK_STATUS_MCU_L0_RUNNING 0x0000000000002000ULL
286 #define ROGUE_CR_CLK_STATUS_TPU_SHIFT 12U
287 #define ROGUE_CR_CLK_STATUS_TPU_CLRMSK 0xFFFFFFFFFFFFEFFFULL
288 #define ROGUE_CR_CLK_STATUS_TPU_GATED 0x0000000000000000ULL
289 #define ROGUE_CR_CLK_STATUS_TPU_RUNNING 0x0000000000001000ULL
290 #define ROGUE_CR_CLK_STATUS_USC_SHIFT 10U
291 #define ROGUE_CR_CLK_STATUS_USC_CLRMSK 0xFFFFFFFFFFFFFBFFULL
292 #define ROGUE_CR_CLK_STATUS_USC_GATED 0x0000000000000000ULL
293 #define ROGUE_CR_CLK_STATUS_USC_RUNNING 0x0000000000000400ULL
294 #define ROGUE_CR_CLK_STATUS_TLA_SHIFT 9U
295 #define ROGUE_CR_CLK_STATUS_TLA_CLRMSK 0xFFFFFFFFFFFFFDFFULL
296 #define ROGUE_CR_CLK_STATUS_TLA_GATED 0x0000000000000000ULL
297 #define ROGUE_CR_CLK_STATUS_TLA_RUNNING 0x0000000000000200ULL
298 #define ROGUE_CR_CLK_STATUS_SLC_SHIFT 8U
299 #define ROGUE_CR_CLK_STATUS_SLC_CLRMSK 0xFFFFFFFFFFFFFEFFULL
300 #define ROGUE_CR_CLK_STATUS_SLC_GATED 0x0000000000000000ULL
301 #define ROGUE_CR_CLK_STATUS_SLC_RUNNING 0x0000000000000100ULL
302 #define ROGUE_CR_CLK_STATUS_UVS_SHIFT 7U
303 #define ROGUE_CR_CLK_STATUS_UVS_CLRMSK 0xFFFFFFFFFFFFFF7FULL
304 #define ROGUE_CR_CLK_STATUS_UVS_GATED 0x0000000000000000ULL
305 #define ROGUE_CR_CLK_STATUS_UVS_RUNNING 0x0000000000000080ULL
306 #define ROGUE_CR_CLK_STATUS_PDS_SHIFT 6U
307 #define ROGUE_CR_CLK_STATUS_PDS_CLRMSK 0xFFFFFFFFFFFFFFBFULL
308 #define ROGUE_CR_CLK_STATUS_PDS_GATED 0x0000000000000000ULL
309 #define ROGUE_CR_CLK_STATUS_PDS_RUNNING 0x0000000000000040ULL
310 #define ROGUE_CR_CLK_STATUS_VDM_SHIFT 5U
311 #define ROGUE_CR_CLK_STATUS_VDM_CLRMSK 0xFFFFFFFFFFFFFFDFULL
312 #define ROGUE_CR_CLK_STATUS_VDM_GATED 0x0000000000000000ULL
313 #define ROGUE_CR_CLK_STATUS_VDM_RUNNING 0x0000000000000020ULL
314 #define ROGUE_CR_CLK_STATUS_PM_SHIFT 4U
315 #define ROGUE_CR_CLK_STATUS_PM_CLRMSK 0xFFFFFFFFFFFFFFEFULL
316 #define ROGUE_CR_CLK_STATUS_PM_GATED 0x0000000000000000ULL
317 #define ROGUE_CR_CLK_STATUS_PM_RUNNING 0x0000000000000010ULL
318 #define ROGUE_CR_CLK_STATUS_GPP_SHIFT 3U
319 #define ROGUE_CR_CLK_STATUS_GPP_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
320 #define ROGUE_CR_CLK_STATUS_GPP_GATED 0x0000000000000000ULL
321 #define ROGUE_CR_CLK_STATUS_GPP_RUNNING 0x0000000000000008ULL
322 #define ROGUE_CR_CLK_STATUS_TE_SHIFT 2U
323 #define ROGUE_CR_CLK_STATUS_TE_CLRMSK 0xFFFFFFFFFFFFFFFBULL
324 #define ROGUE_CR_CLK_STATUS_TE_GATED 0x0000000000000000ULL
325 #define ROGUE_CR_CLK_STATUS_TE_RUNNING 0x0000000000000004ULL
326 #define ROGUE_CR_CLK_STATUS_TSP_SHIFT 1U
327 #define ROGUE_CR_CLK_STATUS_TSP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
328 #define ROGUE_CR_CLK_STATUS_TSP_GATED 0x0000000000000000ULL
329 #define ROGUE_CR_CLK_STATUS_TSP_RUNNING 0x0000000000000002ULL
330 #define ROGUE_CR_CLK_STATUS_ISP_SHIFT 0U
331 #define ROGUE_CR_CLK_STATUS_ISP_CLRMSK 0xFFFFFFFFFFFFFFFEULL
332 #define ROGUE_CR_CLK_STATUS_ISP_GATED 0x0000000000000000ULL
333 #define ROGUE_CR_CLK_STATUS_ISP_RUNNING 0x0000000000000001ULL
334 
335 /* Register ROGUE_CR_CORE_ID */
336 #define ROGUE_CR_CORE_ID__PBVNC 0x0020U
337 #define ROGUE_CR_CORE_ID__PBVNC__MASKFULL 0xFFFFFFFFFFFFFFFFULL
338 #define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_SHIFT 48U
339 #define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_CLRMSK 0x0000FFFFFFFFFFFFULL
340 #define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_SHIFT 32U
341 #define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_CLRMSK 0xFFFF0000FFFFFFFFULL
342 #define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_SHIFT 16U
343 #define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_CLRMSK 0xFFFFFFFF0000FFFFULL
344 #define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_SHIFT 0U
345 #define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_CLRMSK 0xFFFFFFFFFFFF0000ULL
346 
347 /* Register ROGUE_CR_CORE_ID */
348 #define ROGUE_CR_CORE_ID 0x0018U
349 #define ROGUE_CR_CORE_ID_MASKFULL 0x00000000FFFFFFFFULL
350 #define ROGUE_CR_CORE_ID_ID_SHIFT 16U
351 #define ROGUE_CR_CORE_ID_ID_CLRMSK 0x0000FFFFU
352 #define ROGUE_CR_CORE_ID_CONFIG_SHIFT 0U
353 #define ROGUE_CR_CORE_ID_CONFIG_CLRMSK 0xFFFF0000U
354 
355 /* Register ROGUE_CR_CORE_REVISION */
356 #define ROGUE_CR_CORE_REVISION 0x0020U
357 #define ROGUE_CR_CORE_REVISION_MASKFULL 0x00000000FFFFFFFFULL
358 #define ROGUE_CR_CORE_REVISION_DESIGNER_SHIFT 24U
359 #define ROGUE_CR_CORE_REVISION_DESIGNER_CLRMSK 0x00FFFFFFU
360 #define ROGUE_CR_CORE_REVISION_MAJOR_SHIFT 16U
361 #define ROGUE_CR_CORE_REVISION_MAJOR_CLRMSK 0xFF00FFFFU
362 #define ROGUE_CR_CORE_REVISION_MINOR_SHIFT 8U
363 #define ROGUE_CR_CORE_REVISION_MINOR_CLRMSK 0xFFFF00FFU
364 #define ROGUE_CR_CORE_REVISION_MAINTENANCE_SHIFT 0U
365 #define ROGUE_CR_CORE_REVISION_MAINTENANCE_CLRMSK 0xFFFFFF00U
366 
367 /* Register ROGUE_CR_DESIGNER_REV_FIELD1 */
368 #define ROGUE_CR_DESIGNER_REV_FIELD1 0x0028U
369 #define ROGUE_CR_DESIGNER_REV_FIELD1_MASKFULL 0x00000000FFFFFFFFULL
370 #define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0U
371 #define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_CLRMSK 0x00000000U
372 
373 /* Register ROGUE_CR_DESIGNER_REV_FIELD2 */
374 #define ROGUE_CR_DESIGNER_REV_FIELD2 0x0030U
375 #define ROGUE_CR_DESIGNER_REV_FIELD2_MASKFULL 0x00000000FFFFFFFFULL
376 #define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0U
377 #define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_CLRMSK 0x00000000U
378 
379 /* Register ROGUE_CR_CHANGESET_NUMBER */
380 #define ROGUE_CR_CHANGESET_NUMBER 0x0040U
381 #define ROGUE_CR_CHANGESET_NUMBER_MASKFULL 0xFFFFFFFFFFFFFFFFULL
382 #define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_SHIFT 0U
383 #define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK 0x0000000000000000ULL
384 
385 /* Register ROGUE_CR_CLK_XTPLUS_CTRL */
386 #define ROGUE_CR_CLK_XTPLUS_CTRL 0x0080U
387 #define ROGUE_CR_CLK_XTPLUS_CTRL_MASKFULL 0x0000003FFFFF0000ULL
388 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_SHIFT 36U
389 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_CLRMSK 0xFFFFFFCFFFFFFFFFULL
390 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_OFF 0x0000000000000000ULL
391 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_ON 0x0000001000000000ULL
392 #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_AUTO 0x0000002000000000ULL
393 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_SHIFT 34U
394 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_CLRMSK 0xFFFFFFF3FFFFFFFFULL
395 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_OFF 0x0000000000000000ULL
396 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_ON 0x0000000400000000ULL
397 #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_AUTO 0x0000000800000000ULL
398 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_SHIFT 32U
399 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_CLRMSK 0xFFFFFFFCFFFFFFFFULL
400 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_OFF 0x0000000000000000ULL
401 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_ON 0x0000000100000000ULL
402 #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_AUTO 0x0000000200000000ULL
403 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_SHIFT 30U
404 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_CLRMSK 0xFFFFFFFF3FFFFFFFULL
405 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_OFF 0x0000000000000000ULL
406 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_ON 0x0000000040000000ULL
407 #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_AUTO 0x0000000080000000ULL
408 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_SHIFT 28U
409 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_CLRMSK 0xFFFFFFFFCFFFFFFFULL
410 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_OFF 0x0000000000000000ULL
411 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_ON 0x0000000010000000ULL
412 #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_AUTO 0x0000000020000000ULL
413 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_SHIFT 26U
414 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_CLRMSK 0xFFFFFFFFF3FFFFFFULL
415 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_OFF 0x0000000000000000ULL
416 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_ON 0x0000000004000000ULL
417 #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_AUTO 0x0000000008000000ULL
418 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_SHIFT 24U
419 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_CLRMSK 0xFFFFFFFFFCFFFFFFULL
420 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_OFF 0x0000000000000000ULL
421 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_ON 0x0000000001000000ULL
422 #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_AUTO 0x0000000002000000ULL
423 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_SHIFT 22U
424 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_CLRMSK 0xFFFFFFFFFF3FFFFFULL
425 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_OFF 0x0000000000000000ULL
426 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_ON 0x0000000000400000ULL
427 #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_AUTO 0x0000000000800000ULL
428 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_SHIFT 20U
429 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFCFFFFFULL
430 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_OFF 0x0000000000000000ULL
431 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_ON 0x0000000000100000ULL
432 #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_AUTO 0x0000000000200000ULL
433 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_SHIFT 18U
434 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_CLRMSK 0xFFFFFFFFFFF3FFFFULL
435 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_OFF 0x0000000000000000ULL
436 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_ON 0x0000000000040000ULL
437 #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_AUTO 0x0000000000080000ULL
438 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_SHIFT 16U
439 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_CLRMSK 0xFFFFFFFFFFFCFFFFULL
440 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_OFF 0x0000000000000000ULL
441 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_ON 0x0000000000010000ULL
442 #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_AUTO 0x0000000000020000ULL
443 
444 /* Register ROGUE_CR_CLK_XTPLUS_STATUS */
445 #define ROGUE_CR_CLK_XTPLUS_STATUS 0x0088U
446 #define ROGUE_CR_CLK_XTPLUS_STATUS_MASKFULL 0x00000000000007FFULL
447 #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_SHIFT 10U
448 #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_CLRMSK 0xFFFFFFFFFFFFFBFFULL
449 #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_GATED 0x0000000000000000ULL
450 #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_RUNNING 0x0000000000000400ULL
451 #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_SHIFT 9U
452 #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_CLRMSK 0xFFFFFFFFFFFFFDFFULL
453 #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_GATED 0x0000000000000000ULL
454 #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_RUNNING 0x0000000000000200ULL
455 #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_SHIFT 8U
456 #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFEFFULL
457 #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_GATED 0x0000000000000000ULL
458 #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_RUNNING 0x0000000000000100ULL
459 #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_SHIFT 7U
460 #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_CLRMSK 0xFFFFFFFFFFFFFF7FULL
461 #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_GATED 0x0000000000000000ULL
462 #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_RUNNING 0x0000000000000080ULL
463 #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_SHIFT 6U
464 #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFBFULL
465 #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_GATED 0x0000000000000000ULL
466 #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_RUNNING 0x0000000000000040ULL
467 #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_SHIFT 5U
468 #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_CLRMSK 0xFFFFFFFFFFFFFFDFULL
469 #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_GATED 0x0000000000000000ULL
470 #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_RUNNING 0x0000000000000020ULL
471 #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_SHIFT 4U
472 #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_CLRMSK 0xFFFFFFFFFFFFFFEFULL
473 #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_GATED 0x0000000000000000ULL
474 #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_RUNNING 0x0000000000000010ULL
475 #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_SHIFT 3U
476 #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
477 #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_GATED 0x0000000000000000ULL
478 #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_RUNNING 0x0000000000000008ULL
479 #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_SHIFT 2U
480 #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
481 #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_GATED 0x0000000000000000ULL
482 #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_RUNNING 0x0000000000000004ULL
483 #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_SHIFT 1U
484 #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_CLRMSK 0xFFFFFFFFFFFFFFFDULL
485 #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_GATED 0x0000000000000000ULL
486 #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_RUNNING 0x0000000000000002ULL
487 #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_SHIFT 0U
488 #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_CLRMSK 0xFFFFFFFFFFFFFFFEULL
489 #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_GATED 0x0000000000000000ULL
490 #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_RUNNING 0x0000000000000001ULL
491 
492 /* Register ROGUE_CR_SOFT_RESET */
493 #define ROGUE_CR_SOFT_RESET 0x0100U
494 #define ROGUE_CR_SOFT_RESET__PBE2_XE__MASKFULL 0xFFEFFFFFFFFFFC3DULL
495 #define ROGUE_CR_SOFT_RESET_MASKFULL 0x00E7FFFFFFFFFC3DULL
496 #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_SHIFT 63U
497 #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_CLRMSK 0x7FFFFFFFFFFFFFFFULL
498 #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_EN 0x8000000000000000ULL
499 #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_SHIFT 62U
500 #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_CLRMSK 0xBFFFFFFFFFFFFFFFULL
501 #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_EN 0x4000000000000000ULL
502 #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_SHIFT 61U
503 #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_CLRMSK 0xDFFFFFFFFFFFFFFFULL
504 #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_EN 0x2000000000000000ULL
505 #define ROGUE_CR_SOFT_RESET_JONES_CORE_SHIFT 60U
506 #define ROGUE_CR_SOFT_RESET_JONES_CORE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
507 #define ROGUE_CR_SOFT_RESET_JONES_CORE_EN 0x1000000000000000ULL
508 #define ROGUE_CR_SOFT_RESET_TILING_CORE_SHIFT 59U
509 #define ROGUE_CR_SOFT_RESET_TILING_CORE_CLRMSK 0xF7FFFFFFFFFFFFFFULL
510 #define ROGUE_CR_SOFT_RESET_TILING_CORE_EN 0x0800000000000000ULL
511 #define ROGUE_CR_SOFT_RESET_TE3_SHIFT 58U
512 #define ROGUE_CR_SOFT_RESET_TE3_CLRMSK 0xFBFFFFFFFFFFFFFFULL
513 #define ROGUE_CR_SOFT_RESET_TE3_EN 0x0400000000000000ULL
514 #define ROGUE_CR_SOFT_RESET_VCE_SHIFT 57U
515 #define ROGUE_CR_SOFT_RESET_VCE_CLRMSK 0xFDFFFFFFFFFFFFFFULL
516 #define ROGUE_CR_SOFT_RESET_VCE_EN 0x0200000000000000ULL
517 #define ROGUE_CR_SOFT_RESET_VBS_SHIFT 56U
518 #define ROGUE_CR_SOFT_RESET_VBS_CLRMSK 0xFEFFFFFFFFFFFFFFULL
519 #define ROGUE_CR_SOFT_RESET_VBS_EN 0x0100000000000000ULL
520 #define ROGUE_CR_SOFT_RESET_DPX1_CORE_SHIFT 55U
521 #define ROGUE_CR_SOFT_RESET_DPX1_CORE_CLRMSK 0xFF7FFFFFFFFFFFFFULL
522 #define ROGUE_CR_SOFT_RESET_DPX1_CORE_EN 0x0080000000000000ULL
523 #define ROGUE_CR_SOFT_RESET_DPX0_CORE_SHIFT 54U
524 #define ROGUE_CR_SOFT_RESET_DPX0_CORE_CLRMSK 0xFFBFFFFFFFFFFFFFULL
525 #define ROGUE_CR_SOFT_RESET_DPX0_CORE_EN 0x0040000000000000ULL
526 #define ROGUE_CR_SOFT_RESET_FBA_SHIFT 53U
527 #define ROGUE_CR_SOFT_RESET_FBA_CLRMSK 0xFFDFFFFFFFFFFFFFULL
528 #define ROGUE_CR_SOFT_RESET_FBA_EN 0x0020000000000000ULL
529 #define ROGUE_CR_SOFT_RESET_FB_CDC_SHIFT 51U
530 #define ROGUE_CR_SOFT_RESET_FB_CDC_CLRMSK 0xFFF7FFFFFFFFFFFFULL
531 #define ROGUE_CR_SOFT_RESET_FB_CDC_EN 0x0008000000000000ULL
532 #define ROGUE_CR_SOFT_RESET_SH_SHIFT 50U
533 #define ROGUE_CR_SOFT_RESET_SH_CLRMSK 0xFFFBFFFFFFFFFFFFULL
534 #define ROGUE_CR_SOFT_RESET_SH_EN 0x0004000000000000ULL
535 #define ROGUE_CR_SOFT_RESET_VRDM_SHIFT 49U
536 #define ROGUE_CR_SOFT_RESET_VRDM_CLRMSK 0xFFFDFFFFFFFFFFFFULL
537 #define ROGUE_CR_SOFT_RESET_VRDM_EN 0x0002000000000000ULL
538 #define ROGUE_CR_SOFT_RESET_MCU_FBTC_SHIFT 48U
539 #define ROGUE_CR_SOFT_RESET_MCU_FBTC_CLRMSK 0xFFFEFFFFFFFFFFFFULL
540 #define ROGUE_CR_SOFT_RESET_MCU_FBTC_EN 0x0001000000000000ULL
541 #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_SHIFT 47U
542 #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_CLRMSK 0xFFFF7FFFFFFFFFFFULL
543 #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_EN 0x0000800000000000ULL
544 #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_SHIFT 46U
545 #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_CLRMSK 0xFFFFBFFFFFFFFFFFULL
546 #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_EN 0x0000400000000000ULL
547 #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_SHIFT 45U
548 #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_CLRMSK 0xFFFFDFFFFFFFFFFFULL
549 #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_EN 0x0000200000000000ULL
550 #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_SHIFT 44U
551 #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_CLRMSK 0xFFFFEFFFFFFFFFFFULL
552 #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_EN 0x0000100000000000ULL
553 #define ROGUE_CR_SOFT_RESET_IPP_SHIFT 43U
554 #define ROGUE_CR_SOFT_RESET_IPP_CLRMSK 0xFFFFF7FFFFFFFFFFULL
555 #define ROGUE_CR_SOFT_RESET_IPP_EN 0x0000080000000000ULL
556 #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_SHIFT 42U
557 #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_CLRMSK 0xFFFFFBFFFFFFFFFFULL
558 #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_EN 0x0000040000000000ULL
559 #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_SHIFT 41U
560 #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_CLRMSK 0xFFFFFDFFFFFFFFFFULL
561 #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_EN 0x0000020000000000ULL
562 #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_SHIFT 40U
563 #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_CLRMSK 0xFFFFFEFFFFFFFFFFULL
564 #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN 0x0000010000000000ULL
565 #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_SHIFT 39U
566 #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_CLRMSK 0xFFFFFF7FFFFFFFFFULL
567 #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN 0x0000008000000000ULL
568 #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_SHIFT 38U
569 #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_CLRMSK 0xFFFFFFBFFFFFFFFFULL
570 #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN 0x0000004000000000ULL
571 #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_SHIFT 37U
572 #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_CLRMSK 0xFFFFFFDFFFFFFFFFULL
573 #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN 0x0000002000000000ULL
574 #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_SHIFT 36U
575 #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_CLRMSK 0xFFFFFFEFFFFFFFFFULL
576 #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN 0x0000001000000000ULL
577 #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_SHIFT 35U
578 #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_CLRMSK 0xFFFFFFF7FFFFFFFFULL
579 #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN 0x0000000800000000ULL
580 #define ROGUE_CR_SOFT_RESET_MMU_SHIFT 34U
581 #define ROGUE_CR_SOFT_RESET_MMU_CLRMSK 0xFFFFFFFBFFFFFFFFULL
582 #define ROGUE_CR_SOFT_RESET_MMU_EN 0x0000000400000000ULL
583 #define ROGUE_CR_SOFT_RESET_BIF1_SHIFT 33U
584 #define ROGUE_CR_SOFT_RESET_BIF1_CLRMSK 0xFFFFFFFDFFFFFFFFULL
585 #define ROGUE_CR_SOFT_RESET_BIF1_EN 0x0000000200000000ULL
586 #define ROGUE_CR_SOFT_RESET_GARTEN_SHIFT 32U
587 #define ROGUE_CR_SOFT_RESET_GARTEN_CLRMSK 0xFFFFFFFEFFFFFFFFULL
588 #define ROGUE_CR_SOFT_RESET_GARTEN_EN 0x0000000100000000ULL
589 #define ROGUE_CR_SOFT_RESET_CPU_SHIFT 32U
590 #define ROGUE_CR_SOFT_RESET_CPU_CLRMSK 0xFFFFFFFEFFFFFFFFULL
591 #define ROGUE_CR_SOFT_RESET_CPU_EN 0x0000000100000000ULL
592 #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_SHIFT 31U
593 #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
594 #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN 0x0000000080000000ULL
595 #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_SHIFT 30U
596 #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_CLRMSK 0xFFFFFFFFBFFFFFFFULL
597 #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN 0x0000000040000000ULL
598 #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_SHIFT 29U
599 #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_CLRMSK 0xFFFFFFFFDFFFFFFFULL
600 #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN 0x0000000020000000ULL
601 #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_SHIFT 28U
602 #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_CLRMSK 0xFFFFFFFFEFFFFFFFULL
603 #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_EN 0x0000000010000000ULL
604 #define ROGUE_CR_SOFT_RESET_SLC_SHIFT 27U
605 #define ROGUE_CR_SOFT_RESET_SLC_CLRMSK 0xFFFFFFFFF7FFFFFFULL
606 #define ROGUE_CR_SOFT_RESET_SLC_EN 0x0000000008000000ULL
607 #define ROGUE_CR_SOFT_RESET_TLA_SHIFT 26U
608 #define ROGUE_CR_SOFT_RESET_TLA_CLRMSK 0xFFFFFFFFFBFFFFFFULL
609 #define ROGUE_CR_SOFT_RESET_TLA_EN 0x0000000004000000ULL
610 #define ROGUE_CR_SOFT_RESET_UVS_SHIFT 25U
611 #define ROGUE_CR_SOFT_RESET_UVS_CLRMSK 0xFFFFFFFFFDFFFFFFULL
612 #define ROGUE_CR_SOFT_RESET_UVS_EN 0x0000000002000000ULL
613 #define ROGUE_CR_SOFT_RESET_TE_SHIFT 24U
614 #define ROGUE_CR_SOFT_RESET_TE_CLRMSK 0xFFFFFFFFFEFFFFFFULL
615 #define ROGUE_CR_SOFT_RESET_TE_EN 0x0000000001000000ULL
616 #define ROGUE_CR_SOFT_RESET_GPP_SHIFT 23U
617 #define ROGUE_CR_SOFT_RESET_GPP_CLRMSK 0xFFFFFFFFFF7FFFFFULL
618 #define ROGUE_CR_SOFT_RESET_GPP_EN 0x0000000000800000ULL
619 #define ROGUE_CR_SOFT_RESET_FBDC_SHIFT 22U
620 #define ROGUE_CR_SOFT_RESET_FBDC_CLRMSK 0xFFFFFFFFFFBFFFFFULL
621 #define ROGUE_CR_SOFT_RESET_FBDC_EN 0x0000000000400000ULL
622 #define ROGUE_CR_SOFT_RESET_FBC_SHIFT 21U
623 #define ROGUE_CR_SOFT_RESET_FBC_CLRMSK 0xFFFFFFFFFFDFFFFFULL
624 #define ROGUE_CR_SOFT_RESET_FBC_EN 0x0000000000200000ULL
625 #define ROGUE_CR_SOFT_RESET_PM_SHIFT 20U
626 #define ROGUE_CR_SOFT_RESET_PM_CLRMSK 0xFFFFFFFFFFEFFFFFULL
627 #define ROGUE_CR_SOFT_RESET_PM_EN 0x0000000000100000ULL
628 #define ROGUE_CR_SOFT_RESET_PBE_SHIFT 19U
629 #define ROGUE_CR_SOFT_RESET_PBE_CLRMSK 0xFFFFFFFFFFF7FFFFULL
630 #define ROGUE_CR_SOFT_RESET_PBE_EN 0x0000000000080000ULL
631 #define ROGUE_CR_SOFT_RESET_USC_SHARED_SHIFT 18U
632 #define ROGUE_CR_SOFT_RESET_USC_SHARED_CLRMSK 0xFFFFFFFFFFFBFFFFULL
633 #define ROGUE_CR_SOFT_RESET_USC_SHARED_EN 0x0000000000040000ULL
634 #define ROGUE_CR_SOFT_RESET_MCU_L1_SHIFT 17U
635 #define ROGUE_CR_SOFT_RESET_MCU_L1_CLRMSK 0xFFFFFFFFFFFDFFFFULL
636 #define ROGUE_CR_SOFT_RESET_MCU_L1_EN 0x0000000000020000ULL
637 #define ROGUE_CR_SOFT_RESET_BIF_SHIFT 16U
638 #define ROGUE_CR_SOFT_RESET_BIF_CLRMSK 0xFFFFFFFFFFFEFFFFULL
639 #define ROGUE_CR_SOFT_RESET_BIF_EN 0x0000000000010000ULL
640 #define ROGUE_CR_SOFT_RESET_CDM_SHIFT 15U
641 #define ROGUE_CR_SOFT_RESET_CDM_CLRMSK 0xFFFFFFFFFFFF7FFFULL
642 #define ROGUE_CR_SOFT_RESET_CDM_EN 0x0000000000008000ULL
643 #define ROGUE_CR_SOFT_RESET_VDM_SHIFT 14U
644 #define ROGUE_CR_SOFT_RESET_VDM_CLRMSK 0xFFFFFFFFFFFFBFFFULL
645 #define ROGUE_CR_SOFT_RESET_VDM_EN 0x0000000000004000ULL
646 #define ROGUE_CR_SOFT_RESET_TESS_SHIFT 13U
647 #define ROGUE_CR_SOFT_RESET_TESS_CLRMSK 0xFFFFFFFFFFFFDFFFULL
648 #define ROGUE_CR_SOFT_RESET_TESS_EN 0x0000000000002000ULL
649 #define ROGUE_CR_SOFT_RESET_PDS_SHIFT 12U
650 #define ROGUE_CR_SOFT_RESET_PDS_CLRMSK 0xFFFFFFFFFFFFEFFFULL
651 #define ROGUE_CR_SOFT_RESET_PDS_EN 0x0000000000001000ULL
652 #define ROGUE_CR_SOFT_RESET_ISP_SHIFT 11U
653 #define ROGUE_CR_SOFT_RESET_ISP_CLRMSK 0xFFFFFFFFFFFFF7FFULL
654 #define ROGUE_CR_SOFT_RESET_ISP_EN 0x0000000000000800ULL
655 #define ROGUE_CR_SOFT_RESET_TSP_SHIFT 10U
656 #define ROGUE_CR_SOFT_RESET_TSP_CLRMSK 0xFFFFFFFFFFFFFBFFULL
657 #define ROGUE_CR_SOFT_RESET_TSP_EN 0x0000000000000400ULL
658 #define ROGUE_CR_SOFT_RESET_SYSARB_SHIFT 5U
659 #define ROGUE_CR_SOFT_RESET_SYSARB_CLRMSK 0xFFFFFFFFFFFFFFDFULL
660 #define ROGUE_CR_SOFT_RESET_SYSARB_EN 0x0000000000000020ULL
661 #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_SHIFT 4U
662 #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFFFEFULL
663 #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_EN 0x0000000000000010ULL
664 #define ROGUE_CR_SOFT_RESET_MCU_L0_SHIFT 3U
665 #define ROGUE_CR_SOFT_RESET_MCU_L0_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
666 #define ROGUE_CR_SOFT_RESET_MCU_L0_EN 0x0000000000000008ULL
667 #define ROGUE_CR_SOFT_RESET_TPU_SHIFT 2U
668 #define ROGUE_CR_SOFT_RESET_TPU_CLRMSK 0xFFFFFFFFFFFFFFFBULL
669 #define ROGUE_CR_SOFT_RESET_TPU_EN 0x0000000000000004ULL
670 #define ROGUE_CR_SOFT_RESET_USC_SHIFT 0U
671 #define ROGUE_CR_SOFT_RESET_USC_CLRMSK 0xFFFFFFFFFFFFFFFEULL
672 #define ROGUE_CR_SOFT_RESET_USC_EN 0x0000000000000001ULL
673 
674 /* Register ROGUE_CR_SOFT_RESET2 */
675 #define ROGUE_CR_SOFT_RESET2 0x0108U
676 #define ROGUE_CR_SOFT_RESET2_MASKFULL 0x00000000001FFFFFULL
677 #define ROGUE_CR_SOFT_RESET2_SPFILTER_SHIFT 12U
678 #define ROGUE_CR_SOFT_RESET2_SPFILTER_CLRMSK 0xFFE00FFFU
679 #define ROGUE_CR_SOFT_RESET2_TDM_SHIFT 11U
680 #define ROGUE_CR_SOFT_RESET2_TDM_CLRMSK 0xFFFFF7FFU
681 #define ROGUE_CR_SOFT_RESET2_TDM_EN 0x00000800U
682 #define ROGUE_CR_SOFT_RESET2_ASTC_SHIFT 10U
683 #define ROGUE_CR_SOFT_RESET2_ASTC_CLRMSK 0xFFFFFBFFU
684 #define ROGUE_CR_SOFT_RESET2_ASTC_EN 0x00000400U
685 #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_SHIFT 9U
686 #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_CLRMSK 0xFFFFFDFFU
687 #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN 0x00000200U
688 #define ROGUE_CR_SOFT_RESET2_USCPS_SHIFT 8U
689 #define ROGUE_CR_SOFT_RESET2_USCPS_CLRMSK 0xFFFFFEFFU
690 #define ROGUE_CR_SOFT_RESET2_USCPS_EN 0x00000100U
691 #define ROGUE_CR_SOFT_RESET2_IPF_SHIFT 7U
692 #define ROGUE_CR_SOFT_RESET2_IPF_CLRMSK 0xFFFFFF7FU
693 #define ROGUE_CR_SOFT_RESET2_IPF_EN 0x00000080U
694 #define ROGUE_CR_SOFT_RESET2_GEOMETRY_SHIFT 6U
695 #define ROGUE_CR_SOFT_RESET2_GEOMETRY_CLRMSK 0xFFFFFFBFU
696 #define ROGUE_CR_SOFT_RESET2_GEOMETRY_EN 0x00000040U
697 #define ROGUE_CR_SOFT_RESET2_USC_SHARED_SHIFT 5U
698 #define ROGUE_CR_SOFT_RESET2_USC_SHARED_CLRMSK 0xFFFFFFDFU
699 #define ROGUE_CR_SOFT_RESET2_USC_SHARED_EN 0x00000020U
700 #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_SHIFT 4U
701 #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_CLRMSK 0xFFFFFFEFU
702 #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_EN 0x00000010U
703 #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_SHIFT 3U
704 #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_CLRMSK 0xFFFFFFF7U
705 #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_EN 0x00000008U
706 #define ROGUE_CR_SOFT_RESET2_PIXEL_SHIFT 2U
707 #define ROGUE_CR_SOFT_RESET2_PIXEL_CLRMSK 0xFFFFFFFBU
708 #define ROGUE_CR_SOFT_RESET2_PIXEL_EN 0x00000004U
709 #define ROGUE_CR_SOFT_RESET2_CDM_SHIFT 1U
710 #define ROGUE_CR_SOFT_RESET2_CDM_CLRMSK 0xFFFFFFFDU
711 #define ROGUE_CR_SOFT_RESET2_CDM_EN 0x00000002U
712 #define ROGUE_CR_SOFT_RESET2_VERTEX_SHIFT 0U
713 #define ROGUE_CR_SOFT_RESET2_VERTEX_CLRMSK 0xFFFFFFFEU
714 #define ROGUE_CR_SOFT_RESET2_VERTEX_EN 0x00000001U
715 
716 /* Register ROGUE_CR_EVENT_STATUS */
717 #define ROGUE_CR_EVENT_STATUS 0x0130U
718 #define ROGUE_CR_EVENT_STATUS__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL
719 #define ROGUE_CR_EVENT_STATUS__SIGNALS__MASKFULL 0x00000000E007FFFFULL
720 #define ROGUE_CR_EVENT_STATUS_MASKFULL 0x00000000FFFFFFFFULL
721 #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT 31U
722 #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU
723 #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_EN 0x80000000U
724 #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT 30U
725 #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU
726 #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_EN 0x40000000U
727 #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT 29U
728 #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU
729 #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U
730 #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_SHIFT 28U
731 #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU
732 #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_EN 0x10000000U
733 #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_SHIFT 27U
734 #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU
735 #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_EN 0x08000000U
736 #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_SHIFT 26U
737 #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU
738 #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_EN 0x04000000U
739 #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_SHIFT 25U
740 #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU
741 #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_EN 0x02000000U
742 #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_SHIFT 24U
743 #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU
744 #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_EN 0x01000000U
745 #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_SHIFT 23U
746 #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU
747 #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_EN 0x00800000U
748 #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_SHIFT 22U
749 #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU
750 #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_EN 0x00400000U
751 #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_SHIFT 21U
752 #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU
753 #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_EN 0x00200000U
754 #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_SHIFT 20U
755 #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU
756 #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_EN 0x00100000U
757 #define ROGUE_CR_EVENT_STATUS_SAFETY_SHIFT 20U
758 #define ROGUE_CR_EVENT_STATUS_SAFETY_CLRMSK 0xFFEFFFFFU
759 #define ROGUE_CR_EVENT_STATUS_SAFETY_EN 0x00100000U
760 #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_SHIFT 19U
761 #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU
762 #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_EN 0x00080000U
763 #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_SHIFT 19U
764 #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_CLRMSK 0xFFF7FFFFU
765 #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_EN 0x00080000U
766 #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_SHIFT 18U
767 #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU
768 #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_EN 0x00040000U
769 #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U
770 #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU
771 #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U
772 #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_SHIFT 17U
773 #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_CLRMSK 0xFFFDFFFFU
774 #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_EN 0x00020000U
775 #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT 17U
776 #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU
777 #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U
778 #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT 16U
779 #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU
780 #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_EN 0x00010000U
781 #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_SHIFT 15U
782 #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_CLRMSK 0xFFFF7FFFU
783 #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_EN 0x00008000U
784 #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_SHIFT 14U
785 #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU
786 #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_EN 0x00004000U
787 #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_SHIFT 13U
788 #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_CLRMSK 0xFFFFDFFFU
789 #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_EN 0x00002000U
790 #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_SHIFT 12U
791 #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_CLRMSK 0xFFFFEFFFU
792 #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_EN 0x00001000U
793 #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_SHIFT 11U
794 #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_CLRMSK 0xFFFFF7FFU
795 #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_EN 0x00000800U
796 #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT 10U
797 #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU
798 #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_EN 0x00000400U
799 #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT 9U
800 #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU
801 #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_EN 0x00000200U
802 #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_SHIFT 8U
803 #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU
804 #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_EN 0x00000100U
805 #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT 7U
806 #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU
807 #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_EN 0x00000080U
808 #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 6U
809 #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_CLRMSK 0xFFFFFFBFU
810 #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_EN 0x00000040U
811 #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_SHIFT 5U
812 #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_CLRMSK 0xFFFFFFDFU
813 #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_EN 0x00000020U
814 #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT 4U
815 #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU
816 #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_EN 0x00000010U
817 #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 3U
818 #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U
819 #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_EN 0x00000008U
820 #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT 2U
821 #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU
822 #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_EN 0x00000004U
823 #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT 1U
824 #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU
825 #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_EN 0x00000002U
826 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_SHIFT 0U
827 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
828 #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U
829 
830 /* Register ROGUE_CR_TIMER */
831 #define ROGUE_CR_TIMER 0x0160U
832 #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL
833 #define ROGUE_CR_TIMER_BIT31_SHIFT 63U
834 #define ROGUE_CR_TIMER_BIT31_CLRMSK 0x7FFFFFFFFFFFFFFFULL
835 #define ROGUE_CR_TIMER_BIT31_EN 0x8000000000000000ULL
836 #define ROGUE_CR_TIMER_VALUE_SHIFT 0U
837 #define ROGUE_CR_TIMER_VALUE_CLRMSK 0xFFFF000000000000ULL
838 
839 /* Register ROGUE_CR_TLA_STATUS */
840 #define ROGUE_CR_TLA_STATUS 0x0178U
841 #define ROGUE_CR_TLA_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
842 #define ROGUE_CR_TLA_STATUS_BLIT_COUNT_SHIFT 39U
843 #define ROGUE_CR_TLA_STATUS_BLIT_COUNT_CLRMSK 0x0000007FFFFFFFFFULL
844 #define ROGUE_CR_TLA_STATUS_REQUEST_SHIFT 7U
845 #define ROGUE_CR_TLA_STATUS_REQUEST_CLRMSK 0xFFFFFF800000007FULL
846 #define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_SHIFT 1U
847 #define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_CLRMSK 0xFFFFFFFFFFFFFF81ULL
848 #define ROGUE_CR_TLA_STATUS_BUSY_SHIFT 0U
849 #define ROGUE_CR_TLA_STATUS_BUSY_CLRMSK 0xFFFFFFFFFFFFFFFEULL
850 #define ROGUE_CR_TLA_STATUS_BUSY_EN 0x0000000000000001ULL
851 
852 /* Register ROGUE_CR_PM_PARTIAL_RENDER_ENABLE */
853 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE 0x0338U
854 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_MASKFULL 0x0000000000000001ULL
855 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT 0U
856 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_CLRMSK 0xFFFFFFFEU
857 #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_EN 0x00000001U
858 
859 /* Register ROGUE_CR_SIDEKICK_IDLE */
860 #define ROGUE_CR_SIDEKICK_IDLE 0x03C8U
861 #define ROGUE_CR_SIDEKICK_IDLE_MASKFULL 0x000000000000007FULL
862 #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_SHIFT 6U
863 #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_CLRMSK 0xFFFFFFBFU
864 #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_EN 0x00000040U
865 #define ROGUE_CR_SIDEKICK_IDLE_MMU_SHIFT 5U
866 #define ROGUE_CR_SIDEKICK_IDLE_MMU_CLRMSK 0xFFFFFFDFU
867 #define ROGUE_CR_SIDEKICK_IDLE_MMU_EN 0x00000020U
868 #define ROGUE_CR_SIDEKICK_IDLE_BIF128_SHIFT 4U
869 #define ROGUE_CR_SIDEKICK_IDLE_BIF128_CLRMSK 0xFFFFFFEFU
870 #define ROGUE_CR_SIDEKICK_IDLE_BIF128_EN 0x00000010U
871 #define ROGUE_CR_SIDEKICK_IDLE_TLA_SHIFT 3U
872 #define ROGUE_CR_SIDEKICK_IDLE_TLA_CLRMSK 0xFFFFFFF7U
873 #define ROGUE_CR_SIDEKICK_IDLE_TLA_EN 0x00000008U
874 #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_SHIFT 2U
875 #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_CLRMSK 0xFFFFFFFBU
876 #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN 0x00000004U
877 #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_SHIFT 1U
878 #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_CLRMSK 0xFFFFFFFDU
879 #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN 0x00000002U
880 #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_SHIFT 0U
881 #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU
882 #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN 0x00000001U
883 
884 /* Register ROGUE_CR_MARS_IDLE */
885 #define ROGUE_CR_MARS_IDLE 0x08F8U
886 #define ROGUE_CR_MARS_IDLE_MASKFULL 0x0000000000000007ULL
887 #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_SHIFT 2U
888 #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFFFBU
889 #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN 0x00000004U
890 #define ROGUE_CR_MARS_IDLE_CPU_SHIFT 1U
891 #define ROGUE_CR_MARS_IDLE_CPU_CLRMSK 0xFFFFFFFDU
892 #define ROGUE_CR_MARS_IDLE_CPU_EN 0x00000002U
893 #define ROGUE_CR_MARS_IDLE_SOCIF_SHIFT 0U
894 #define ROGUE_CR_MARS_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU
895 #define ROGUE_CR_MARS_IDLE_SOCIF_EN 0x00000001U
896 
897 /* Register ROGUE_CR_VDM_CONTEXT_STORE_STATUS */
898 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS 0x0430U
899 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_MASKFULL 0x00000000000000F3ULL
900 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_SHIFT 4U
901 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_CLRMSK 0xFFFFFF0FU
902 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
903 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU
904 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U
905 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
906 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU
907 #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U
908 
909 /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK0 */
910 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0 0x0438U
911 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL
912 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_SHIFT 32U
913 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL
914 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_SHIFT 0U
915 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL
916 
917 /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK1 */
918 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1 0x0440U
919 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_MASKFULL 0x00000000FFFFFFFFULL
920 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_SHIFT 0U
921 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_CLRMSK 0x00000000U
922 
923 /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK2 */
924 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2 0x0448U
925 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
926 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_SHIFT 32U
927 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL
928 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_SHIFT 0U
929 #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL
930 
931 /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 */
932 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 0x0450U
933 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL
934 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_SHIFT 32U
935 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL
936 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_SHIFT 0U
937 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL
938 
939 /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 */
940 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 0x0458U
941 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_MASKFULL 0x00000000FFFFFFFFULL
942 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_SHIFT 0U
943 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_CLRMSK 0x00000000U
944 
945 /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 */
946 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 0x0460U
947 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
948 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_SHIFT 32U
949 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL
950 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_SHIFT 0U
951 #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL
952 
953 /* Register ROGUE_CR_CDM_CONTEXT_STORE_STATUS */
954 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS 0x04A0U
955 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_MASKFULL 0x0000000000000003ULL
956 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
957 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU
958 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U
959 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
960 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU
961 #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U
962 
963 /* Register ROGUE_CR_CDM_CONTEXT_PDS0 */
964 #define ROGUE_CR_CDM_CONTEXT_PDS0 0x04A8U
965 #define ROGUE_CR_CDM_CONTEXT_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
966 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT 36U
967 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
968 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT 4U
969 #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE 16U
970 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT 4U
971 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
972 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT 4U
973 #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE 16U
974 
975 /* Register ROGUE_CR_CDM_CONTEXT_PDS1 */
976 #define ROGUE_CR_CDM_CONTEXT_PDS1 0x04B0U
977 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
978 #define ROGUE_CR_CDM_CONTEXT_PDS1_MASKFULL 0x000000003FFFFFFFULL
979 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
980 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
981 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
982 #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT 29U
983 #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
984 #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_EN 0x20000000U
985 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
986 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
987 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
988 #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT 28U
989 #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
990 #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_EN 0x10000000U
991 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
992 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
993 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
994 #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT 27U
995 #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
996 #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_EN 0x08000000U
997 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
998 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
999 #define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT 21U
1000 #define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
1001 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1002 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
1003 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
1004 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_SHIFT 20U
1005 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
1006 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_EN 0x00100000U
1007 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1008 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
1009 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_SHIFT 11U
1010 #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
1011 #define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT 7U
1012 #define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
1013 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1014 #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
1015 #define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT 1U
1016 #define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
1017 #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_SHIFT 0U
1018 #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
1019 #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_EN 0x00000001U
1020 
1021 /* Register ROGUE_CR_CDM_TERMINATE_PDS */
1022 #define ROGUE_CR_CDM_TERMINATE_PDS 0x04B8U
1023 #define ROGUE_CR_CDM_TERMINATE_PDS_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
1024 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT 36U
1025 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
1026 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT 4U
1027 #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE 16U
1028 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT 4U
1029 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
1030 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT 4U
1031 #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE 16U
1032 
1033 /* Register ROGUE_CR_CDM_TERMINATE_PDS1 */
1034 #define ROGUE_CR_CDM_TERMINATE_PDS1 0x04C0U
1035 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
1036 #define ROGUE_CR_CDM_TERMINATE_PDS1_MASKFULL 0x000000003FFFFFFFULL
1037 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
1038 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
1039 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
1040 #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT 29U
1041 #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
1042 #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_EN 0x20000000U
1043 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
1044 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
1045 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
1046 #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT 28U
1047 #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
1048 #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_EN 0x10000000U
1049 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
1050 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
1051 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
1052 #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_SHIFT 27U
1053 #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
1054 #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_EN 0x08000000U
1055 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
1056 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
1057 #define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT 21U
1058 #define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
1059 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1060 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
1061 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
1062 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_SHIFT 20U
1063 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
1064 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_EN 0x00100000U
1065 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1066 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
1067 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_SHIFT 11U
1068 #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
1069 #define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT 7U
1070 #define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
1071 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1072 #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
1073 #define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT 1U
1074 #define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
1075 #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_SHIFT 0U
1076 #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
1077 #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_EN 0x00000001U
1078 
1079 /* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 */
1080 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 0x04D8U
1081 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
1082 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT 36U
1083 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
1084 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT 4U
1085 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE 16U
1086 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT 4U
1087 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
1088 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT 4U
1089 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE 16U
1090 
1091 /* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 */
1092 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 0x04E0U
1093 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
1094 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_MASKFULL 0x000000003FFFFFFFULL
1095 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
1096 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
1097 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
1098 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT 29U
1099 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
1100 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_EN 0x20000000U
1101 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
1102 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
1103 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
1104 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT 28U
1105 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
1106 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_EN 0x10000000U
1107 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
1108 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
1109 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
1110 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_SHIFT 27U
1111 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
1112 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_EN 0x08000000U
1113 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
1114 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
1115 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT 21U
1116 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
1117 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
1118 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
1119 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
1120 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_SHIFT 20U
1121 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
1122 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_EN 0x00100000U
1123 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
1124 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
1125 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_SHIFT 11U
1126 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
1127 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT 7U
1128 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
1129 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
1130 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
1131 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT 1U
1132 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
1133 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_SHIFT 0U
1134 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
1135 #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_EN 0x00000001U
1136 
1137 /* Register ROGUE_CR_MIPS_WRAPPER_CONFIG */
1138 #define ROGUE_CR_MIPS_WRAPPER_CONFIG 0x0810U
1139 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_MASKFULL 0x000001030F01FFFFULL
1140 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_SHIFT 40U
1141 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_CLRMSK 0xFFFFFEFFFFFFFFFFULL
1142 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_EN 0x0000010000000000ULL
1143 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_SHIFT 33U
1144 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_CLRMSK 0xFFFFFFFDFFFFFFFFULL
1145 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_EN 0x0000000200000000ULL
1146 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_SHIFT 32U
1147 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_CLRMSK 0xFFFFFFFEFFFFFFFFULL
1148 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_EN 0x0000000100000000ULL
1149 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_SHIFT 25U
1150 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_CLRMSK 0xFFFFFFFFF1FFFFFFULL
1151 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_SHIFT 24U
1152 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFEFFFFFFULL
1153 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_EN 0x0000000001000000ULL
1154 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_SHIFT 16U
1155 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_CLRMSK 0xFFFFFFFFFFFEFFFFULL
1156 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MIPS32 0x0000000000000000ULL
1157 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS 0x0000000000010000ULL
1158 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_SHIFT 0U
1159 #define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_CLRMSK 0xFFFFFFFFFFFF0000ULL
1160 
1161 /* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 */
1162 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 0x0818U
1163 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
1164 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1165 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1166 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_SHIFT 0U
1167 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1168 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
1169 
1170 /* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 */
1171 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 0x0820U
1172 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
1173 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_SHIFT 12U
1174 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
1175 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_SHIFT 6U
1176 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
1177 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_SHIFT 5U
1178 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
1179 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
1180 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1181 #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
1182 
1183 /* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 */
1184 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 0x0828U
1185 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
1186 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1187 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1188 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_SHIFT 0U
1189 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1190 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
1191 
1192 /* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 */
1193 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 0x0830U
1194 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
1195 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_SHIFT 12U
1196 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
1197 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_SHIFT 6U
1198 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
1199 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_SHIFT 5U
1200 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
1201 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
1202 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1203 #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
1204 
1205 /* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 */
1206 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 0x0838U
1207 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
1208 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1209 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1210 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_SHIFT 0U
1211 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1212 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
1213 
1214 /* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 */
1215 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 0x0840U
1216 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
1217 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_SHIFT 12U
1218 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
1219 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_SHIFT 6U
1220 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
1221 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_SHIFT 5U
1222 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
1223 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
1224 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1225 #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
1226 
1227 /* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 */
1228 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 0x0848U
1229 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
1230 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1231 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1232 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_SHIFT 0U
1233 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1234 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
1235 
1236 /* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 */
1237 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 0x0850U
1238 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
1239 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_SHIFT 12U
1240 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
1241 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_SHIFT 6U
1242 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
1243 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_SHIFT 5U
1244 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
1245 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
1246 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1247 #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
1248 
1249 /* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 */
1250 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 0x0858U
1251 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
1252 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_SHIFT 12U
1253 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1254 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_SHIFT 0U
1255 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1256 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
1257 
1258 /* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 */
1259 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 0x0860U
1260 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
1261 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_SHIFT 12U
1262 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
1263 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_SHIFT 6U
1264 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
1265 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_SHIFT 5U
1266 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
1267 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
1268 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
1269 #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
1270 
1271 /* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS */
1272 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS 0x0868U
1273 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_MASKFULL 0x00000001FFFFFFFFULL
1274 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_SHIFT 32U
1275 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_CLRMSK 0xFFFFFFFEFFFFFFFFULL
1276 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_EN 0x0000000100000000ULL
1277 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_SHIFT 0U
1278 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_CLRMSK 0xFFFFFFFF00000000ULL
1279 
1280 /* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR */
1281 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR 0x0870U
1282 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_MASKFULL 0x0000000000000001ULL
1283 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_SHIFT 0U
1284 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU
1285 #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_EN 0x00000001U
1286 
1287 /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG */
1288 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG 0x0878U
1289 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MASKFULL 0xFFFFFFF7FFFFFFBFULL
1290 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_SHIFT 36U
1291 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL
1292 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_SHIFT 32U
1293 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL
1294 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_SHIFT 12U
1295 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1296 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_SHIFT 11U
1297 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL
1298 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_EN 0x0000000000000800ULL
1299 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_SHIFT 7U
1300 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL
1301 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4KB 0x0000000000000000ULL
1302 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16KB 0x0000000000000080ULL
1303 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64KB 0x0000000000000100ULL
1304 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256KB 0x0000000000000180ULL
1305 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_1MB 0x0000000000000200ULL
1306 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4MB 0x0000000000000280ULL
1307 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16MB 0x0000000000000300ULL
1308 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64MB 0x0000000000000380ULL
1309 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256MB 0x0000000000000400ULL
1310 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_SHIFT 1U
1311 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_CLRMSK 0xFFFFFFFFFFFFFFC1ULL
1312 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_SHIFT 0U
1313 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1314 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_EN 0x0000000000000001ULL
1315 
1316 /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ */
1317 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ 0x0880U
1318 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_MASKFULL 0x000000000000003FULL
1319 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_SHIFT 1U
1320 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_CLRMSK 0xFFFFFFC1U
1321 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_SHIFT 0U
1322 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_CLRMSK 0xFFFFFFFEU
1323 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_EN 0x00000001U
1324 
1325 /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA */
1326 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA 0x0888U
1327 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MASKFULL 0xFFFFFFF7FFFFFF81ULL
1328 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_SHIFT 36U
1329 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL
1330 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_SHIFT 32U
1331 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL
1332 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_SHIFT 12U
1333 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
1334 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_SHIFT 11U
1335 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL
1336 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_EN 0x0000000000000800ULL
1337 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_SHIFT 7U
1338 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL
1339 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_SHIFT 0U
1340 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1341 #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_EN 0x0000000000000001ULL
1342 
1343 /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE */
1344 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE 0x08A0U
1345 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_MASKFULL 0x0000000000000001ULL
1346 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_SHIFT 0U
1347 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU
1348 #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_EN 0x00000001U
1349 
1350 /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS */
1351 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS 0x08A8U
1352 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_MASKFULL 0x0000000000000001ULL
1353 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_SHIFT 0U
1354 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_CLRMSK 0xFFFFFFFEU
1355 #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN 0x00000001U
1356 
1357 /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR */
1358 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR 0x08B0U
1359 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_MASKFULL 0x0000000000000001ULL
1360 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_SHIFT 0U
1361 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU
1362 #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN 0x00000001U
1363 
1364 /* Register ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE */
1365 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE 0x08B8U
1366 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_MASKFULL 0x0000000000000001ULL
1367 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_SHIFT 0U
1368 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU
1369 #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_EN 0x00000001U
1370 
1371 /* Register ROGUE_CR_MIPS_WRAPPER_NMI_EVENT */
1372 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT 0x08C0U
1373 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL
1374 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_SHIFT 0U
1375 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_CLRMSK 0xFFFFFFFEU
1376 #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_EN 0x00000001U
1377 
1378 /* Register ROGUE_CR_MIPS_DEBUG_CONFIG */
1379 #define ROGUE_CR_MIPS_DEBUG_CONFIG 0x08C8U
1380 #define ROGUE_CR_MIPS_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL
1381 #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_SHIFT 0U
1382 #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_CLRMSK 0xFFFFFFFEU
1383 #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_EN 0x00000001U
1384 
1385 /* Register ROGUE_CR_MIPS_EXCEPTION_STATUS */
1386 #define ROGUE_CR_MIPS_EXCEPTION_STATUS 0x08D0U
1387 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_MASKFULL 0x000000000000003FULL
1388 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_SHIFT 5U
1389 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_CLRMSK 0xFFFFFFDFU
1390 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_EN 0x00000020U
1391 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_SHIFT 4U
1392 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_CLRMSK 0xFFFFFFEFU
1393 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_EN 0x00000010U
1394 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_SHIFT 3U
1395 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_CLRMSK 0xFFFFFFF7U
1396 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_EN 0x00000008U
1397 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_SHIFT 2U
1398 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_CLRMSK 0xFFFFFFFBU
1399 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_EN 0x00000004U
1400 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_SHIFT 1U
1401 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_CLRMSK 0xFFFFFFFDU
1402 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_EN 0x00000002U
1403 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_SHIFT 0U
1404 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_CLRMSK 0xFFFFFFFEU
1405 #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_EN 0x00000001U
1406 
1407 /* Register ROGUE_CR_MIPS_WRAPPER_STATUS */
1408 #define ROGUE_CR_MIPS_WRAPPER_STATUS 0x08E8U
1409 #define ROGUE_CR_MIPS_WRAPPER_STATUS_MASKFULL 0x00000000000000FFULL
1410 #define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_SHIFT 0U
1411 #define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_CLRMSK 0xFFFFFF00U
1412 
1413 /* Register ROGUE_CR_XPU_BROADCAST */
1414 #define ROGUE_CR_XPU_BROADCAST 0x0890U
1415 #define ROGUE_CR_XPU_BROADCAST_MASKFULL 0x00000000000001FFULL
1416 #define ROGUE_CR_XPU_BROADCAST_MASK_SHIFT 0U
1417 #define ROGUE_CR_XPU_BROADCAST_MASK_CLRMSK 0xFFFFFE00U
1418 
1419 /* Register ROGUE_CR_META_SP_MSLVDATAX */
1420 #define ROGUE_CR_META_SP_MSLVDATAX 0x0A00U
1421 #define ROGUE_CR_META_SP_MSLVDATAX_MASKFULL 0x00000000FFFFFFFFULL
1422 #define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT 0U
1423 #define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_CLRMSK 0x00000000U
1424 
1425 /* Register ROGUE_CR_META_SP_MSLVDATAT */
1426 #define ROGUE_CR_META_SP_MSLVDATAT 0x0A08U
1427 #define ROGUE_CR_META_SP_MSLVDATAT_MASKFULL 0x00000000FFFFFFFFULL
1428 #define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT 0U
1429 #define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_CLRMSK 0x00000000U
1430 
1431 /* Register ROGUE_CR_META_SP_MSLVCTRL0 */
1432 #define ROGUE_CR_META_SP_MSLVCTRL0 0x0A10U
1433 #define ROGUE_CR_META_SP_MSLVCTRL0_MASKFULL 0x00000000FFFFFFFFULL
1434 #define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_SHIFT 2U
1435 #define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_CLRMSK 0x00000003U
1436 #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT 1U
1437 #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_CLRMSK 0xFFFFFFFDU
1438 #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_EN 0x00000002U
1439 #define ROGUE_CR_META_SP_MSLVCTRL0_RD_SHIFT 0U
1440 #define ROGUE_CR_META_SP_MSLVCTRL0_RD_CLRMSK 0xFFFFFFFEU
1441 #define ROGUE_CR_META_SP_MSLVCTRL0_RD_EN 0x00000001U
1442 
1443 /* Register ROGUE_CR_META_SP_MSLVCTRL1 */
1444 #define ROGUE_CR_META_SP_MSLVCTRL1 0x0A18U
1445 #define ROGUE_CR_META_SP_MSLVCTRL1_MASKFULL 0x00000000F7F4003FULL
1446 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT 30U
1447 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_CLRMSK 0x3FFFFFFFU
1448 #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT 29U
1449 #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_CLRMSK 0xDFFFFFFFU
1450 #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_EN 0x20000000U
1451 #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT 28U
1452 #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_CLRMSK 0xEFFFFFFFU
1453 #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_EN 0x10000000U
1454 #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT 26U
1455 #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_CLRMSK 0xFBFFFFFFU
1456 #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN 0x04000000U
1457 #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT 25U
1458 #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_CLRMSK 0xFDFFFFFFU
1459 #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_EN 0x02000000U
1460 #define ROGUE_CR_META_SP_MSLVCTRL1_READY_SHIFT 24U
1461 #define ROGUE_CR_META_SP_MSLVCTRL1_READY_CLRMSK 0xFEFFFFFFU
1462 #define ROGUE_CR_META_SP_MSLVCTRL1_READY_EN 0x01000000U
1463 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT 21U
1464 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_CLRMSK 0xFF1FFFFFU
1465 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT 20U
1466 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_CLRMSK 0xFFEFFFFFU
1467 #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_EN 0x00100000U
1468 #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT 18U
1469 #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_CLRMSK 0xFFFBFFFFU
1470 #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_EN 0x00040000U
1471 #define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_SHIFT 4U
1472 #define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_CLRMSK 0xFFFFFFCFU
1473 #define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT 2U
1474 #define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_CLRMSK 0xFFFFFFF3U
1475 #define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT 0U
1476 #define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_CLRMSK 0xFFFFFFFCU
1477 
1478 /* Register ROGUE_CR_META_SP_MSLVHANDSHKE */
1479 #define ROGUE_CR_META_SP_MSLVHANDSHKE 0x0A50U
1480 #define ROGUE_CR_META_SP_MSLVHANDSHKE_MASKFULL 0x000000000000000FULL
1481 #define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT 2U
1482 #define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_CLRMSK 0xFFFFFFF3U
1483 #define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT 0U
1484 #define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_CLRMSK 0xFFFFFFFCU
1485 
1486 /* Register ROGUE_CR_META_SP_MSLVT0KICK */
1487 #define ROGUE_CR_META_SP_MSLVT0KICK 0x0A80U
1488 #define ROGUE_CR_META_SP_MSLVT0KICK_MASKFULL 0x000000000000FFFFULL
1489 #define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT 0U
1490 #define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_CLRMSK 0xFFFF0000U
1491 
1492 /* Register ROGUE_CR_META_SP_MSLVT0KICKI */
1493 #define ROGUE_CR_META_SP_MSLVT0KICKI 0x0A88U
1494 #define ROGUE_CR_META_SP_MSLVT0KICKI_MASKFULL 0x000000000000FFFFULL
1495 #define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT 0U
1496 #define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_CLRMSK 0xFFFF0000U
1497 
1498 /* Register ROGUE_CR_META_SP_MSLVT1KICK */
1499 #define ROGUE_CR_META_SP_MSLVT1KICK 0x0A90U
1500 #define ROGUE_CR_META_SP_MSLVT1KICK_MASKFULL 0x000000000000FFFFULL
1501 #define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT 0U
1502 #define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_CLRMSK 0xFFFF0000U
1503 
1504 /* Register ROGUE_CR_META_SP_MSLVT1KICKI */
1505 #define ROGUE_CR_META_SP_MSLVT1KICKI 0x0A98U
1506 #define ROGUE_CR_META_SP_MSLVT1KICKI_MASKFULL 0x000000000000FFFFULL
1507 #define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT 0U
1508 #define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_CLRMSK 0xFFFF0000U
1509 
1510 /* Register ROGUE_CR_META_SP_MSLVT2KICK */
1511 #define ROGUE_CR_META_SP_MSLVT2KICK 0x0AA0U
1512 #define ROGUE_CR_META_SP_MSLVT2KICK_MASKFULL 0x000000000000FFFFULL
1513 #define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT 0U
1514 #define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_CLRMSK 0xFFFF0000U
1515 
1516 /* Register ROGUE_CR_META_SP_MSLVT2KICKI */
1517 #define ROGUE_CR_META_SP_MSLVT2KICKI 0x0AA8U
1518 #define ROGUE_CR_META_SP_MSLVT2KICKI_MASKFULL 0x000000000000FFFFULL
1519 #define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT 0U
1520 #define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_CLRMSK 0xFFFF0000U
1521 
1522 /* Register ROGUE_CR_META_SP_MSLVT3KICK */
1523 #define ROGUE_CR_META_SP_MSLVT3KICK 0x0AB0U
1524 #define ROGUE_CR_META_SP_MSLVT3KICK_MASKFULL 0x000000000000FFFFULL
1525 #define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT 0U
1526 #define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_CLRMSK 0xFFFF0000U
1527 
1528 /* Register ROGUE_CR_META_SP_MSLVT3KICKI */
1529 #define ROGUE_CR_META_SP_MSLVT3KICKI 0x0AB8U
1530 #define ROGUE_CR_META_SP_MSLVT3KICKI_MASKFULL 0x000000000000FFFFULL
1531 #define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT 0U
1532 #define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_CLRMSK 0xFFFF0000U
1533 
1534 /* Register ROGUE_CR_META_SP_MSLVRST */
1535 #define ROGUE_CR_META_SP_MSLVRST 0x0AC0U
1536 #define ROGUE_CR_META_SP_MSLVRST_MASKFULL 0x0000000000000001ULL
1537 #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_SHIFT 0U
1538 #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_CLRMSK 0xFFFFFFFEU
1539 #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_EN 0x00000001U
1540 
1541 /* Register ROGUE_CR_META_SP_MSLVIRQSTATUS */
1542 #define ROGUE_CR_META_SP_MSLVIRQSTATUS 0x0AC8U
1543 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_MASKFULL 0x000000000000000CULL
1544 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT 3U
1545 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_CLRMSK 0xFFFFFFF7U
1546 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_EN 0x00000008U
1547 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT 2U
1548 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK 0xFFFFFFFBU
1549 #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN 0x00000004U
1550 
1551 /* Register ROGUE_CR_META_SP_MSLVIRQENABLE */
1552 #define ROGUE_CR_META_SP_MSLVIRQENABLE 0x0AD0U
1553 #define ROGUE_CR_META_SP_MSLVIRQENABLE_MASKFULL 0x000000000000000CULL
1554 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT 3U
1555 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_CLRMSK 0xFFFFFFF7U
1556 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_EN 0x00000008U
1557 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT 2U
1558 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_CLRMSK 0xFFFFFFFBU
1559 #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_EN 0x00000004U
1560 
1561 /* Register ROGUE_CR_META_SP_MSLVIRQLEVEL */
1562 #define ROGUE_CR_META_SP_MSLVIRQLEVEL 0x0AD8U
1563 #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MASKFULL 0x0000000000000001ULL
1564 #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT 0U
1565 #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_CLRMSK 0xFFFFFFFEU
1566 #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_EN 0x00000001U
1567 
1568 /* Register ROGUE_CR_MTS_SCHEDULE */
1569 #define ROGUE_CR_MTS_SCHEDULE 0x0B00U
1570 #define ROGUE_CR_MTS_SCHEDULE_MASKFULL 0x00000000000001FFULL
1571 #define ROGUE_CR_MTS_SCHEDULE_HOST_SHIFT 8U
1572 #define ROGUE_CR_MTS_SCHEDULE_HOST_CLRMSK 0xFFFFFEFFU
1573 #define ROGUE_CR_MTS_SCHEDULE_HOST_BG_TIMER 0x00000000U
1574 #define ROGUE_CR_MTS_SCHEDULE_HOST_HOST 0x00000100U
1575 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_SHIFT 6U
1576 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_CLRMSK 0xFFFFFF3FU
1577 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT0 0x00000000U
1578 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT1 0x00000040U
1579 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT2 0x00000080U
1580 #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT3 0x000000C0U
1581 #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_SHIFT 5U
1582 #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_CLRMSK 0xFFFFFFDFU
1583 #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_BGCTX 0x00000000U
1584 #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_INTCTX 0x00000020U
1585 #define ROGUE_CR_MTS_SCHEDULE_TASK_SHIFT 4U
1586 #define ROGUE_CR_MTS_SCHEDULE_TASK_CLRMSK 0xFFFFFFEFU
1587 #define ROGUE_CR_MTS_SCHEDULE_TASK_NON_COUNTED 0x00000000U
1588 #define ROGUE_CR_MTS_SCHEDULE_TASK_COUNTED 0x00000010U
1589 #define ROGUE_CR_MTS_SCHEDULE_DM_SHIFT 0U
1590 #define ROGUE_CR_MTS_SCHEDULE_DM_CLRMSK 0xFFFFFFF0U
1591 #define ROGUE_CR_MTS_SCHEDULE_DM_DM0 0x00000000U
1592 #define ROGUE_CR_MTS_SCHEDULE_DM_DM1 0x00000001U
1593 #define ROGUE_CR_MTS_SCHEDULE_DM_DM2 0x00000002U
1594 #define ROGUE_CR_MTS_SCHEDULE_DM_DM3 0x00000003U
1595 #define ROGUE_CR_MTS_SCHEDULE_DM_DM4 0x00000004U
1596 #define ROGUE_CR_MTS_SCHEDULE_DM_DM5 0x00000005U
1597 #define ROGUE_CR_MTS_SCHEDULE_DM_DM6 0x00000006U
1598 #define ROGUE_CR_MTS_SCHEDULE_DM_DM7 0x00000007U
1599 #define ROGUE_CR_MTS_SCHEDULE_DM_DM_ALL 0x0000000FU
1600 
1601 /* Register ROGUE_CR_MTS_SCHEDULE1 */
1602 #define ROGUE_CR_MTS_SCHEDULE1 0x10B00U
1603 #define ROGUE_CR_MTS_SCHEDULE1_MASKFULL 0x00000000000001FFULL
1604 #define ROGUE_CR_MTS_SCHEDULE1_HOST_SHIFT 8U
1605 #define ROGUE_CR_MTS_SCHEDULE1_HOST_CLRMSK 0xFFFFFEFFU
1606 #define ROGUE_CR_MTS_SCHEDULE1_HOST_BG_TIMER 0x00000000U
1607 #define ROGUE_CR_MTS_SCHEDULE1_HOST_HOST 0x00000100U
1608 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_SHIFT 6U
1609 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_CLRMSK 0xFFFFFF3FU
1610 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT0 0x00000000U
1611 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT1 0x00000040U
1612 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT2 0x00000080U
1613 #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT3 0x000000C0U
1614 #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_SHIFT 5U
1615 #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_CLRMSK 0xFFFFFFDFU
1616 #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_BGCTX 0x00000000U
1617 #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_INTCTX 0x00000020U
1618 #define ROGUE_CR_MTS_SCHEDULE1_TASK_SHIFT 4U
1619 #define ROGUE_CR_MTS_SCHEDULE1_TASK_CLRMSK 0xFFFFFFEFU
1620 #define ROGUE_CR_MTS_SCHEDULE1_TASK_NON_COUNTED 0x00000000U
1621 #define ROGUE_CR_MTS_SCHEDULE1_TASK_COUNTED 0x00000010U
1622 #define ROGUE_CR_MTS_SCHEDULE1_DM_SHIFT 0U
1623 #define ROGUE_CR_MTS_SCHEDULE1_DM_CLRMSK 0xFFFFFFF0U
1624 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM0 0x00000000U
1625 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM1 0x00000001U
1626 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM2 0x00000002U
1627 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM3 0x00000003U
1628 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM4 0x00000004U
1629 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM5 0x00000005U
1630 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM6 0x00000006U
1631 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM7 0x00000007U
1632 #define ROGUE_CR_MTS_SCHEDULE1_DM_DM_ALL 0x0000000FU
1633 
1634 /* Register ROGUE_CR_MTS_SCHEDULE2 */
1635 #define ROGUE_CR_MTS_SCHEDULE2 0x20B00U
1636 #define ROGUE_CR_MTS_SCHEDULE2_MASKFULL 0x00000000000001FFULL
1637 #define ROGUE_CR_MTS_SCHEDULE2_HOST_SHIFT 8U
1638 #define ROGUE_CR_MTS_SCHEDULE2_HOST_CLRMSK 0xFFFFFEFFU
1639 #define ROGUE_CR_MTS_SCHEDULE2_HOST_BG_TIMER 0x00000000U
1640 #define ROGUE_CR_MTS_SCHEDULE2_HOST_HOST 0x00000100U
1641 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_SHIFT 6U
1642 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_CLRMSK 0xFFFFFF3FU
1643 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT0 0x00000000U
1644 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT1 0x00000040U
1645 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT2 0x00000080U
1646 #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT3 0x000000C0U
1647 #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_SHIFT 5U
1648 #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_CLRMSK 0xFFFFFFDFU
1649 #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_BGCTX 0x00000000U
1650 #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_INTCTX 0x00000020U
1651 #define ROGUE_CR_MTS_SCHEDULE2_TASK_SHIFT 4U
1652 #define ROGUE_CR_MTS_SCHEDULE2_TASK_CLRMSK 0xFFFFFFEFU
1653 #define ROGUE_CR_MTS_SCHEDULE2_TASK_NON_COUNTED 0x00000000U
1654 #define ROGUE_CR_MTS_SCHEDULE2_TASK_COUNTED 0x00000010U
1655 #define ROGUE_CR_MTS_SCHEDULE2_DM_SHIFT 0U
1656 #define ROGUE_CR_MTS_SCHEDULE2_DM_CLRMSK 0xFFFFFFF0U
1657 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM0 0x00000000U
1658 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM1 0x00000001U
1659 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM2 0x00000002U
1660 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM3 0x00000003U
1661 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM4 0x00000004U
1662 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM5 0x00000005U
1663 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM6 0x00000006U
1664 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM7 0x00000007U
1665 #define ROGUE_CR_MTS_SCHEDULE2_DM_DM_ALL 0x0000000FU
1666 
1667 /* Register ROGUE_CR_MTS_SCHEDULE3 */
1668 #define ROGUE_CR_MTS_SCHEDULE3 0x30B00U
1669 #define ROGUE_CR_MTS_SCHEDULE3_MASKFULL 0x00000000000001FFULL
1670 #define ROGUE_CR_MTS_SCHEDULE3_HOST_SHIFT 8U
1671 #define ROGUE_CR_MTS_SCHEDULE3_HOST_CLRMSK 0xFFFFFEFFU
1672 #define ROGUE_CR_MTS_SCHEDULE3_HOST_BG_TIMER 0x00000000U
1673 #define ROGUE_CR_MTS_SCHEDULE3_HOST_HOST 0x00000100U
1674 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_SHIFT 6U
1675 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_CLRMSK 0xFFFFFF3FU
1676 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT0 0x00000000U
1677 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT1 0x00000040U
1678 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT2 0x00000080U
1679 #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT3 0x000000C0U
1680 #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_SHIFT 5U
1681 #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_CLRMSK 0xFFFFFFDFU
1682 #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_BGCTX 0x00000000U
1683 #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_INTCTX 0x00000020U
1684 #define ROGUE_CR_MTS_SCHEDULE3_TASK_SHIFT 4U
1685 #define ROGUE_CR_MTS_SCHEDULE3_TASK_CLRMSK 0xFFFFFFEFU
1686 #define ROGUE_CR_MTS_SCHEDULE3_TASK_NON_COUNTED 0x00000000U
1687 #define ROGUE_CR_MTS_SCHEDULE3_TASK_COUNTED 0x00000010U
1688 #define ROGUE_CR_MTS_SCHEDULE3_DM_SHIFT 0U
1689 #define ROGUE_CR_MTS_SCHEDULE3_DM_CLRMSK 0xFFFFFFF0U
1690 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM0 0x00000000U
1691 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM1 0x00000001U
1692 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM2 0x00000002U
1693 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM3 0x00000003U
1694 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM4 0x00000004U
1695 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM5 0x00000005U
1696 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM6 0x00000006U
1697 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM7 0x00000007U
1698 #define ROGUE_CR_MTS_SCHEDULE3_DM_DM_ALL 0x0000000FU
1699 
1700 /* Register ROGUE_CR_MTS_SCHEDULE4 */
1701 #define ROGUE_CR_MTS_SCHEDULE4 0x40B00U
1702 #define ROGUE_CR_MTS_SCHEDULE4_MASKFULL 0x00000000000001FFULL
1703 #define ROGUE_CR_MTS_SCHEDULE4_HOST_SHIFT 8U
1704 #define ROGUE_CR_MTS_SCHEDULE4_HOST_CLRMSK 0xFFFFFEFFU
1705 #define ROGUE_CR_MTS_SCHEDULE4_HOST_BG_TIMER 0x00000000U
1706 #define ROGUE_CR_MTS_SCHEDULE4_HOST_HOST 0x00000100U
1707 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_SHIFT 6U
1708 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_CLRMSK 0xFFFFFF3FU
1709 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT0 0x00000000U
1710 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT1 0x00000040U
1711 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT2 0x00000080U
1712 #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT3 0x000000C0U
1713 #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_SHIFT 5U
1714 #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_CLRMSK 0xFFFFFFDFU
1715 #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_BGCTX 0x00000000U
1716 #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_INTCTX 0x00000020U
1717 #define ROGUE_CR_MTS_SCHEDULE4_TASK_SHIFT 4U
1718 #define ROGUE_CR_MTS_SCHEDULE4_TASK_CLRMSK 0xFFFFFFEFU
1719 #define ROGUE_CR_MTS_SCHEDULE4_TASK_NON_COUNTED 0x00000000U
1720 #define ROGUE_CR_MTS_SCHEDULE4_TASK_COUNTED 0x00000010U
1721 #define ROGUE_CR_MTS_SCHEDULE4_DM_SHIFT 0U
1722 #define ROGUE_CR_MTS_SCHEDULE4_DM_CLRMSK 0xFFFFFFF0U
1723 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM0 0x00000000U
1724 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM1 0x00000001U
1725 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM2 0x00000002U
1726 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM3 0x00000003U
1727 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM4 0x00000004U
1728 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM5 0x00000005U
1729 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM6 0x00000006U
1730 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM7 0x00000007U
1731 #define ROGUE_CR_MTS_SCHEDULE4_DM_DM_ALL 0x0000000FU
1732 
1733 /* Register ROGUE_CR_MTS_SCHEDULE5 */
1734 #define ROGUE_CR_MTS_SCHEDULE5 0x50B00U
1735 #define ROGUE_CR_MTS_SCHEDULE5_MASKFULL 0x00000000000001FFULL
1736 #define ROGUE_CR_MTS_SCHEDULE5_HOST_SHIFT 8U
1737 #define ROGUE_CR_MTS_SCHEDULE5_HOST_CLRMSK 0xFFFFFEFFU
1738 #define ROGUE_CR_MTS_SCHEDULE5_HOST_BG_TIMER 0x00000000U
1739 #define ROGUE_CR_MTS_SCHEDULE5_HOST_HOST 0x00000100U
1740 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_SHIFT 6U
1741 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_CLRMSK 0xFFFFFF3FU
1742 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT0 0x00000000U
1743 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT1 0x00000040U
1744 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT2 0x00000080U
1745 #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT3 0x000000C0U
1746 #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_SHIFT 5U
1747 #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_CLRMSK 0xFFFFFFDFU
1748 #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_BGCTX 0x00000000U
1749 #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_INTCTX 0x00000020U
1750 #define ROGUE_CR_MTS_SCHEDULE5_TASK_SHIFT 4U
1751 #define ROGUE_CR_MTS_SCHEDULE5_TASK_CLRMSK 0xFFFFFFEFU
1752 #define ROGUE_CR_MTS_SCHEDULE5_TASK_NON_COUNTED 0x00000000U
1753 #define ROGUE_CR_MTS_SCHEDULE5_TASK_COUNTED 0x00000010U
1754 #define ROGUE_CR_MTS_SCHEDULE5_DM_SHIFT 0U
1755 #define ROGUE_CR_MTS_SCHEDULE5_DM_CLRMSK 0xFFFFFFF0U
1756 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM0 0x00000000U
1757 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM1 0x00000001U
1758 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM2 0x00000002U
1759 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM3 0x00000003U
1760 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM4 0x00000004U
1761 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM5 0x00000005U
1762 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM6 0x00000006U
1763 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM7 0x00000007U
1764 #define ROGUE_CR_MTS_SCHEDULE5_DM_DM_ALL 0x0000000FU
1765 
1766 /* Register ROGUE_CR_MTS_SCHEDULE6 */
1767 #define ROGUE_CR_MTS_SCHEDULE6 0x60B00U
1768 #define ROGUE_CR_MTS_SCHEDULE6_MASKFULL 0x00000000000001FFULL
1769 #define ROGUE_CR_MTS_SCHEDULE6_HOST_SHIFT 8U
1770 #define ROGUE_CR_MTS_SCHEDULE6_HOST_CLRMSK 0xFFFFFEFFU
1771 #define ROGUE_CR_MTS_SCHEDULE6_HOST_BG_TIMER 0x00000000U
1772 #define ROGUE_CR_MTS_SCHEDULE6_HOST_HOST 0x00000100U
1773 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_SHIFT 6U
1774 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_CLRMSK 0xFFFFFF3FU
1775 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT0 0x00000000U
1776 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT1 0x00000040U
1777 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT2 0x00000080U
1778 #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT3 0x000000C0U
1779 #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_SHIFT 5U
1780 #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_CLRMSK 0xFFFFFFDFU
1781 #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_BGCTX 0x00000000U
1782 #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_INTCTX 0x00000020U
1783 #define ROGUE_CR_MTS_SCHEDULE6_TASK_SHIFT 4U
1784 #define ROGUE_CR_MTS_SCHEDULE6_TASK_CLRMSK 0xFFFFFFEFU
1785 #define ROGUE_CR_MTS_SCHEDULE6_TASK_NON_COUNTED 0x00000000U
1786 #define ROGUE_CR_MTS_SCHEDULE6_TASK_COUNTED 0x00000010U
1787 #define ROGUE_CR_MTS_SCHEDULE6_DM_SHIFT 0U
1788 #define ROGUE_CR_MTS_SCHEDULE6_DM_CLRMSK 0xFFFFFFF0U
1789 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM0 0x00000000U
1790 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM1 0x00000001U
1791 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM2 0x00000002U
1792 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM3 0x00000003U
1793 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM4 0x00000004U
1794 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM5 0x00000005U
1795 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM6 0x00000006U
1796 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM7 0x00000007U
1797 #define ROGUE_CR_MTS_SCHEDULE6_DM_DM_ALL 0x0000000FU
1798 
1799 /* Register ROGUE_CR_MTS_SCHEDULE7 */
1800 #define ROGUE_CR_MTS_SCHEDULE7 0x70B00U
1801 #define ROGUE_CR_MTS_SCHEDULE7_MASKFULL 0x00000000000001FFULL
1802 #define ROGUE_CR_MTS_SCHEDULE7_HOST_SHIFT 8U
1803 #define ROGUE_CR_MTS_SCHEDULE7_HOST_CLRMSK 0xFFFFFEFFU
1804 #define ROGUE_CR_MTS_SCHEDULE7_HOST_BG_TIMER 0x00000000U
1805 #define ROGUE_CR_MTS_SCHEDULE7_HOST_HOST 0x00000100U
1806 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_SHIFT 6U
1807 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_CLRMSK 0xFFFFFF3FU
1808 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT0 0x00000000U
1809 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT1 0x00000040U
1810 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT2 0x00000080U
1811 #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT3 0x000000C0U
1812 #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_SHIFT 5U
1813 #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_CLRMSK 0xFFFFFFDFU
1814 #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_BGCTX 0x00000000U
1815 #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_INTCTX 0x00000020U
1816 #define ROGUE_CR_MTS_SCHEDULE7_TASK_SHIFT 4U
1817 #define ROGUE_CR_MTS_SCHEDULE7_TASK_CLRMSK 0xFFFFFFEFU
1818 #define ROGUE_CR_MTS_SCHEDULE7_TASK_NON_COUNTED 0x00000000U
1819 #define ROGUE_CR_MTS_SCHEDULE7_TASK_COUNTED 0x00000010U
1820 #define ROGUE_CR_MTS_SCHEDULE7_DM_SHIFT 0U
1821 #define ROGUE_CR_MTS_SCHEDULE7_DM_CLRMSK 0xFFFFFFF0U
1822 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM0 0x00000000U
1823 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM1 0x00000001U
1824 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM2 0x00000002U
1825 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM3 0x00000003U
1826 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM4 0x00000004U
1827 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM5 0x00000005U
1828 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM6 0x00000006U
1829 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM7 0x00000007U
1830 #define ROGUE_CR_MTS_SCHEDULE7_DM_DM_ALL 0x0000000FU
1831 
1832 /* Register ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC */
1833 #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC 0x0B30U
1834 #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
1835 #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
1836 #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
1837 
1838 /* Register ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC */
1839 #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC 0x0B38U
1840 #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
1841 #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
1842 #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
1843 
1844 /* Register ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC */
1845 #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC 0x0B40U
1846 #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
1847 #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
1848 #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
1849 
1850 /* Register ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC */
1851 #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC 0x0B48U
1852 #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
1853 #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
1854 #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
1855 
1856 /* Register ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG */
1857 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG 0x0B50U
1858 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__MASKFULL 0x000FF0FFFFFFF701ULL
1859 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_MASKFULL 0x0000FFFFFFFFF001ULL
1860 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT 44U
1861 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK 0xFFFF0FFFFFFFFFFFULL
1862 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_SHIFT 44U
1863 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_CLRMSK 0xFFF00FFFFFFFFFFFULL
1864 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT 40U
1865 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_CLRMSK 0xFFFFF0FFFFFFFFFFULL
1866 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_SHIFT 12U
1867 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
1868 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_SHIFT 9U
1869 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_CLRMSK 0xFFFFFFFFFFFFF9FFULL
1870 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT 8U
1871 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_CLRMSK 0xFFFFFFFFFFFFFEFFULL
1872 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_EN 0x0000000000000100ULL
1873 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT 0U
1874 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
1875 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META 0x0000000000000000ULL
1876 #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_MTS 0x0000000000000001ULL
1877 
1878 /* Register ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE */
1879 #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE 0x0B58U
1880 #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1881 #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1882 #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1883 
1884 /* Register ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE */
1885 #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE 0x0B60U
1886 #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1887 #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1888 #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1889 
1890 /* Register ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE */
1891 #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE 0x0B68U
1892 #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1893 #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1894 #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1895 
1896 /* Register ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE */
1897 #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE 0x0B70U
1898 #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1899 #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1900 #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1901 
1902 /* Register ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE */
1903 #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE 0x0B78U
1904 #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1905 #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1906 #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1907 
1908 /* Register ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE */
1909 #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE 0x0B80U
1910 #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
1911 #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
1912 #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
1913 
1914 /* Register ROGUE_CR_MTS_INTCTX */
1915 #define ROGUE_CR_MTS_INTCTX 0x0B98U
1916 #define ROGUE_CR_MTS_INTCTX_MASKFULL 0x000000003FFFFFFFULL
1917 #define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT 22U
1918 #define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_CLRMSK 0xC03FFFFFU
1919 #define ROGUE_CR_MTS_INTCTX_DM_PTR_SHIFT 18U
1920 #define ROGUE_CR_MTS_INTCTX_DM_PTR_CLRMSK 0xFFC3FFFFU
1921 #define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_SHIFT 16U
1922 #define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_CLRMSK 0xFFFCFFFFU
1923 #define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT 8U
1924 #define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_CLRMSK 0xFFFF00FFU
1925 #define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT 0U
1926 #define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_CLRMSK 0xFFFFFF00U
1927 
1928 /* Register ROGUE_CR_MTS_BGCTX */
1929 #define ROGUE_CR_MTS_BGCTX 0x0BA0U
1930 #define ROGUE_CR_MTS_BGCTX_MASKFULL 0x0000000000003FFFULL
1931 #define ROGUE_CR_MTS_BGCTX_DM_PTR_SHIFT 10U
1932 #define ROGUE_CR_MTS_BGCTX_DM_PTR_CLRMSK 0xFFFFC3FFU
1933 #define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_SHIFT 8U
1934 #define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_CLRMSK 0xFFFFFCFFU
1935 #define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT 0U
1936 #define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_CLRMSK 0xFFFFFF00U
1937 
1938 /* Register ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE */
1939 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE 0x0BA8U
1940 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_MASKFULL 0xFFFFFFFFFFFFFFFFULL
1941 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT 56U
1942 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_CLRMSK 0x00FFFFFFFFFFFFFFULL
1943 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT 48U
1944 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_CLRMSK 0xFF00FFFFFFFFFFFFULL
1945 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT 40U
1946 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_CLRMSK 0xFFFF00FFFFFFFFFFULL
1947 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT 32U
1948 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_CLRMSK 0xFFFFFF00FFFFFFFFULL
1949 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT 24U
1950 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_CLRMSK 0xFFFFFFFF00FFFFFFULL
1951 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT 16U
1952 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_CLRMSK 0xFFFFFFFFFF00FFFFULL
1953 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT 8U
1954 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_CLRMSK 0xFFFFFFFFFFFF00FFULL
1955 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT 0U
1956 #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_CLRMSK 0xFFFFFFFFFFFFFF00ULL
1957 
1958 /* Register ROGUE_CR_MTS_GPU_INT_STATUS */
1959 #define ROGUE_CR_MTS_GPU_INT_STATUS 0x0BB0U
1960 #define ROGUE_CR_MTS_GPU_INT_STATUS_MASKFULL 0x00000000FFFFFFFFULL
1961 #define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT 0U
1962 #define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_CLRMSK 0x00000000U
1963 
1964 /* Register ROGUE_CR_MTS_SCHEDULE_ENABLE */
1965 #define ROGUE_CR_MTS_SCHEDULE_ENABLE 0x0BC8U
1966 #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASKFULL 0x00000000000000FFULL
1967 #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT 0U
1968 #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_CLRMSK 0xFFFFFF00U
1969 
1970 /* Register ROGUE_CR_IRQ_OS0_EVENT_STATUS */
1971 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS 0x0BD8U
1972 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
1973 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT 0U
1974 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
1975 #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN 0x00000001U
1976 
1977 /* Register ROGUE_CR_IRQ_OS0_EVENT_CLEAR */
1978 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR 0x0BE8U
1979 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
1980 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT 0U
1981 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
1982 #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN 0x00000001U
1983 
1984 /* Register ROGUE_CR_IRQ_OS1_EVENT_STATUS */
1985 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS 0x10BD8U
1986 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
1987 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT 0U
1988 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
1989 #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_EN 0x00000001U
1990 
1991 /* Register ROGUE_CR_IRQ_OS1_EVENT_CLEAR */
1992 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR 0x10BE8U
1993 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
1994 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT 0U
1995 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
1996 #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_EN 0x00000001U
1997 
1998 /* Register ROGUE_CR_IRQ_OS2_EVENT_STATUS */
1999 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS 0x20BD8U
2000 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2001 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT 0U
2002 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2003 #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_EN 0x00000001U
2004 
2005 /* Register ROGUE_CR_IRQ_OS2_EVENT_CLEAR */
2006 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR 0x20BE8U
2007 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2008 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT 0U
2009 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2010 #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_EN 0x00000001U
2011 
2012 /* Register ROGUE_CR_IRQ_OS3_EVENT_STATUS */
2013 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS 0x30BD8U
2014 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2015 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT 0U
2016 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2017 #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_EN 0x00000001U
2018 
2019 /* Register ROGUE_CR_IRQ_OS3_EVENT_CLEAR */
2020 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR 0x30BE8U
2021 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2022 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT 0U
2023 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2024 #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_EN 0x00000001U
2025 
2026 /* Register ROGUE_CR_IRQ_OS4_EVENT_STATUS */
2027 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS 0x40BD8U
2028 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2029 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT 0U
2030 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2031 #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_EN 0x00000001U
2032 
2033 /* Register ROGUE_CR_IRQ_OS4_EVENT_CLEAR */
2034 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR 0x40BE8U
2035 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2036 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT 0U
2037 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2038 #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_EN 0x00000001U
2039 
2040 /* Register ROGUE_CR_IRQ_OS5_EVENT_STATUS */
2041 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS 0x50BD8U
2042 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2043 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT 0U
2044 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2045 #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_EN 0x00000001U
2046 
2047 /* Register ROGUE_CR_IRQ_OS5_EVENT_CLEAR */
2048 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR 0x50BE8U
2049 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2050 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT 0U
2051 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2052 #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_EN 0x00000001U
2053 
2054 /* Register ROGUE_CR_IRQ_OS6_EVENT_STATUS */
2055 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS 0x60BD8U
2056 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2057 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT 0U
2058 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2059 #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_EN 0x00000001U
2060 
2061 /* Register ROGUE_CR_IRQ_OS6_EVENT_CLEAR */
2062 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR 0x60BE8U
2063 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2064 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT 0U
2065 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2066 #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_EN 0x00000001U
2067 
2068 /* Register ROGUE_CR_IRQ_OS7_EVENT_STATUS */
2069 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS 0x70BD8U
2070 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
2071 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT 0U
2072 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
2073 #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_EN 0x00000001U
2074 
2075 /* Register ROGUE_CR_IRQ_OS7_EVENT_CLEAR */
2076 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR 0x70BE8U
2077 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
2078 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT 0U
2079 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
2080 #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_EN 0x00000001U
2081 
2082 /* Register ROGUE_CR_META_BOOT */
2083 #define ROGUE_CR_META_BOOT 0x0BF8U
2084 #define ROGUE_CR_META_BOOT_MASKFULL 0x0000000000000001ULL
2085 #define ROGUE_CR_META_BOOT_MODE_SHIFT 0U
2086 #define ROGUE_CR_META_BOOT_MODE_CLRMSK 0xFFFFFFFEU
2087 #define ROGUE_CR_META_BOOT_MODE_EN 0x00000001U
2088 
2089 /* Register ROGUE_CR_GARTEN_SLC */
2090 #define ROGUE_CR_GARTEN_SLC 0x0BB8U
2091 #define ROGUE_CR_GARTEN_SLC_MASKFULL 0x0000000000000001ULL
2092 #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT 0U
2093 #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_CLRMSK 0xFFFFFFFEU
2094 #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_EN 0x00000001U
2095 
2096 /* Register ROGUE_CR_PPP */
2097 #define ROGUE_CR_PPP 0x0CD0U
2098 #define ROGUE_CR_PPP_MASKFULL 0x00000000FFFFFFFFULL
2099 #define ROGUE_CR_PPP_CHECKSUM_SHIFT 0U
2100 #define ROGUE_CR_PPP_CHECKSUM_CLRMSK 0x00000000U
2101 
2102 #define ROGUE_CR_ISP_RENDER_DIR_TYPE_MASK 0x00000003U
2103 /* Top-left to bottom-right */
2104 #define ROGUE_CR_ISP_RENDER_DIR_TYPE_TL2BR 0x00000000U
2105 /* Top-right to bottom-left */
2106 #define ROGUE_CR_ISP_RENDER_DIR_TYPE_TR2BL 0x00000001U
2107 /* Bottom-left to top-right */
2108 #define ROGUE_CR_ISP_RENDER_DIR_TYPE_BL2TR 0x00000002U
2109 /* Bottom-right to top-left */
2110 #define ROGUE_CR_ISP_RENDER_DIR_TYPE_BR2TL 0x00000003U
2111 
2112 #define ROGUE_CR_ISP_RENDER_MODE_TYPE_MASK 0x00000003U
2113 /* Normal render */
2114 #define ROGUE_CR_ISP_RENDER_MODE_TYPE_NORM 0x00000000U
2115 /* Fast 2D render */
2116 #define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_2D 0x00000002U
2117 /* Fast scale render */
2118 #define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_SCALE 0x00000003U
2119 
2120 /* Register ROGUE_CR_ISP_RENDER */
2121 #define ROGUE_CR_ISP_RENDER 0x0F08U
2122 #define ROGUE_CR_ISP_RENDER_MASKFULL 0x00000000000001FFULL
2123 #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_SHIFT 8U
2124 #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_CLRMSK 0xFFFFFEFFU
2125 #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_EN 0x00000100U
2126 #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT 7U
2127 #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_CLRMSK 0xFFFFFF7FU
2128 #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_EN 0x00000080U
2129 #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT 6U
2130 #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_CLRMSK 0xFFFFFFBFU
2131 #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_EN 0x00000040U
2132 #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_SHIFT 5U
2133 #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_CLRMSK 0xFFFFFFDFU
2134 #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_EN 0x00000020U
2135 #define ROGUE_CR_ISP_RENDER_RESUME_SHIFT 4U
2136 #define ROGUE_CR_ISP_RENDER_RESUME_CLRMSK 0xFFFFFFEFU
2137 #define ROGUE_CR_ISP_RENDER_RESUME_EN 0x00000010U
2138 #define ROGUE_CR_ISP_RENDER_DIR_SHIFT 2U
2139 #define ROGUE_CR_ISP_RENDER_DIR_CLRMSK 0xFFFFFFF3U
2140 #define ROGUE_CR_ISP_RENDER_DIR_TL2BR 0x00000000U
2141 #define ROGUE_CR_ISP_RENDER_DIR_TR2BL 0x00000004U
2142 #define ROGUE_CR_ISP_RENDER_DIR_BL2TR 0x00000008U
2143 #define ROGUE_CR_ISP_RENDER_DIR_BR2TL 0x0000000CU
2144 #define ROGUE_CR_ISP_RENDER_MODE_SHIFT 0U
2145 #define ROGUE_CR_ISP_RENDER_MODE_CLRMSK 0xFFFFFFFCU
2146 #define ROGUE_CR_ISP_RENDER_MODE_NORM 0x00000000U
2147 #define ROGUE_CR_ISP_RENDER_MODE_FAST_2D 0x00000002U
2148 #define ROGUE_CR_ISP_RENDER_MODE_FAST_SCALE 0x00000003U
2149 
2150 /* Register ROGUE_CR_ISP_CTL */
2151 #define ROGUE_CR_ISP_CTL 0x0F38U
2152 #define ROGUE_CR_ISP_CTL_MASKFULL 0x00000000FFFFF3FFULL
2153 #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_SHIFT 31U
2154 #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_CLRMSK 0x7FFFFFFFU
2155 #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_EN 0x80000000U
2156 #define ROGUE_CR_ISP_CTL_LINE_STYLE_SHIFT 30U
2157 #define ROGUE_CR_ISP_CTL_LINE_STYLE_CLRMSK 0xBFFFFFFFU
2158 #define ROGUE_CR_ISP_CTL_LINE_STYLE_EN 0x40000000U
2159 #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_SHIFT 29U
2160 #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_CLRMSK 0xDFFFFFFFU
2161 #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_EN 0x20000000U
2162 #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_SHIFT 28U
2163 #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_CLRMSK 0xEFFFFFFFU
2164 #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_EN 0x10000000U
2165 #define ROGUE_CR_ISP_CTL_PAIR_TILES_SHIFT 27U
2166 #define ROGUE_CR_ISP_CTL_PAIR_TILES_CLRMSK 0xF7FFFFFFU
2167 #define ROGUE_CR_ISP_CTL_PAIR_TILES_EN 0x08000000U
2168 #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_SHIFT 26U
2169 #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_CLRMSK 0xFBFFFFFFU
2170 #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_EN 0x04000000U
2171 #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_SHIFT 25U
2172 #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_CLRMSK 0xFDFFFFFFU
2173 #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_EN 0x02000000U
2174 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_SHIFT 23U
2175 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_CLRMSK 0xFE7FFFFFU
2176 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX9 0x00000000U
2177 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX10 0x00800000U
2178 #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_OGL 0x01000000U
2179 #define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_SHIFT 21U
2180 #define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_CLRMSK 0xFF9FFFFFU
2181 #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_SHIFT 20U
2182 #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_CLRMSK 0xFFEFFFFFU
2183 #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_EN 0x00100000U
2184 #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT 19U
2185 #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_CLRMSK 0xFFF7FFFFU
2186 #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_EN 0x00080000U
2187 #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_SHIFT 18U
2188 #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_CLRMSK 0xFFFBFFFFU
2189 #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_EN 0x00040000U
2190 #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_SHIFT 17U
2191 #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_CLRMSK 0xFFFDFFFFU
2192 #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_EN 0x00020000U
2193 #define ROGUE_CR_ISP_CTL_SAMPLE_POS_SHIFT 16U
2194 #define ROGUE_CR_ISP_CTL_SAMPLE_POS_CLRMSK 0xFFFEFFFFU
2195 #define ROGUE_CR_ISP_CTL_SAMPLE_POS_EN 0x00010000U
2196 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_SHIFT 12U
2197 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_CLRMSK 0xFFFF0FFFU
2198 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ONE 0x00000000U
2199 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWO 0x00001000U
2200 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THREE 0x00002000U
2201 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOUR 0x00003000U
2202 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIVE 0x00004000U
2203 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIX 0x00005000U
2204 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SEVEN 0x00006000U
2205 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_EIGHT 0x00007000U
2206 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_NINE 0x00008000U
2207 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TEN 0x00009000U
2208 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ELEVEN 0x0000A000U
2209 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWELVE 0x0000B000U
2210 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THIRTEEN 0x0000C000U
2211 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOURTEEN 0x0000D000U
2212 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIFTEEN 0x0000E000U
2213 #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIXTEEN 0x0000F000U
2214 #define ROGUE_CR_ISP_CTL_VALID_ID_SHIFT 4U
2215 #define ROGUE_CR_ISP_CTL_VALID_ID_CLRMSK 0xFFFFFC0FU
2216 #define ROGUE_CR_ISP_CTL_UPASS_START_SHIFT 0U
2217 #define ROGUE_CR_ISP_CTL_UPASS_START_CLRMSK 0xFFFFFFF0U
2218 
2219 /* Register ROGUE_CR_ISP_STATUS */
2220 #define ROGUE_CR_ISP_STATUS 0x1038U
2221 #define ROGUE_CR_ISP_STATUS_MASKFULL 0x0000000000000007ULL
2222 #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_SHIFT 2U
2223 #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_CLRMSK 0xFFFFFFFBU
2224 #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_EN 0x00000004U
2225 #define ROGUE_CR_ISP_STATUS_ACTIVE_SHIFT 1U
2226 #define ROGUE_CR_ISP_STATUS_ACTIVE_CLRMSK 0xFFFFFFFDU
2227 #define ROGUE_CR_ISP_STATUS_ACTIVE_EN 0x00000002U
2228 #define ROGUE_CR_ISP_STATUS_EOR_SHIFT 0U
2229 #define ROGUE_CR_ISP_STATUS_EOR_CLRMSK 0xFFFFFFFEU
2230 #define ROGUE_CR_ISP_STATUS_EOR_EN 0x00000001U
2231 
2232 /* Register group: ROGUE_CR_ISP_XTP_RESUME, with 64 repeats */
2233 #define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U
2234 /* Register ROGUE_CR_ISP_XTP_RESUME0 */
2235 #define ROGUE_CR_ISP_XTP_RESUME0 0x3A00U
2236 #define ROGUE_CR_ISP_XTP_RESUME0_MASKFULL 0x00000000003FF3FFULL
2237 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U
2238 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_CLRMSK 0xFFC00FFFU
2239 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U
2240 #define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_CLRMSK 0xFFFFFC00U
2241 
2242 /* Register group: ROGUE_CR_ISP_XTP_STORE, with 32 repeats */
2243 #define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U
2244 /* Register ROGUE_CR_ISP_XTP_STORE0 */
2245 #define ROGUE_CR_ISP_XTP_STORE0 0x3C00U
2246 #define ROGUE_CR_ISP_XTP_STORE0_MASKFULL 0x000000007F3FF3FFULL
2247 #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U
2248 #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_CLRMSK 0xBFFFFFFFU
2249 #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_EN 0x40000000U
2250 #define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U
2251 #define ROGUE_CR_ISP_XTP_STORE0_EOR_CLRMSK 0xDFFFFFFFU
2252 #define ROGUE_CR_ISP_XTP_STORE0_EOR_EN 0x20000000U
2253 #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U
2254 #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_CLRMSK 0xEFFFFFFFU
2255 #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_EN 0x10000000U
2256 #define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U
2257 #define ROGUE_CR_ISP_XTP_STORE0_MT_CLRMSK 0xF0FFFFFFU
2258 #define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U
2259 #define ROGUE_CR_ISP_XTP_STORE0_TILE_X_CLRMSK 0xFFC00FFFU
2260 #define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U
2261 #define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_CLRMSK 0xFFFFFC00U
2262 
2263 /* Register group: ROGUE_CR_BIF_CAT_BASE, with 8 repeats */
2264 #define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U
2265 /* Register ROGUE_CR_BIF_CAT_BASE0 */
2266 #define ROGUE_CR_BIF_CAT_BASE0 0x1200U
2267 #define ROGUE_CR_BIF_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
2268 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U
2269 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2270 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U
2271 #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U
2272 
2273 /* Register ROGUE_CR_BIF_CAT_BASE1 */
2274 #define ROGUE_CR_BIF_CAT_BASE1 0x1208U
2275 #define ROGUE_CR_BIF_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
2276 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U
2277 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2278 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U
2279 #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U
2280 
2281 /* Register ROGUE_CR_BIF_CAT_BASE2 */
2282 #define ROGUE_CR_BIF_CAT_BASE2 0x1210U
2283 #define ROGUE_CR_BIF_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
2284 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U
2285 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2286 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U
2287 #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U
2288 
2289 /* Register ROGUE_CR_BIF_CAT_BASE3 */
2290 #define ROGUE_CR_BIF_CAT_BASE3 0x1218U
2291 #define ROGUE_CR_BIF_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
2292 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U
2293 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2294 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U
2295 #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U
2296 
2297 /* Register ROGUE_CR_BIF_CAT_BASE4 */
2298 #define ROGUE_CR_BIF_CAT_BASE4 0x1220U
2299 #define ROGUE_CR_BIF_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
2300 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U
2301 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2302 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U
2303 #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U
2304 
2305 /* Register ROGUE_CR_BIF_CAT_BASE5 */
2306 #define ROGUE_CR_BIF_CAT_BASE5 0x1228U
2307 #define ROGUE_CR_BIF_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
2308 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U
2309 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2310 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U
2311 #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U
2312 
2313 /* Register ROGUE_CR_BIF_CAT_BASE6 */
2314 #define ROGUE_CR_BIF_CAT_BASE6 0x1230U
2315 #define ROGUE_CR_BIF_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
2316 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U
2317 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2318 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U
2319 #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U
2320 
2321 /* Register ROGUE_CR_BIF_CAT_BASE7 */
2322 #define ROGUE_CR_BIF_CAT_BASE7 0x1238U
2323 #define ROGUE_CR_BIF_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
2324 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U
2325 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2326 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U
2327 #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U
2328 
2329 /* Register ROGUE_CR_BIF_CAT_BASE_INDEX */
2330 #define ROGUE_CR_BIF_CAT_BASE_INDEX 0x1240U
2331 #define ROGUE_CR_BIF_CAT_BASE_INDEX_MASKFULL 0x00070707073F0707ULL
2332 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_SHIFT 48U
2333 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_CLRMSK 0xFFF8FFFFFFFFFFFFULL
2334 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_SHIFT 40U
2335 #define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_CLRMSK 0xFFFFF8FFFFFFFFFFULL
2336 #define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_SHIFT 32U
2337 #define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_CLRMSK 0xFFFFFFF8FFFFFFFFULL
2338 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_SHIFT 24U
2339 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_CLRMSK 0xFFFFFFFFF8FFFFFFULL
2340 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_SHIFT 19U
2341 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_CLRMSK 0xFFFFFFFFFFC7FFFFULL
2342 #define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_SHIFT 16U
2343 #define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_CLRMSK 0xFFFFFFFFFFF8FFFFULL
2344 #define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_SHIFT 8U
2345 #define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_CLRMSK 0xFFFFFFFFFFFFF8FFULL
2346 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_SHIFT 0U
2347 #define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_CLRMSK 0xFFFFFFFFFFFFFFF8ULL
2348 
2349 /* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE0 */
2350 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0 0x1248U
2351 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_MASKFULL 0x0FFFFFFFFFFFF003ULL
2352 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_SHIFT 40U
2353 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2354 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_SHIFT 12U
2355 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2356 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_SHIFT 1U
2357 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2358 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_EN 0x0000000000000002ULL
2359 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_SHIFT 0U
2360 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2361 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_EN 0x0000000000000001ULL
2362 
2363 /* Register ROGUE_CR_BIF_PM_CAT_BASE_TE0 */
2364 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0 0x1250U
2365 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_MASKFULL 0x0FFFFFFFFFFFF003ULL
2366 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_SHIFT 40U
2367 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2368 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_SHIFT 12U
2369 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2370 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_SHIFT 1U
2371 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2372 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_EN 0x0000000000000002ULL
2373 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_SHIFT 0U
2374 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2375 #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_EN 0x0000000000000001ULL
2376 
2377 /* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 */
2378 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 0x1260U
2379 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_MASKFULL 0x0FFFFFFFFFFFF003ULL
2380 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT 40U
2381 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2382 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_SHIFT 12U
2383 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2384 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_SHIFT 1U
2385 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2386 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_EN 0x0000000000000002ULL
2387 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_SHIFT 0U
2388 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2389 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_EN 0x0000000000000001ULL
2390 
2391 /* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE1 */
2392 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1 0x1268U
2393 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_MASKFULL 0x0FFFFFFFFFFFF003ULL
2394 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_SHIFT 40U
2395 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2396 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_SHIFT 12U
2397 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2398 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_SHIFT 1U
2399 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2400 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_EN 0x0000000000000002ULL
2401 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_SHIFT 0U
2402 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2403 #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_EN 0x0000000000000001ULL
2404 
2405 /* Register ROGUE_CR_BIF_PM_CAT_BASE_TE1 */
2406 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1 0x1270U
2407 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_MASKFULL 0x0FFFFFFFFFFFF003ULL
2408 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_SHIFT 40U
2409 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2410 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_SHIFT 12U
2411 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2412 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_SHIFT 1U
2413 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2414 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_EN 0x0000000000000002ULL
2415 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_SHIFT 0U
2416 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2417 #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_EN 0x0000000000000001ULL
2418 
2419 /* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 */
2420 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 0x1280U
2421 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_MASKFULL 0x0FFFFFFFFFFFF003ULL
2422 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT 40U
2423 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
2424 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_SHIFT 12U
2425 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
2426 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_SHIFT 1U
2427 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
2428 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_EN 0x0000000000000002ULL
2429 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_SHIFT 0U
2430 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
2431 #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_EN 0x0000000000000001ULL
2432 
2433 /* Register ROGUE_CR_BIF_MMU_ENTRY_STATUS */
2434 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS 0x1288U
2435 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_MASKFULL 0x000000FFFFFFF0F3ULL
2436 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_SHIFT 12U
2437 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_CLRMSK 0xFFFFFF0000000FFFULL
2438 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_SHIFT 4U
2439 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_CLRMSK 0xFFFFFFFFFFFFFF0FULL
2440 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_SHIFT 0U
2441 #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_CLRMSK 0xFFFFFFFFFFFFFFFCULL
2442 
2443 /* Register ROGUE_CR_BIF_MMU_ENTRY */
2444 #define ROGUE_CR_BIF_MMU_ENTRY 0x1290U
2445 #define ROGUE_CR_BIF_MMU_ENTRY_MASKFULL 0x0000000000000003ULL
2446 #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_SHIFT 1U
2447 #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_CLRMSK 0xFFFFFFFDU
2448 #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_EN 0x00000002U
2449 #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_SHIFT 0U
2450 #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_CLRMSK 0xFFFFFFFEU
2451 #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_EN 0x00000001U
2452 
2453 /* Register ROGUE_CR_BIF_CTRL_INVAL */
2454 #define ROGUE_CR_BIF_CTRL_INVAL 0x12A0U
2455 #define ROGUE_CR_BIF_CTRL_INVAL_MASKFULL 0x000000000000000FULL
2456 #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_SHIFT 3U
2457 #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_CLRMSK 0xFFFFFFF7U
2458 #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_EN 0x00000008U
2459 #define ROGUE_CR_BIF_CTRL_INVAL_PC_SHIFT 2U
2460 #define ROGUE_CR_BIF_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU
2461 #define ROGUE_CR_BIF_CTRL_INVAL_PC_EN 0x00000004U
2462 #define ROGUE_CR_BIF_CTRL_INVAL_PD_SHIFT 1U
2463 #define ROGUE_CR_BIF_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU
2464 #define ROGUE_CR_BIF_CTRL_INVAL_PD_EN 0x00000002U
2465 #define ROGUE_CR_BIF_CTRL_INVAL_PT_SHIFT 0U
2466 #define ROGUE_CR_BIF_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU
2467 #define ROGUE_CR_BIF_CTRL_INVAL_PT_EN 0x00000001U
2468 
2469 /* Register ROGUE_CR_BIF_CTRL */
2470 #define ROGUE_CR_BIF_CTRL 0x12A8U
2471 #define ROGUE_CR_BIF_CTRL__XE_MEM__MASKFULL 0x000000000000033FULL
2472 #define ROGUE_CR_BIF_CTRL_MASKFULL 0x00000000000000FFULL
2473 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_SHIFT 9U
2474 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_CLRMSK 0xFFFFFDFFU
2475 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_EN 0x00000200U
2476 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_SHIFT 8U
2477 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_CLRMSK 0xFFFFFEFFU
2478 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_EN 0x00000100U
2479 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_SHIFT 7U
2480 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_CLRMSK 0xFFFFFF7FU
2481 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_EN 0x00000080U
2482 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_SHIFT 6U
2483 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_CLRMSK 0xFFFFFFBFU
2484 #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_EN 0x00000040U
2485 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_SHIFT 5U
2486 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_CLRMSK 0xFFFFFFDFU
2487 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_EN 0x00000020U
2488 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_SHIFT 4U
2489 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_CLRMSK 0xFFFFFFEFU
2490 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_EN 0x00000010U
2491 #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_SHIFT 3U
2492 #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_CLRMSK 0xFFFFFFF7U
2493 #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_EN 0x00000008U
2494 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_SHIFT 2U
2495 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_CLRMSK 0xFFFFFFFBU
2496 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_EN 0x00000004U
2497 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_SHIFT 1U
2498 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_CLRMSK 0xFFFFFFFDU
2499 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_EN 0x00000002U
2500 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_SHIFT 0U
2501 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_CLRMSK 0xFFFFFFFEU
2502 #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_EN 0x00000001U
2503 
2504 /* Register ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS */
2505 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS 0x12B0U
2506 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL
2507 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
2508 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
2509 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2510 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
2511 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
2512 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
2513 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
2514 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
2515 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U
2516 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2517 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
2518 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
2519 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
2520 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
2521 #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U
2522 
2523 /* Register ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS */
2524 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS 0x12B8U
2525 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__MASKFULL 0x001FFFFFFFFFFFF0ULL
2526 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
2527 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_SHIFT 52U
2528 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL
2529 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_EN 0x0010000000000000ULL
2530 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
2531 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
2532 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL
2533 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_SHIFT 46U
2534 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL
2535 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
2536 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
2537 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
2538 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
2539 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_SHIFT 40U
2540 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL
2541 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
2542 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
2543 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2544 #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2545 
2546 /* Register ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS */
2547 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS 0x12C0U
2548 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_MASKFULL 0x000000000000F775ULL
2549 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_SHIFT 12U
2550 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
2551 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2552 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
2553 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_SHIFT 5U
2554 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
2555 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_SHIFT 4U
2556 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
2557 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_EN 0x00000010U
2558 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2559 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
2560 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
2561 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_SHIFT 0U
2562 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
2563 #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_EN 0x00000001U
2564 
2565 /* Register ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS */
2566 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS 0x12C8U
2567 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
2568 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_SHIFT 50U
2569 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
2570 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_EN 0x0004000000000000ULL
2571 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_SHIFT 44U
2572 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
2573 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_SHIFT 40U
2574 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
2575 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_SHIFT 4U
2576 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
2577 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2578 #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2579 
2580 /* Register ROGUE_CR_BIF_MMU_STATUS */
2581 #define ROGUE_CR_BIF_MMU_STATUS 0x12D0U
2582 #define ROGUE_CR_BIF_MMU_STATUS__XE_MEM__MASKFULL 0x000000001FFFFFF7ULL
2583 #define ROGUE_CR_BIF_MMU_STATUS_MASKFULL 0x000000001FFFFFF7ULL
2584 #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_SHIFT 28U
2585 #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_CLRMSK 0xEFFFFFFFU
2586 #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_EN 0x10000000U
2587 #define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
2588 #define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
2589 #define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
2590 #define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
2591 #define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
2592 #define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
2593 #define ROGUE_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
2594 #define ROGUE_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
2595 #define ROGUE_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U
2596 #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
2597 #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
2598 #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U
2599 #define ROGUE_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
2600 #define ROGUE_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
2601 #define ROGUE_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U
2602 
2603 /* Register group: ROGUE_CR_BIF_TILING_CFG, with 8 repeats */
2604 #define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U
2605 /* Register ROGUE_CR_BIF_TILING_CFG0 */
2606 #define ROGUE_CR_BIF_TILING_CFG0 0x12D8U
2607 #define ROGUE_CR_BIF_TILING_CFG0_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2608 #define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U
2609 #define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2610 #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U
2611 #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2612 #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_EN 0x1000000000000000ULL
2613 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U
2614 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2615 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U
2616 #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U
2617 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U
2618 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2619 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U
2620 #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U
2621 
2622 /* Register ROGUE_CR_BIF_TILING_CFG1 */
2623 #define ROGUE_CR_BIF_TILING_CFG1 0x12E0U
2624 #define ROGUE_CR_BIF_TILING_CFG1_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2625 #define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U
2626 #define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2627 #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U
2628 #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2629 #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_EN 0x1000000000000000ULL
2630 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U
2631 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2632 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U
2633 #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U
2634 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U
2635 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2636 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U
2637 #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U
2638 
2639 /* Register ROGUE_CR_BIF_TILING_CFG2 */
2640 #define ROGUE_CR_BIF_TILING_CFG2 0x12E8U
2641 #define ROGUE_CR_BIF_TILING_CFG2_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2642 #define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U
2643 #define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2644 #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U
2645 #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2646 #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_EN 0x1000000000000000ULL
2647 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U
2648 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2649 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U
2650 #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U
2651 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U
2652 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2653 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U
2654 #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U
2655 
2656 /* Register ROGUE_CR_BIF_TILING_CFG3 */
2657 #define ROGUE_CR_BIF_TILING_CFG3 0x12F0U
2658 #define ROGUE_CR_BIF_TILING_CFG3_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2659 #define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U
2660 #define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2661 #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U
2662 #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2663 #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_EN 0x1000000000000000ULL
2664 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U
2665 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2666 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U
2667 #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U
2668 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U
2669 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2670 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U
2671 #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U
2672 
2673 /* Register ROGUE_CR_BIF_TILING_CFG4 */
2674 #define ROGUE_CR_BIF_TILING_CFG4 0x12F8U
2675 #define ROGUE_CR_BIF_TILING_CFG4_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2676 #define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U
2677 #define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2678 #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U
2679 #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2680 #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_EN 0x1000000000000000ULL
2681 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U
2682 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2683 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U
2684 #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U
2685 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U
2686 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2687 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U
2688 #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U
2689 
2690 /* Register ROGUE_CR_BIF_TILING_CFG5 */
2691 #define ROGUE_CR_BIF_TILING_CFG5 0x1300U
2692 #define ROGUE_CR_BIF_TILING_CFG5_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2693 #define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U
2694 #define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2695 #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U
2696 #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2697 #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_EN 0x1000000000000000ULL
2698 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U
2699 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2700 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U
2701 #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U
2702 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U
2703 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2704 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U
2705 #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U
2706 
2707 /* Register ROGUE_CR_BIF_TILING_CFG6 */
2708 #define ROGUE_CR_BIF_TILING_CFG6 0x1308U
2709 #define ROGUE_CR_BIF_TILING_CFG6_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2710 #define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U
2711 #define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2712 #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U
2713 #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2714 #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_EN 0x1000000000000000ULL
2715 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U
2716 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2717 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U
2718 #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U
2719 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U
2720 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2721 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U
2722 #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U
2723 
2724 /* Register ROGUE_CR_BIF_TILING_CFG7 */
2725 #define ROGUE_CR_BIF_TILING_CFG7 0x1310U
2726 #define ROGUE_CR_BIF_TILING_CFG7_MASKFULL 0xFFFFFFFF0FFFFFFFULL
2727 #define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U
2728 #define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
2729 #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U
2730 #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
2731 #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_EN 0x1000000000000000ULL
2732 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U
2733 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
2734 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U
2735 #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U
2736 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U
2737 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
2738 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U
2739 #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U
2740 
2741 /* Register ROGUE_CR_BIF_READS_EXT_STATUS */
2742 #define ROGUE_CR_BIF_READS_EXT_STATUS 0x1320U
2743 #define ROGUE_CR_BIF_READS_EXT_STATUS_MASKFULL 0x000000000FFFFFFFULL
2744 #define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_SHIFT 16U
2745 #define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_CLRMSK 0xF000FFFFU
2746 #define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_SHIFT 0U
2747 #define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_CLRMSK 0xFFFF0000U
2748 
2749 /* Register ROGUE_CR_BIF_READS_INT_STATUS */
2750 #define ROGUE_CR_BIF_READS_INT_STATUS 0x1328U
2751 #define ROGUE_CR_BIF_READS_INT_STATUS_MASKFULL 0x0000000007FFFFFFULL
2752 #define ROGUE_CR_BIF_READS_INT_STATUS_MMU_SHIFT 16U
2753 #define ROGUE_CR_BIF_READS_INT_STATUS_MMU_CLRMSK 0xF800FFFFU
2754 #define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_SHIFT 0U
2755 #define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_CLRMSK 0xFFFF0000U
2756 
2757 /* Register ROGUE_CR_BIFPM_READS_INT_STATUS */
2758 #define ROGUE_CR_BIFPM_READS_INT_STATUS 0x1330U
2759 #define ROGUE_CR_BIFPM_READS_INT_STATUS_MASKFULL 0x000000000000FFFFULL
2760 #define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_SHIFT 0U
2761 #define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_CLRMSK 0xFFFF0000U
2762 
2763 /* Register ROGUE_CR_BIFPM_READS_EXT_STATUS */
2764 #define ROGUE_CR_BIFPM_READS_EXT_STATUS 0x1338U
2765 #define ROGUE_CR_BIFPM_READS_EXT_STATUS_MASKFULL 0x000000000000FFFFULL
2766 #define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_SHIFT 0U
2767 #define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_CLRMSK 0xFFFF0000U
2768 
2769 /* Register ROGUE_CR_BIFPM_STATUS_MMU */
2770 #define ROGUE_CR_BIFPM_STATUS_MMU 0x1350U
2771 #define ROGUE_CR_BIFPM_STATUS_MMU_MASKFULL 0x00000000000000FFULL
2772 #define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_SHIFT 0U
2773 #define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U
2774 
2775 /* Register ROGUE_CR_BIF_STATUS_MMU */
2776 #define ROGUE_CR_BIF_STATUS_MMU 0x1358U
2777 #define ROGUE_CR_BIF_STATUS_MMU_MASKFULL 0x00000000000000FFULL
2778 #define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_SHIFT 0U
2779 #define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U
2780 
2781 /* Register ROGUE_CR_BIF_FAULT_READ */
2782 #define ROGUE_CR_BIF_FAULT_READ 0x13E0U
2783 #define ROGUE_CR_BIF_FAULT_READ_MASKFULL 0x000000FFFFFFFFF0ULL
2784 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_SHIFT 4U
2785 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
2786 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSHIFT 4U
2787 #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSIZE 16U
2788 
2789 /* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS */
2790 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS 0x1430U
2791 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL
2792 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
2793 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
2794 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
2795 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
2796 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
2797 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
2798 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
2799 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
2800 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U
2801 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
2802 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
2803 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
2804 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
2805 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
2806 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U
2807 
2808 /* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS */
2809 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS 0x1438U
2810 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
2811 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
2812 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
2813 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL
2814 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
2815 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
2816 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
2817 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
2818 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
2819 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
2820 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
2821 #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
2822 
2823 /* Register ROGUE_CR_MCU_FENCE */
2824 #define ROGUE_CR_MCU_FENCE 0x1740U
2825 #define ROGUE_CR_MCU_FENCE_MASKFULL 0x000007FFFFFFFFE0ULL
2826 #define ROGUE_CR_MCU_FENCE_DM_SHIFT 40U
2827 #define ROGUE_CR_MCU_FENCE_DM_CLRMSK 0xFFFFF8FFFFFFFFFFULL
2828 #define ROGUE_CR_MCU_FENCE_DM_VERTEX 0x0000000000000000ULL
2829 #define ROGUE_CR_MCU_FENCE_DM_PIXEL 0x0000010000000000ULL
2830 #define ROGUE_CR_MCU_FENCE_DM_COMPUTE 0x0000020000000000ULL
2831 #define ROGUE_CR_MCU_FENCE_DM_RAY_VERTEX 0x0000030000000000ULL
2832 #define ROGUE_CR_MCU_FENCE_DM_RAY 0x0000040000000000ULL
2833 #define ROGUE_CR_MCU_FENCE_DM_FASTRENDER 0x0000050000000000ULL
2834 #define ROGUE_CR_MCU_FENCE_ADDR_SHIFT 5U
2835 #define ROGUE_CR_MCU_FENCE_ADDR_CLRMSK 0xFFFFFF000000001FULL
2836 #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSHIFT 5U
2837 #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U
2838 
2839 /* Register group: ROGUE_CR_SCRATCH, with 16 repeats */
2840 #define ROGUE_CR_SCRATCH_REPEATCOUNT 16U
2841 /* Register ROGUE_CR_SCRATCH0 */
2842 #define ROGUE_CR_SCRATCH0 0x1A00U
2843 #define ROGUE_CR_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
2844 #define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U
2845 #define ROGUE_CR_SCRATCH0_DATA_CLRMSK 0x00000000U
2846 
2847 /* Register ROGUE_CR_SCRATCH1 */
2848 #define ROGUE_CR_SCRATCH1 0x1A08U
2849 #define ROGUE_CR_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
2850 #define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U
2851 #define ROGUE_CR_SCRATCH1_DATA_CLRMSK 0x00000000U
2852 
2853 /* Register ROGUE_CR_SCRATCH2 */
2854 #define ROGUE_CR_SCRATCH2 0x1A10U
2855 #define ROGUE_CR_SCRATCH2_MASKFULL 0x00000000FFFFFFFFULL
2856 #define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U
2857 #define ROGUE_CR_SCRATCH2_DATA_CLRMSK 0x00000000U
2858 
2859 /* Register ROGUE_CR_SCRATCH3 */
2860 #define ROGUE_CR_SCRATCH3 0x1A18U
2861 #define ROGUE_CR_SCRATCH3_MASKFULL 0x00000000FFFFFFFFULL
2862 #define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U
2863 #define ROGUE_CR_SCRATCH3_DATA_CLRMSK 0x00000000U
2864 
2865 /* Register ROGUE_CR_SCRATCH4 */
2866 #define ROGUE_CR_SCRATCH4 0x1A20U
2867 #define ROGUE_CR_SCRATCH4_MASKFULL 0x00000000FFFFFFFFULL
2868 #define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U
2869 #define ROGUE_CR_SCRATCH4_DATA_CLRMSK 0x00000000U
2870 
2871 /* Register ROGUE_CR_SCRATCH5 */
2872 #define ROGUE_CR_SCRATCH5 0x1A28U
2873 #define ROGUE_CR_SCRATCH5_MASKFULL 0x00000000FFFFFFFFULL
2874 #define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U
2875 #define ROGUE_CR_SCRATCH5_DATA_CLRMSK 0x00000000U
2876 
2877 /* Register ROGUE_CR_SCRATCH6 */
2878 #define ROGUE_CR_SCRATCH6 0x1A30U
2879 #define ROGUE_CR_SCRATCH6_MASKFULL 0x00000000FFFFFFFFULL
2880 #define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U
2881 #define ROGUE_CR_SCRATCH6_DATA_CLRMSK 0x00000000U
2882 
2883 /* Register ROGUE_CR_SCRATCH7 */
2884 #define ROGUE_CR_SCRATCH7 0x1A38U
2885 #define ROGUE_CR_SCRATCH7_MASKFULL 0x00000000FFFFFFFFULL
2886 #define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U
2887 #define ROGUE_CR_SCRATCH7_DATA_CLRMSK 0x00000000U
2888 
2889 /* Register ROGUE_CR_SCRATCH8 */
2890 #define ROGUE_CR_SCRATCH8 0x1A40U
2891 #define ROGUE_CR_SCRATCH8_MASKFULL 0x00000000FFFFFFFFULL
2892 #define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U
2893 #define ROGUE_CR_SCRATCH8_DATA_CLRMSK 0x00000000U
2894 
2895 /* Register ROGUE_CR_SCRATCH9 */
2896 #define ROGUE_CR_SCRATCH9 0x1A48U
2897 #define ROGUE_CR_SCRATCH9_MASKFULL 0x00000000FFFFFFFFULL
2898 #define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U
2899 #define ROGUE_CR_SCRATCH9_DATA_CLRMSK 0x00000000U
2900 
2901 /* Register ROGUE_CR_SCRATCH10 */
2902 #define ROGUE_CR_SCRATCH10 0x1A50U
2903 #define ROGUE_CR_SCRATCH10_MASKFULL 0x00000000FFFFFFFFULL
2904 #define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U
2905 #define ROGUE_CR_SCRATCH10_DATA_CLRMSK 0x00000000U
2906 
2907 /* Register ROGUE_CR_SCRATCH11 */
2908 #define ROGUE_CR_SCRATCH11 0x1A58U
2909 #define ROGUE_CR_SCRATCH11_MASKFULL 0x00000000FFFFFFFFULL
2910 #define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U
2911 #define ROGUE_CR_SCRATCH11_DATA_CLRMSK 0x00000000U
2912 
2913 /* Register ROGUE_CR_SCRATCH12 */
2914 #define ROGUE_CR_SCRATCH12 0x1A60U
2915 #define ROGUE_CR_SCRATCH12_MASKFULL 0x00000000FFFFFFFFULL
2916 #define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U
2917 #define ROGUE_CR_SCRATCH12_DATA_CLRMSK 0x00000000U
2918 
2919 /* Register ROGUE_CR_SCRATCH13 */
2920 #define ROGUE_CR_SCRATCH13 0x1A68U
2921 #define ROGUE_CR_SCRATCH13_MASKFULL 0x00000000FFFFFFFFULL
2922 #define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U
2923 #define ROGUE_CR_SCRATCH13_DATA_CLRMSK 0x00000000U
2924 
2925 /* Register ROGUE_CR_SCRATCH14 */
2926 #define ROGUE_CR_SCRATCH14 0x1A70U
2927 #define ROGUE_CR_SCRATCH14_MASKFULL 0x00000000FFFFFFFFULL
2928 #define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U
2929 #define ROGUE_CR_SCRATCH14_DATA_CLRMSK 0x00000000U
2930 
2931 /* Register ROGUE_CR_SCRATCH15 */
2932 #define ROGUE_CR_SCRATCH15 0x1A78U
2933 #define ROGUE_CR_SCRATCH15_MASKFULL 0x00000000FFFFFFFFULL
2934 #define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U
2935 #define ROGUE_CR_SCRATCH15_DATA_CLRMSK 0x00000000U
2936 
2937 /* Register group: ROGUE_CR_OS0_SCRATCH, with 2 repeats */
2938 #define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U
2939 /* Register ROGUE_CR_OS0_SCRATCH0 */
2940 #define ROGUE_CR_OS0_SCRATCH0 0x1A80U
2941 #define ROGUE_CR_OS0_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
2942 #define ROGUE_CR_OS0_SCRATCH0_DATA_SHIFT 0U
2943 #define ROGUE_CR_OS0_SCRATCH0_DATA_CLRMSK 0x00000000U
2944 
2945 /* Register ROGUE_CR_OS0_SCRATCH1 */
2946 #define ROGUE_CR_OS0_SCRATCH1 0x1A88U
2947 #define ROGUE_CR_OS0_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
2948 #define ROGUE_CR_OS0_SCRATCH1_DATA_SHIFT 0U
2949 #define ROGUE_CR_OS0_SCRATCH1_DATA_CLRMSK 0x00000000U
2950 
2951 /* Register ROGUE_CR_OS0_SCRATCH2 */
2952 #define ROGUE_CR_OS0_SCRATCH2 0x1A90U
2953 #define ROGUE_CR_OS0_SCRATCH2_MASKFULL 0x00000000000000FFULL
2954 #define ROGUE_CR_OS0_SCRATCH2_DATA_SHIFT 0U
2955 #define ROGUE_CR_OS0_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
2956 
2957 /* Register ROGUE_CR_OS0_SCRATCH3 */
2958 #define ROGUE_CR_OS0_SCRATCH3 0x1A98U
2959 #define ROGUE_CR_OS0_SCRATCH3_MASKFULL 0x00000000000000FFULL
2960 #define ROGUE_CR_OS0_SCRATCH3_DATA_SHIFT 0U
2961 #define ROGUE_CR_OS0_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
2962 
2963 /* Register group: ROGUE_CR_OS1_SCRATCH, with 2 repeats */
2964 #define ROGUE_CR_OS1_SCRATCH_REPEATCOUNT 2U
2965 /* Register ROGUE_CR_OS1_SCRATCH0 */
2966 #define ROGUE_CR_OS1_SCRATCH0 0x11A80U
2967 #define ROGUE_CR_OS1_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
2968 #define ROGUE_CR_OS1_SCRATCH0_DATA_SHIFT 0U
2969 #define ROGUE_CR_OS1_SCRATCH0_DATA_CLRMSK 0x00000000U
2970 
2971 /* Register ROGUE_CR_OS1_SCRATCH1 */
2972 #define ROGUE_CR_OS1_SCRATCH1 0x11A88U
2973 #define ROGUE_CR_OS1_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
2974 #define ROGUE_CR_OS1_SCRATCH1_DATA_SHIFT 0U
2975 #define ROGUE_CR_OS1_SCRATCH1_DATA_CLRMSK 0x00000000U
2976 
2977 /* Register ROGUE_CR_OS1_SCRATCH2 */
2978 #define ROGUE_CR_OS1_SCRATCH2 0x11A90U
2979 #define ROGUE_CR_OS1_SCRATCH2_MASKFULL 0x00000000000000FFULL
2980 #define ROGUE_CR_OS1_SCRATCH2_DATA_SHIFT 0U
2981 #define ROGUE_CR_OS1_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
2982 
2983 /* Register ROGUE_CR_OS1_SCRATCH3 */
2984 #define ROGUE_CR_OS1_SCRATCH3 0x11A98U
2985 #define ROGUE_CR_OS1_SCRATCH3_MASKFULL 0x00000000000000FFULL
2986 #define ROGUE_CR_OS1_SCRATCH3_DATA_SHIFT 0U
2987 #define ROGUE_CR_OS1_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
2988 
2989 /* Register group: ROGUE_CR_OS2_SCRATCH, with 2 repeats */
2990 #define ROGUE_CR_OS2_SCRATCH_REPEATCOUNT 2U
2991 /* Register ROGUE_CR_OS2_SCRATCH0 */
2992 #define ROGUE_CR_OS2_SCRATCH0 0x21A80U
2993 #define ROGUE_CR_OS2_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
2994 #define ROGUE_CR_OS2_SCRATCH0_DATA_SHIFT 0U
2995 #define ROGUE_CR_OS2_SCRATCH0_DATA_CLRMSK 0x00000000U
2996 
2997 /* Register ROGUE_CR_OS2_SCRATCH1 */
2998 #define ROGUE_CR_OS2_SCRATCH1 0x21A88U
2999 #define ROGUE_CR_OS2_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3000 #define ROGUE_CR_OS2_SCRATCH1_DATA_SHIFT 0U
3001 #define ROGUE_CR_OS2_SCRATCH1_DATA_CLRMSK 0x00000000U
3002 
3003 /* Register ROGUE_CR_OS2_SCRATCH2 */
3004 #define ROGUE_CR_OS2_SCRATCH2 0x21A90U
3005 #define ROGUE_CR_OS2_SCRATCH2_MASKFULL 0x00000000000000FFULL
3006 #define ROGUE_CR_OS2_SCRATCH2_DATA_SHIFT 0U
3007 #define ROGUE_CR_OS2_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3008 
3009 /* Register ROGUE_CR_OS2_SCRATCH3 */
3010 #define ROGUE_CR_OS2_SCRATCH3 0x21A98U
3011 #define ROGUE_CR_OS2_SCRATCH3_MASKFULL 0x00000000000000FFULL
3012 #define ROGUE_CR_OS2_SCRATCH3_DATA_SHIFT 0U
3013 #define ROGUE_CR_OS2_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3014 
3015 /* Register group: ROGUE_CR_OS3_SCRATCH, with 2 repeats */
3016 #define ROGUE_CR_OS3_SCRATCH_REPEATCOUNT 2U
3017 /* Register ROGUE_CR_OS3_SCRATCH0 */
3018 #define ROGUE_CR_OS3_SCRATCH0 0x31A80U
3019 #define ROGUE_CR_OS3_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
3020 #define ROGUE_CR_OS3_SCRATCH0_DATA_SHIFT 0U
3021 #define ROGUE_CR_OS3_SCRATCH0_DATA_CLRMSK 0x00000000U
3022 
3023 /* Register ROGUE_CR_OS3_SCRATCH1 */
3024 #define ROGUE_CR_OS3_SCRATCH1 0x31A88U
3025 #define ROGUE_CR_OS3_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3026 #define ROGUE_CR_OS3_SCRATCH1_DATA_SHIFT 0U
3027 #define ROGUE_CR_OS3_SCRATCH1_DATA_CLRMSK 0x00000000U
3028 
3029 /* Register ROGUE_CR_OS3_SCRATCH2 */
3030 #define ROGUE_CR_OS3_SCRATCH2 0x31A90U
3031 #define ROGUE_CR_OS3_SCRATCH2_MASKFULL 0x00000000000000FFULL
3032 #define ROGUE_CR_OS3_SCRATCH2_DATA_SHIFT 0U
3033 #define ROGUE_CR_OS3_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3034 
3035 /* Register ROGUE_CR_OS3_SCRATCH3 */
3036 #define ROGUE_CR_OS3_SCRATCH3 0x31A98U
3037 #define ROGUE_CR_OS3_SCRATCH3_MASKFULL 0x00000000000000FFULL
3038 #define ROGUE_CR_OS3_SCRATCH3_DATA_SHIFT 0U
3039 #define ROGUE_CR_OS3_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3040 
3041 /* Register group: ROGUE_CR_OS4_SCRATCH, with 2 repeats */
3042 #define ROGUE_CR_OS4_SCRATCH_REPEATCOUNT 2U
3043 /* Register ROGUE_CR_OS4_SCRATCH0 */
3044 #define ROGUE_CR_OS4_SCRATCH0 0x41A80U
3045 #define ROGUE_CR_OS4_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
3046 #define ROGUE_CR_OS4_SCRATCH0_DATA_SHIFT 0U
3047 #define ROGUE_CR_OS4_SCRATCH0_DATA_CLRMSK 0x00000000U
3048 
3049 /* Register ROGUE_CR_OS4_SCRATCH1 */
3050 #define ROGUE_CR_OS4_SCRATCH1 0x41A88U
3051 #define ROGUE_CR_OS4_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3052 #define ROGUE_CR_OS4_SCRATCH1_DATA_SHIFT 0U
3053 #define ROGUE_CR_OS4_SCRATCH1_DATA_CLRMSK 0x00000000U
3054 
3055 /* Register ROGUE_CR_OS4_SCRATCH2 */
3056 #define ROGUE_CR_OS4_SCRATCH2 0x41A90U
3057 #define ROGUE_CR_OS4_SCRATCH2_MASKFULL 0x00000000000000FFULL
3058 #define ROGUE_CR_OS4_SCRATCH2_DATA_SHIFT 0U
3059 #define ROGUE_CR_OS4_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3060 
3061 /* Register ROGUE_CR_OS4_SCRATCH3 */
3062 #define ROGUE_CR_OS4_SCRATCH3 0x41A98U
3063 #define ROGUE_CR_OS4_SCRATCH3_MASKFULL 0x00000000000000FFULL
3064 #define ROGUE_CR_OS4_SCRATCH3_DATA_SHIFT 0U
3065 #define ROGUE_CR_OS4_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3066 
3067 /* Register group: ROGUE_CR_OS5_SCRATCH, with 2 repeats */
3068 #define ROGUE_CR_OS5_SCRATCH_REPEATCOUNT 2U
3069 /* Register ROGUE_CR_OS5_SCRATCH0 */
3070 #define ROGUE_CR_OS5_SCRATCH0 0x51A80U
3071 #define ROGUE_CR_OS5_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
3072 #define ROGUE_CR_OS5_SCRATCH0_DATA_SHIFT 0U
3073 #define ROGUE_CR_OS5_SCRATCH0_DATA_CLRMSK 0x00000000U
3074 
3075 /* Register ROGUE_CR_OS5_SCRATCH1 */
3076 #define ROGUE_CR_OS5_SCRATCH1 0x51A88U
3077 #define ROGUE_CR_OS5_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3078 #define ROGUE_CR_OS5_SCRATCH1_DATA_SHIFT 0U
3079 #define ROGUE_CR_OS5_SCRATCH1_DATA_CLRMSK 0x00000000U
3080 
3081 /* Register ROGUE_CR_OS5_SCRATCH2 */
3082 #define ROGUE_CR_OS5_SCRATCH2 0x51A90U
3083 #define ROGUE_CR_OS5_SCRATCH2_MASKFULL 0x00000000000000FFULL
3084 #define ROGUE_CR_OS5_SCRATCH2_DATA_SHIFT 0U
3085 #define ROGUE_CR_OS5_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3086 
3087 /* Register ROGUE_CR_OS5_SCRATCH3 */
3088 #define ROGUE_CR_OS5_SCRATCH3 0x51A98U
3089 #define ROGUE_CR_OS5_SCRATCH3_MASKFULL 0x00000000000000FFULL
3090 #define ROGUE_CR_OS5_SCRATCH3_DATA_SHIFT 0U
3091 #define ROGUE_CR_OS5_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3092 
3093 /* Register group: ROGUE_CR_OS6_SCRATCH, with 2 repeats */
3094 #define ROGUE_CR_OS6_SCRATCH_REPEATCOUNT 2U
3095 /* Register ROGUE_CR_OS6_SCRATCH0 */
3096 #define ROGUE_CR_OS6_SCRATCH0 0x61A80U
3097 #define ROGUE_CR_OS6_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
3098 #define ROGUE_CR_OS6_SCRATCH0_DATA_SHIFT 0U
3099 #define ROGUE_CR_OS6_SCRATCH0_DATA_CLRMSK 0x00000000U
3100 
3101 /* Register ROGUE_CR_OS6_SCRATCH1 */
3102 #define ROGUE_CR_OS6_SCRATCH1 0x61A88U
3103 #define ROGUE_CR_OS6_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3104 #define ROGUE_CR_OS6_SCRATCH1_DATA_SHIFT 0U
3105 #define ROGUE_CR_OS6_SCRATCH1_DATA_CLRMSK 0x00000000U
3106 
3107 /* Register ROGUE_CR_OS6_SCRATCH2 */
3108 #define ROGUE_CR_OS6_SCRATCH2 0x61A90U
3109 #define ROGUE_CR_OS6_SCRATCH2_MASKFULL 0x00000000000000FFULL
3110 #define ROGUE_CR_OS6_SCRATCH2_DATA_SHIFT 0U
3111 #define ROGUE_CR_OS6_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3112 
3113 /* Register ROGUE_CR_OS6_SCRATCH3 */
3114 #define ROGUE_CR_OS6_SCRATCH3 0x61A98U
3115 #define ROGUE_CR_OS6_SCRATCH3_MASKFULL 0x00000000000000FFULL
3116 #define ROGUE_CR_OS6_SCRATCH3_DATA_SHIFT 0U
3117 #define ROGUE_CR_OS6_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3118 
3119 /* Register group: ROGUE_CR_OS7_SCRATCH, with 2 repeats */
3120 #define ROGUE_CR_OS7_SCRATCH_REPEATCOUNT 2U
3121 /* Register ROGUE_CR_OS7_SCRATCH0 */
3122 #define ROGUE_CR_OS7_SCRATCH0 0x71A80U
3123 #define ROGUE_CR_OS7_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
3124 #define ROGUE_CR_OS7_SCRATCH0_DATA_SHIFT 0U
3125 #define ROGUE_CR_OS7_SCRATCH0_DATA_CLRMSK 0x00000000U
3126 
3127 /* Register ROGUE_CR_OS7_SCRATCH1 */
3128 #define ROGUE_CR_OS7_SCRATCH1 0x71A88U
3129 #define ROGUE_CR_OS7_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
3130 #define ROGUE_CR_OS7_SCRATCH1_DATA_SHIFT 0U
3131 #define ROGUE_CR_OS7_SCRATCH1_DATA_CLRMSK 0x00000000U
3132 
3133 /* Register ROGUE_CR_OS7_SCRATCH2 */
3134 #define ROGUE_CR_OS7_SCRATCH2 0x71A90U
3135 #define ROGUE_CR_OS7_SCRATCH2_MASKFULL 0x00000000000000FFULL
3136 #define ROGUE_CR_OS7_SCRATCH2_DATA_SHIFT 0U
3137 #define ROGUE_CR_OS7_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
3138 
3139 /* Register ROGUE_CR_OS7_SCRATCH3 */
3140 #define ROGUE_CR_OS7_SCRATCH3 0x71A98U
3141 #define ROGUE_CR_OS7_SCRATCH3_MASKFULL 0x00000000000000FFULL
3142 #define ROGUE_CR_OS7_SCRATCH3_DATA_SHIFT 0U
3143 #define ROGUE_CR_OS7_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
3144 
3145 /* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR */
3146 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR 0x2700U
3147 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MASKFULL 0x000000000000FFFFULL
3148 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_SHIFT 0U
3149 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_CLRMSK 0xFFFF0000U
3150 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSHIFT 4U
3151 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSIZE 16U
3152 
3153 /* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN */
3154 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN 0x2708U
3155 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_MASKFULL 0x000000FFFFFFFFF0ULL
3156 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_SHIFT 4U
3157 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_CLRMSK 0xFFFFFF000000000FULL
3158 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSHIFT 4U
3159 #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U
3160 
3161 /* Register group: ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats */
3162 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U
3163 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 */
3164 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 0x3000U
3165 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL 0x7FFFF7FFFFFFF000ULL
3166 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U
3167 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3168 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_EN 0x4000000000000000ULL
3169 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U
3170 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3171 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN 0x2000000000000000ULL
3172 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U
3173 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3174 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN 0x1000000000000000ULL
3175 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U
3176 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3177 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U
3178 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3179 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U
3180 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3181 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U
3182 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U
3183 
3184 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 */
3185 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 0x3008U
3186 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL 0x7FFFF7FFFFFFF000ULL
3187 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U
3188 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3189 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_EN 0x4000000000000000ULL
3190 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U
3191 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3192 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN 0x2000000000000000ULL
3193 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U
3194 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3195 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN 0x1000000000000000ULL
3196 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U
3197 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3198 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U
3199 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3200 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U
3201 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3202 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U
3203 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U
3204 
3205 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 */
3206 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 0x3010U
3207 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL 0x7FFFF7FFFFFFF000ULL
3208 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U
3209 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3210 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_EN 0x4000000000000000ULL
3211 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U
3212 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3213 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN 0x2000000000000000ULL
3214 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U
3215 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3216 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN 0x1000000000000000ULL
3217 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U
3218 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3219 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U
3220 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3221 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U
3222 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3223 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U
3224 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U
3225 
3226 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 */
3227 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 0x3018U
3228 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL 0x7FFFF7FFFFFFF000ULL
3229 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U
3230 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3231 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_EN 0x4000000000000000ULL
3232 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U
3233 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3234 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN 0x2000000000000000ULL
3235 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U
3236 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3237 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN 0x1000000000000000ULL
3238 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U
3239 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3240 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U
3241 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3242 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U
3243 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3244 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U
3245 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U
3246 
3247 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 */
3248 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 0x3020U
3249 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL 0x7FFFF7FFFFFFF000ULL
3250 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U
3251 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3252 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_EN 0x4000000000000000ULL
3253 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U
3254 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3255 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN 0x2000000000000000ULL
3256 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U
3257 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3258 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN 0x1000000000000000ULL
3259 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U
3260 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3261 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U
3262 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3263 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U
3264 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3265 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U
3266 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U
3267 
3268 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 */
3269 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 0x3028U
3270 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL 0x7FFFF7FFFFFFF000ULL
3271 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U
3272 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3273 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_EN 0x4000000000000000ULL
3274 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U
3275 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3276 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN 0x2000000000000000ULL
3277 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U
3278 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3279 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN 0x1000000000000000ULL
3280 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U
3281 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3282 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U
3283 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3284 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U
3285 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3286 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U
3287 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U
3288 
3289 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 */
3290 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 0x3030U
3291 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL 0x7FFFF7FFFFFFF000ULL
3292 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U
3293 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3294 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_EN 0x4000000000000000ULL
3295 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U
3296 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3297 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN 0x2000000000000000ULL
3298 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U
3299 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3300 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN 0x1000000000000000ULL
3301 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U
3302 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3303 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U
3304 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3305 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U
3306 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3307 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U
3308 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U
3309 
3310 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 */
3311 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 0x3038U
3312 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL 0x7FFFF7FFFFFFF000ULL
3313 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U
3314 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3315 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_EN 0x4000000000000000ULL
3316 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U
3317 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3318 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN 0x2000000000000000ULL
3319 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U
3320 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3321 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN 0x1000000000000000ULL
3322 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U
3323 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3324 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U
3325 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3326 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U
3327 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3328 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U
3329 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U
3330 
3331 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 */
3332 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 0x3040U
3333 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL 0x7FFFF7FFFFFFF000ULL
3334 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U
3335 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3336 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_EN 0x4000000000000000ULL
3337 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U
3338 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3339 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN 0x2000000000000000ULL
3340 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U
3341 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3342 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN 0x1000000000000000ULL
3343 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U
3344 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3345 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U
3346 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3347 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U
3348 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3349 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U
3350 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U
3351 
3352 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 */
3353 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 0x3048U
3354 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL 0x7FFFF7FFFFFFF000ULL
3355 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U
3356 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3357 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_EN 0x4000000000000000ULL
3358 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U
3359 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3360 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN 0x2000000000000000ULL
3361 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U
3362 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3363 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN 0x1000000000000000ULL
3364 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U
3365 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3366 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U
3367 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3368 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U
3369 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3370 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U
3371 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U
3372 
3373 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 */
3374 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 0x3050U
3375 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL 0x7FFFF7FFFFFFF000ULL
3376 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U
3377 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3378 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_EN 0x4000000000000000ULL
3379 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U
3380 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3381 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN 0x2000000000000000ULL
3382 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U
3383 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3384 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN 0x1000000000000000ULL
3385 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U
3386 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3387 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U
3388 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3389 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U
3390 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3391 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U
3392 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U
3393 
3394 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 */
3395 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 0x3058U
3396 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL 0x7FFFF7FFFFFFF000ULL
3397 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U
3398 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3399 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_EN 0x4000000000000000ULL
3400 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U
3401 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3402 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN 0x2000000000000000ULL
3403 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U
3404 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3405 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN 0x1000000000000000ULL
3406 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U
3407 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3408 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U
3409 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3410 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U
3411 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3412 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U
3413 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U
3414 
3415 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 */
3416 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 0x3060U
3417 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL 0x7FFFF7FFFFFFF000ULL
3418 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U
3419 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3420 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_EN 0x4000000000000000ULL
3421 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U
3422 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3423 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN 0x2000000000000000ULL
3424 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U
3425 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3426 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN 0x1000000000000000ULL
3427 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U
3428 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3429 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U
3430 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3431 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U
3432 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3433 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U
3434 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U
3435 
3436 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 */
3437 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 0x3068U
3438 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL 0x7FFFF7FFFFFFF000ULL
3439 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U
3440 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3441 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_EN 0x4000000000000000ULL
3442 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U
3443 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3444 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN 0x2000000000000000ULL
3445 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U
3446 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3447 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN 0x1000000000000000ULL
3448 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U
3449 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3450 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U
3451 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3452 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U
3453 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3454 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U
3455 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U
3456 
3457 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 */
3458 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 0x3070U
3459 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL 0x7FFFF7FFFFFFF000ULL
3460 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U
3461 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3462 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_EN 0x4000000000000000ULL
3463 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U
3464 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3465 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN 0x2000000000000000ULL
3466 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U
3467 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3468 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN 0x1000000000000000ULL
3469 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U
3470 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3471 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U
3472 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3473 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U
3474 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3475 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U
3476 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U
3477 
3478 /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 */
3479 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 0x3078U
3480 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL 0x7FFFF7FFFFFFF000ULL
3481 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U
3482 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
3483 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_EN 0x4000000000000000ULL
3484 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U
3485 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
3486 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN 0x2000000000000000ULL
3487 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U
3488 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
3489 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN 0x1000000000000000ULL
3490 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U
3491 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
3492 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U
3493 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
3494 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U
3495 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
3496 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U
3497 #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U
3498 
3499 /* Register ROGUE_CR_FWCORE_BOOT */
3500 #define ROGUE_CR_FWCORE_BOOT 0x3090U
3501 #define ROGUE_CR_FWCORE_BOOT_MASKFULL 0x0000000000000001ULL
3502 #define ROGUE_CR_FWCORE_BOOT_ENABLE_SHIFT 0U
3503 #define ROGUE_CR_FWCORE_BOOT_ENABLE_CLRMSK 0xFFFFFFFEU
3504 #define ROGUE_CR_FWCORE_BOOT_ENABLE_EN 0x00000001U
3505 
3506 /* Register ROGUE_CR_FWCORE_RESET_ADDR */
3507 #define ROGUE_CR_FWCORE_RESET_ADDR 0x3098U
3508 #define ROGUE_CR_FWCORE_RESET_ADDR_MASKFULL 0x00000000FFFFFFFEULL
3509 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_SHIFT 1U
3510 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_CLRMSK 0x00000001U
3511 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSHIFT 1U
3512 #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSIZE 2U
3513 
3514 /* Register ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR */
3515 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR 0x30A0U
3516 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_MASKFULL 0x00000000FFFFFFFEULL
3517 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_SHIFT 1U
3518 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_CLRMSK 0x00000001U
3519 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSHIFT 1U
3520 #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSIZE 2U
3521 
3522 /* Register ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT */
3523 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT 0x30A8U
3524 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL
3525 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT 0U
3526 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_CLRMSK 0xFFFFFFFEU
3527 #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_EN 0x00000001U
3528 
3529 /* Register ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS */
3530 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS 0x30B0U
3531 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_MASKFULL 0x000000000000F771ULL
3532 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_SHIFT 12U
3533 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
3534 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_SHIFT 8U
3535 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
3536 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_SHIFT 5U
3537 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
3538 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_SHIFT 4U
3539 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
3540 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_EN 0x00000010U
3541 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_SHIFT 0U
3542 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
3543 #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_EN 0x00000001U
3544 
3545 /* Register ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS */
3546 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS 0x30B8U
3547 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_MASKFULL 0x001FFFFFFFFFFFF0ULL
3548 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_SHIFT 52U
3549 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL
3550 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_EN 0x0010000000000000ULL
3551 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_SHIFT 46U
3552 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL
3553 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_SHIFT 40U
3554 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL
3555 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_SHIFT 4U
3556 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
3557 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
3558 #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
3559 
3560 /* Register ROGUE_CR_FWCORE_MEM_CTRL_INVAL */
3561 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL 0x30C0U
3562 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_MASKFULL 0x000000000000000FULL
3563 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_SHIFT 3U
3564 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_CLRMSK 0xFFFFFFF7U
3565 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_EN 0x00000008U
3566 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_SHIFT 2U
3567 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU
3568 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_EN 0x00000004U
3569 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_SHIFT 1U
3570 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU
3571 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_EN 0x00000002U
3572 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_SHIFT 0U
3573 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU
3574 #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_EN 0x00000001U
3575 
3576 /* Register ROGUE_CR_FWCORE_MEM_MMU_STATUS */
3577 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS 0x30C8U
3578 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL
3579 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_SHIFT 20U
3580 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
3581 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_SHIFT 12U
3582 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
3583 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_SHIFT 4U
3584 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
3585 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_SHIFT 2U
3586 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
3587 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_EN 0x00000004U
3588 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_SHIFT 1U
3589 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
3590 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_EN 0x00000002U
3591 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_SHIFT 0U
3592 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
3593 #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_EN 0x00000001U
3594 
3595 /* Register ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS */
3596 #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS 0x30D8U
3597 #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MASKFULL 0x0000000000000FFFULL
3598 #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_SHIFT 0U
3599 #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_CLRMSK 0xFFFFF000U
3600 
3601 /* Register ROGUE_CR_FWCORE_MEM_READS_INT_STATUS */
3602 #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS 0x30E0U
3603 #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MASKFULL 0x00000000000007FFULL
3604 #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_SHIFT 0U
3605 #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_CLRMSK 0xFFFFF800U
3606 
3607 /* Register ROGUE_CR_FWCORE_WRAPPER_FENCE */
3608 #define ROGUE_CR_FWCORE_WRAPPER_FENCE 0x30E8U
3609 #define ROGUE_CR_FWCORE_WRAPPER_FENCE_MASKFULL 0x0000000000000001ULL
3610 #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_SHIFT 0U
3611 #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_CLRMSK 0xFFFFFFFEU
3612 #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_EN 0x00000001U
3613 
3614 /* Register group: ROGUE_CR_FWCORE_MEM_CAT_BASE, with 8 repeats */
3615 #define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U
3616 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE0 */
3617 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0 0x30F0U
3618 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
3619 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U
3620 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3621 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U
3622 #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U
3623 
3624 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE1 */
3625 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1 0x30F8U
3626 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
3627 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U
3628 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3629 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U
3630 #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U
3631 
3632 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE2 */
3633 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2 0x3100U
3634 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
3635 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U
3636 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3637 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U
3638 #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U
3639 
3640 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE3 */
3641 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3 0x3108U
3642 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
3643 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U
3644 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3645 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U
3646 #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U
3647 
3648 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE4 */
3649 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4 0x3110U
3650 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
3651 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U
3652 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3653 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U
3654 #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U
3655 
3656 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE5 */
3657 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5 0x3118U
3658 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
3659 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U
3660 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3661 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U
3662 #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U
3663 
3664 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE6 */
3665 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6 0x3120U
3666 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
3667 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U
3668 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3669 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U
3670 #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U
3671 
3672 /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE7 */
3673 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7 0x3128U
3674 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
3675 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U
3676 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
3677 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U
3678 #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U
3679 
3680 /* Register ROGUE_CR_FWCORE_WDT_RESET */
3681 #define ROGUE_CR_FWCORE_WDT_RESET 0x3130U
3682 #define ROGUE_CR_FWCORE_WDT_RESET_MASKFULL 0x0000000000000001ULL
3683 #define ROGUE_CR_FWCORE_WDT_RESET_EN_SHIFT 0U
3684 #define ROGUE_CR_FWCORE_WDT_RESET_EN_CLRMSK 0xFFFFFFFEU
3685 #define ROGUE_CR_FWCORE_WDT_RESET_EN_EN 0x00000001U
3686 
3687 /* Register ROGUE_CR_FWCORE_WDT_CTRL */
3688 #define ROGUE_CR_FWCORE_WDT_CTRL 0x3138U
3689 #define ROGUE_CR_FWCORE_WDT_CTRL_MASKFULL 0x00000000FFFF1F01ULL
3690 #define ROGUE_CR_FWCORE_WDT_CTRL_PROT_SHIFT 16U
3691 #define ROGUE_CR_FWCORE_WDT_CTRL_PROT_CLRMSK 0x0000FFFFU
3692 #define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT 8U
3693 #define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_CLRMSK 0xFFFFE0FFU
3694 #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT 0U
3695 #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
3696 #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_EN 0x00000001U
3697 
3698 /* Register ROGUE_CR_FWCORE_WDT_COUNT */
3699 #define ROGUE_CR_FWCORE_WDT_COUNT 0x3140U
3700 #define ROGUE_CR_FWCORE_WDT_COUNT_MASKFULL 0x00000000FFFFFFFFULL
3701 #define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_SHIFT 0U
3702 #define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK 0x00000000U
3703 
3704 /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED0, with 4 repeats */
3705 #define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U
3706 /* Register ROGUE_CR_FWCORE_DMI_RESERVED00 */
3707 #define ROGUE_CR_FWCORE_DMI_RESERVED00 0x3400U
3708 #define ROGUE_CR_FWCORE_DMI_RESERVED00_MASKFULL 0x0000000000000000ULL
3709 
3710 /* Register ROGUE_CR_FWCORE_DMI_RESERVED01 */
3711 #define ROGUE_CR_FWCORE_DMI_RESERVED01 0x3408U
3712 #define ROGUE_CR_FWCORE_DMI_RESERVED01_MASKFULL 0x0000000000000000ULL
3713 
3714 /* Register ROGUE_CR_FWCORE_DMI_RESERVED02 */
3715 #define ROGUE_CR_FWCORE_DMI_RESERVED02 0x3410U
3716 #define ROGUE_CR_FWCORE_DMI_RESERVED02_MASKFULL 0x0000000000000000ULL
3717 
3718 /* Register ROGUE_CR_FWCORE_DMI_RESERVED03 */
3719 #define ROGUE_CR_FWCORE_DMI_RESERVED03 0x3418U
3720 #define ROGUE_CR_FWCORE_DMI_RESERVED03_MASKFULL 0x0000000000000000ULL
3721 
3722 /* Register ROGUE_CR_FWCORE_DMI_DATA0 */
3723 #define ROGUE_CR_FWCORE_DMI_DATA0 0x3420U
3724 #define ROGUE_CR_FWCORE_DMI_DATA0_MASKFULL 0x0000000000000000ULL
3725 
3726 /* Register ROGUE_CR_FWCORE_DMI_DATA1 */
3727 #define ROGUE_CR_FWCORE_DMI_DATA1 0x3428U
3728 #define ROGUE_CR_FWCORE_DMI_DATA1_MASKFULL 0x0000000000000000ULL
3729 
3730 /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED1, with 5 repeats */
3731 #define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U
3732 /* Register ROGUE_CR_FWCORE_DMI_RESERVED10 */
3733 #define ROGUE_CR_FWCORE_DMI_RESERVED10 0x3430U
3734 #define ROGUE_CR_FWCORE_DMI_RESERVED10_MASKFULL 0x0000000000000000ULL
3735 
3736 /* Register ROGUE_CR_FWCORE_DMI_RESERVED11 */
3737 #define ROGUE_CR_FWCORE_DMI_RESERVED11 0x3438U
3738 #define ROGUE_CR_FWCORE_DMI_RESERVED11_MASKFULL 0x0000000000000000ULL
3739 
3740 /* Register ROGUE_CR_FWCORE_DMI_RESERVED12 */
3741 #define ROGUE_CR_FWCORE_DMI_RESERVED12 0x3440U
3742 #define ROGUE_CR_FWCORE_DMI_RESERVED12_MASKFULL 0x0000000000000000ULL
3743 
3744 /* Register ROGUE_CR_FWCORE_DMI_RESERVED13 */
3745 #define ROGUE_CR_FWCORE_DMI_RESERVED13 0x3448U
3746 #define ROGUE_CR_FWCORE_DMI_RESERVED13_MASKFULL 0x0000000000000000ULL
3747 
3748 /* Register ROGUE_CR_FWCORE_DMI_RESERVED14 */
3749 #define ROGUE_CR_FWCORE_DMI_RESERVED14 0x3450U
3750 #define ROGUE_CR_FWCORE_DMI_RESERVED14_MASKFULL 0x0000000000000000ULL
3751 
3752 /* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */
3753 #define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U
3754 #define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL
3755 
3756 /* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */
3757 #define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U
3758 #define ROGUE_CR_FWCORE_DMI_DMSTATUS_MASKFULL 0x0000000000000000ULL
3759 
3760 /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED2, with 4 repeats */
3761 #define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U
3762 /* Register ROGUE_CR_FWCORE_DMI_RESERVED20 */
3763 #define ROGUE_CR_FWCORE_DMI_RESERVED20 0x3490U
3764 #define ROGUE_CR_FWCORE_DMI_RESERVED20_MASKFULL 0x0000000000000000ULL
3765 
3766 /* Register ROGUE_CR_FWCORE_DMI_RESERVED21 */
3767 #define ROGUE_CR_FWCORE_DMI_RESERVED21 0x3498U
3768 #define ROGUE_CR_FWCORE_DMI_RESERVED21_MASKFULL 0x0000000000000000ULL
3769 
3770 /* Register ROGUE_CR_FWCORE_DMI_RESERVED22 */
3771 #define ROGUE_CR_FWCORE_DMI_RESERVED22 0x34A0U
3772 #define ROGUE_CR_FWCORE_DMI_RESERVED22_MASKFULL 0x0000000000000000ULL
3773 
3774 /* Register ROGUE_CR_FWCORE_DMI_RESERVED23 */
3775 #define ROGUE_CR_FWCORE_DMI_RESERVED23 0x34A8U
3776 #define ROGUE_CR_FWCORE_DMI_RESERVED23_MASKFULL 0x0000000000000000ULL
3777 
3778 /* Register ROGUE_CR_FWCORE_DMI_ABSTRACTCS */
3779 #define ROGUE_CR_FWCORE_DMI_ABSTRACTCS 0x34B0U
3780 #define ROGUE_CR_FWCORE_DMI_ABSTRACTCS_MASKFULL 0x0000000000000000ULL
3781 
3782 /* Register ROGUE_CR_FWCORE_DMI_COMMAND */
3783 #define ROGUE_CR_FWCORE_DMI_COMMAND 0x34B8U
3784 #define ROGUE_CR_FWCORE_DMI_COMMAND_MASKFULL 0x0000000000000000ULL
3785 
3786 /* Register ROGUE_CR_FWCORE_DMI_SBCS */
3787 #define ROGUE_CR_FWCORE_DMI_SBCS 0x35C0U
3788 #define ROGUE_CR_FWCORE_DMI_SBCS_MASKFULL 0x0000000000000000ULL
3789 
3790 /* Register ROGUE_CR_FWCORE_DMI_SBADDRESS0 */
3791 #define ROGUE_CR_FWCORE_DMI_SBADDRESS0 0x35C8U
3792 #define ROGUE_CR_FWCORE_DMI_SBADDRESS0_MASKFULL 0x0000000000000000ULL
3793 
3794 /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED3, with 2 repeats */
3795 #define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U
3796 /* Register ROGUE_CR_FWCORE_DMI_RESERVED30 */
3797 #define ROGUE_CR_FWCORE_DMI_RESERVED30 0x34D0U
3798 #define ROGUE_CR_FWCORE_DMI_RESERVED30_MASKFULL 0x0000000000000000ULL
3799 
3800 /* Register ROGUE_CR_FWCORE_DMI_RESERVED31 */
3801 #define ROGUE_CR_FWCORE_DMI_RESERVED31 0x34D8U
3802 #define ROGUE_CR_FWCORE_DMI_RESERVED31_MASKFULL 0x0000000000000000ULL
3803 
3804 /* Register group: ROGUE_CR_FWCORE_DMI_SBDATA, with 4 repeats */
3805 #define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U
3806 /* Register ROGUE_CR_FWCORE_DMI_SBDATA0 */
3807 #define ROGUE_CR_FWCORE_DMI_SBDATA0 0x35E0U
3808 #define ROGUE_CR_FWCORE_DMI_SBDATA0_MASKFULL 0x0000000000000000ULL
3809 
3810 /* Register ROGUE_CR_FWCORE_DMI_SBDATA1 */
3811 #define ROGUE_CR_FWCORE_DMI_SBDATA1 0x35E8U
3812 #define ROGUE_CR_FWCORE_DMI_SBDATA1_MASKFULL 0x0000000000000000ULL
3813 
3814 /* Register ROGUE_CR_FWCORE_DMI_SBDATA2 */
3815 #define ROGUE_CR_FWCORE_DMI_SBDATA2 0x35F0U
3816 #define ROGUE_CR_FWCORE_DMI_SBDATA2_MASKFULL 0x0000000000000000ULL
3817 
3818 /* Register ROGUE_CR_FWCORE_DMI_SBDATA3 */
3819 #define ROGUE_CR_FWCORE_DMI_SBDATA3 0x35F8U
3820 #define ROGUE_CR_FWCORE_DMI_SBDATA3_MASKFULL 0x0000000000000000ULL
3821 
3822 /* Register ROGUE_CR_FWCORE_DMI_HALTSUM0 */
3823 #define ROGUE_CR_FWCORE_DMI_HALTSUM0 0x3600U
3824 #define ROGUE_CR_FWCORE_DMI_HALTSUM0_MASKFULL 0x0000000000000000ULL
3825 
3826 /* Register ROGUE_CR_SLC_CTRL_MISC */
3827 #define ROGUE_CR_SLC_CTRL_MISC 0x3800U
3828 #define ROGUE_CR_SLC_CTRL_MISC_MASKFULL 0xFFFFFFFF01FF010FULL
3829 #define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_SHIFT 32U
3830 #define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_CLRMSK 0x00000000FFFFFFFFULL
3831 #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_SHIFT 24U
3832 #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_CLRMSK 0xFFFFFFFFFEFFFFFFULL
3833 #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN 0x0000000001000000ULL
3834 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 16U
3835 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFFFFF00FFFFULL
3836 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_64_BYTE 0x0000000000000000ULL
3837 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_128_BYTE 0x0000000000010000ULL
3838 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH1 0x0000000000100000ULL
3839 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH2 0x0000000000110000ULL
3840 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1 0x0000000000200000ULL
3841 #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH2_SCRAMBLE 0x0000000000210000ULL
3842 #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_SHIFT 8U
3843 #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_CLRMSK 0xFFFFFFFFFFFFFEFFULL
3844 #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_EN 0x0000000000000100ULL
3845 #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_SHIFT 3U
3846 #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
3847 #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_EN 0x0000000000000008ULL
3848 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_SHIFT 2U
3849 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_CLRMSK 0xFFFFFFFFFFFFFFFBULL
3850 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_EN 0x0000000000000004ULL
3851 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_SHIFT 1U
3852 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_CLRMSK 0xFFFFFFFFFFFFFFFDULL
3853 #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN 0x0000000000000002ULL
3854 #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_SHIFT 0U
3855 #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_CLRMSK 0xFFFFFFFFFFFFFFFEULL
3856 #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN 0x0000000000000001ULL
3857 
3858 /* Register ROGUE_CR_SLC_CTRL_FLUSH_INVAL */
3859 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL 0x3818U
3860 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_MASKFULL 0x0000000080000FFFULL
3861 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_SHIFT 31U
3862 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_CLRMSK 0x7FFFFFFFU
3863 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_EN 0x80000000U
3864 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_SHIFT 11U
3865 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_CLRMSK 0xFFFFF7FFU
3866 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_EN 0x00000800U
3867 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_SHIFT 10U
3868 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_CLRMSK 0xFFFFFBFFU
3869 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_EN 0x00000400U
3870 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_SHIFT 9U
3871 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_CLRMSK 0xFFFFFDFFU
3872 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_EN 0x00000200U
3873 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_SHIFT 8U
3874 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_CLRMSK 0xFFFFFEFFU
3875 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_EN 0x00000100U
3876 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_SHIFT 7U
3877 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_CLRMSK 0xFFFFFF7FU
3878 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_EN 0x00000080U
3879 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_SHIFT 6U
3880 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_CLRMSK 0xFFFFFFBFU
3881 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_EN 0x00000040U
3882 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_SHIFT 5U
3883 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_CLRMSK 0xFFFFFFDFU
3884 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_EN 0x00000020U
3885 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_SHIFT 4U
3886 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_CLRMSK 0xFFFFFFEFU
3887 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_EN 0x00000010U
3888 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_SHIFT 3U
3889 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_CLRMSK 0xFFFFFFF7U
3890 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_EN 0x00000008U
3891 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_SHIFT 2U
3892 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_CLRMSK 0xFFFFFFFBU
3893 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_EN 0x00000004U
3894 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_SHIFT 1U
3895 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_CLRMSK 0xFFFFFFFDU
3896 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_EN 0x00000002U
3897 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_SHIFT 0U
3898 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_CLRMSK 0xFFFFFFFEU
3899 #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_EN 0x00000001U
3900 
3901 /* Register ROGUE_CR_SLC_STATUS0 */
3902 #define ROGUE_CR_SLC_STATUS0 0x3820U
3903 #define ROGUE_CR_SLC_STATUS0_MASKFULL 0x0000000000000007ULL
3904 #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_SHIFT 2U
3905 #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_CLRMSK 0xFFFFFFFBU
3906 #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_EN 0x00000004U
3907 #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_SHIFT 1U
3908 #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_CLRMSK 0xFFFFFFFDU
3909 #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_EN 0x00000002U
3910 #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_SHIFT 0U
3911 #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_CLRMSK 0xFFFFFFFEU
3912 #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_EN 0x00000001U
3913 
3914 /* Register ROGUE_CR_SLC_CTRL_BYPASS */
3915 #define ROGUE_CR_SLC_CTRL_BYPASS 0x3828U
3916 #define ROGUE_CR_SLC_CTRL_BYPASS__XE_MEM__MASKFULL 0x0FFFFFFFFFFF7FFFULL
3917 #define ROGUE_CR_SLC_CTRL_BYPASS_MASKFULL 0x000000000FFFFFFFULL
3918 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_SHIFT 59U
3919 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_CLRMSK 0xF7FFFFFFFFFFFFFFULL
3920 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_EN 0x0800000000000000ULL
3921 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_SHIFT 58U
3922 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_CLRMSK 0xFBFFFFFFFFFFFFFFULL
3923 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_EN 0x0400000000000000ULL
3924 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_SHIFT 57U
3925 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_CLRMSK 0xFDFFFFFFFFFFFFFFULL
3926 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_EN 0x0200000000000000ULL
3927 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_SHIFT 56U
3928 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_CLRMSK 0xFEFFFFFFFFFFFFFFULL
3929 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_EN 0x0100000000000000ULL
3930 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_SHIFT 55U
3931 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_CLRMSK 0xFF7FFFFFFFFFFFFFULL
3932 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_EN 0x0080000000000000ULL
3933 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_SHIFT 54U
3934 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_CLRMSK 0xFFBFFFFFFFFFFFFFULL
3935 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_EN 0x0040000000000000ULL
3936 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_SHIFT 53U
3937 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_CLRMSK 0xFFDFFFFFFFFFFFFFULL
3938 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_EN 0x0020000000000000ULL
3939 #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_SHIFT 52U
3940 #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_CLRMSK 0xFFEFFFFFFFFFFFFFULL
3941 #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_EN 0x0010000000000000ULL
3942 #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_SHIFT 51U
3943 #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_CLRMSK 0xFFF7FFFFFFFFFFFFULL
3944 #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_EN 0x0008000000000000ULL
3945 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_SHIFT 50U
3946 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_CLRMSK 0xFFFBFFFFFFFFFFFFULL
3947 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_EN 0x0004000000000000ULL
3948 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_SHIFT 49U
3949 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_CLRMSK 0xFFFDFFFFFFFFFFFFULL
3950 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_EN 0x0002000000000000ULL
3951 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_SHIFT 48U
3952 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_CLRMSK 0xFFFEFFFFFFFFFFFFULL
3953 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_EN 0x0001000000000000ULL
3954 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_SHIFT 47U
3955 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_CLRMSK 0xFFFF7FFFFFFFFFFFULL
3956 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_EN 0x0000800000000000ULL
3957 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_SHIFT 46U
3958 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_CLRMSK 0xFFFFBFFFFFFFFFFFULL
3959 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_EN 0x0000400000000000ULL
3960 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_SHIFT 45U
3961 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_CLRMSK 0xFFFFDFFFFFFFFFFFULL
3962 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_EN 0x0000200000000000ULL
3963 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 44U
3964 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_CLRMSK 0xFFFFEFFFFFFFFFFFULL
3965 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_EN 0x0000100000000000ULL
3966 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_SHIFT 43U
3967 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_CLRMSK 0xFFFFF7FFFFFFFFFFULL
3968 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_EN 0x0000080000000000ULL
3969 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_SHIFT 42U
3970 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_CLRMSK 0xFFFFFBFFFFFFFFFFULL
3971 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_EN 0x0000040000000000ULL
3972 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_SHIFT 41U
3973 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_CLRMSK 0xFFFFFDFFFFFFFFFFULL
3974 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_EN 0x0000020000000000ULL
3975 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_SHIFT 40U
3976 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_CLRMSK 0xFFFFFEFFFFFFFFFFULL
3977 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_EN 0x0000010000000000ULL
3978 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_SHIFT 39U
3979 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_CLRMSK 0xFFFFFF7FFFFFFFFFULL
3980 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_EN 0x0000008000000000ULL
3981 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_SHIFT 38U
3982 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_CLRMSK 0xFFFFFFBFFFFFFFFFULL
3983 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_EN 0x0000004000000000ULL
3984 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_SHIFT 37U
3985 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_CLRMSK 0xFFFFFFDFFFFFFFFFULL
3986 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_EN 0x0000002000000000ULL
3987 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 36U
3988 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_CLRMSK 0xFFFFFFEFFFFFFFFFULL
3989 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_EN 0x0000001000000000ULL
3990 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_SHIFT 35U
3991 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_CLRMSK 0xFFFFFFF7FFFFFFFFULL
3992 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_EN 0x0000000800000000ULL
3993 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_SHIFT 34U
3994 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_CLRMSK 0xFFFFFFFBFFFFFFFFULL
3995 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_EN 0x0000000400000000ULL
3996 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_SHIFT 33U
3997 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_CLRMSK 0xFFFFFFFDFFFFFFFFULL
3998 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_EN 0x0000000200000000ULL
3999 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_SHIFT 32U
4000 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_CLRMSK 0xFFFFFFFEFFFFFFFFULL
4001 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_EN 0x0000000100000000ULL
4002 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_SHIFT 31U
4003 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_CLRMSK 0xFFFFFFFF7FFFFFFFULL
4004 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_EN 0x0000000080000000ULL
4005 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_SHIFT 30U
4006 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_CLRMSK 0xFFFFFFFFBFFFFFFFULL
4007 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_EN 0x0000000040000000ULL
4008 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_SHIFT 29U
4009 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_CLRMSK 0xFFFFFFFFDFFFFFFFULL
4010 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_EN 0x0000000020000000ULL
4011 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_SHIFT 28U
4012 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_CLRMSK 0xFFFFFFFFEFFFFFFFULL
4013 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_EN 0x0000000010000000ULL
4014 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_SHIFT 27U
4015 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_CLRMSK 0xFFFFFFFFF7FFFFFFULL
4016 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_EN 0x0000000008000000ULL
4017 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_SHIFT 26U
4018 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_CLRMSK 0xFFFFFFFFFBFFFFFFULL
4019 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_EN 0x0000000004000000ULL
4020 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_SHIFT 25U
4021 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_CLRMSK 0xFFFFFFFFFDFFFFFFULL
4022 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_EN 0x0000000002000000ULL
4023 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_SHIFT 24U
4024 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_CLRMSK 0xFFFFFFFFFEFFFFFFULL
4025 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_EN 0x0000000001000000ULL
4026 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_SHIFT 23U
4027 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_CLRMSK 0xFFFFFFFFFF7FFFFFULL
4028 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_EN 0x0000000000800000ULL
4029 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_SHIFT 22U
4030 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_CLRMSK 0xFFFFFFFFFFBFFFFFULL
4031 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_EN 0x0000000000400000ULL
4032 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 21U
4033 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4034 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_EN 0x0000000000200000ULL
4035 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_SHIFT 20U
4036 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_CLRMSK 0xFFFFFFFFFFEFFFFFULL
4037 #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_EN 0x0000000000100000ULL
4038 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_SHIFT 19U
4039 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_CLRMSK 0xFFFFFFFFFFF7FFFFULL
4040 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_EN 0x0000000000080000ULL
4041 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 18U
4042 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_CLRMSK 0xFFFFFFFFFFFBFFFFULL
4043 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_EN 0x0000000000040000ULL
4044 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 17U
4045 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_CLRMSK 0xFFFFFFFFFFFDFFFFULL
4046 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_EN 0x0000000000020000ULL
4047 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_SHIFT 16U
4048 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_CLRMSK 0xFFFFFFFFFFFEFFFFULL
4049 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_EN 0x0000000000010000ULL
4050 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 15U
4051 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_CLRMSK 0xFFFFFFFFFFFF7FFFULL
4052 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN 0x0000000000008000ULL
4053 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_SHIFT 14U
4054 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_CLRMSK 0xFFFFFFFFFFFFBFFFULL
4055 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_EN 0x0000000000004000ULL
4056 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_SHIFT 13U
4057 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_CLRMSK 0xFFFFFFFFFFFFDFFFULL
4058 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_EN 0x0000000000002000ULL
4059 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_SHIFT 12U
4060 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_CLRMSK 0xFFFFFFFFFFFFEFFFULL
4061 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_EN 0x0000000000001000ULL
4062 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_SHIFT 11U
4063 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_CLRMSK 0xFFFFFFFFFFFFF7FFULL
4064 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_EN 0x0000000000000800ULL
4065 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_SHIFT 10U
4066 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_CLRMSK 0xFFFFFFFFFFFFFBFFULL
4067 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_EN 0x0000000000000400ULL
4068 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_SHIFT 9U
4069 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_CLRMSK 0xFFFFFFFFFFFFFDFFULL
4070 #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_EN 0x0000000000000200ULL
4071 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_SHIFT 8U
4072 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_CLRMSK 0xFFFFFFFFFFFFFEFFULL
4073 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_EN 0x0000000000000100ULL
4074 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_SHIFT 7U
4075 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_CLRMSK 0xFFFFFFFFFFFFFF7FULL
4076 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_EN 0x0000000000000080ULL
4077 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_SHIFT 6U
4078 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_CLRMSK 0xFFFFFFFFFFFFFFBFULL
4079 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_EN 0x0000000000000040ULL
4080 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_SHIFT 5U
4081 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_CLRMSK 0xFFFFFFFFFFFFFFDFULL
4082 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_EN 0x0000000000000020ULL
4083 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_SHIFT 4U
4084 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_CLRMSK 0xFFFFFFFFFFFFFFEFULL
4085 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_EN 0x0000000000000010ULL
4086 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_SHIFT 3U
4087 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
4088 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_EN 0x0000000000000008ULL
4089 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2U
4090 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
4091 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_EN 0x0000000000000004ULL
4092 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_SHIFT 1U
4093 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_CLRMSK 0xFFFFFFFFFFFFFFFDULL
4094 #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_EN 0x0000000000000002ULL
4095 #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_SHIFT 0U
4096 #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
4097 #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_EN 0x0000000000000001ULL
4098 
4099 /* Register ROGUE_CR_SLC_STATUS1 */
4100 #define ROGUE_CR_SLC_STATUS1 0x3870U
4101 #define ROGUE_CR_SLC_STATUS1_MASKFULL 0x800003FF03FFFFFFULL
4102 #define ROGUE_CR_SLC_STATUS1_PAUSED_SHIFT 63U
4103 #define ROGUE_CR_SLC_STATUS1_PAUSED_CLRMSK 0x7FFFFFFFFFFFFFFFULL
4104 #define ROGUE_CR_SLC_STATUS1_PAUSED_EN 0x8000000000000000ULL
4105 #define ROGUE_CR_SLC_STATUS1_READS1_SHIFT 32U
4106 #define ROGUE_CR_SLC_STATUS1_READS1_CLRMSK 0xFFFFFC00FFFFFFFFULL
4107 #define ROGUE_CR_SLC_STATUS1_READS0_SHIFT 16U
4108 #define ROGUE_CR_SLC_STATUS1_READS0_CLRMSK 0xFFFFFFFFFC00FFFFULL
4109 #define ROGUE_CR_SLC_STATUS1_READS1_EXT_SHIFT 8U
4110 #define ROGUE_CR_SLC_STATUS1_READS1_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL
4111 #define ROGUE_CR_SLC_STATUS1_READS0_EXT_SHIFT 0U
4112 #define ROGUE_CR_SLC_STATUS1_READS0_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL
4113 
4114 /* Register ROGUE_CR_SLC_IDLE */
4115 #define ROGUE_CR_SLC_IDLE 0x3898U
4116 #define ROGUE_CR_SLC_IDLE__XE_MEM__MASKFULL 0x00000000000003FFULL
4117 #define ROGUE_CR_SLC_IDLE_MASKFULL 0x00000000000000FFULL
4118 #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_SHIFT 9U
4119 #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_CLRMSK 0xFFFFFDFFU
4120 #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_EN 0x00000200U
4121 #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_SHIFT 8U
4122 #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFEFFU
4123 #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_EN 0x00000100U
4124 #define ROGUE_CR_SLC_IDLE_IMGBV4_SHIFT 7U
4125 #define ROGUE_CR_SLC_IDLE_IMGBV4_CLRMSK 0xFFFFFF7FU
4126 #define ROGUE_CR_SLC_IDLE_IMGBV4_EN 0x00000080U
4127 #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_SHIFT 6U
4128 #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_CLRMSK 0xFFFFFFBFU
4129 #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_EN 0x00000040U
4130 #define ROGUE_CR_SLC_IDLE_RBOFIFO_SHIFT 5U
4131 #define ROGUE_CR_SLC_IDLE_RBOFIFO_CLRMSK 0xFFFFFFDFU
4132 #define ROGUE_CR_SLC_IDLE_RBOFIFO_EN 0x00000020U
4133 #define ROGUE_CR_SLC_IDLE_FRC_CONV_SHIFT 4U
4134 #define ROGUE_CR_SLC_IDLE_FRC_CONV_CLRMSK 0xFFFFFFEFU
4135 #define ROGUE_CR_SLC_IDLE_FRC_CONV_EN 0x00000010U
4136 #define ROGUE_CR_SLC_IDLE_VXE_CONV_SHIFT 3U
4137 #define ROGUE_CR_SLC_IDLE_VXE_CONV_CLRMSK 0xFFFFFFF7U
4138 #define ROGUE_CR_SLC_IDLE_VXE_CONV_EN 0x00000008U
4139 #define ROGUE_CR_SLC_IDLE_VXD_CONV_SHIFT 2U
4140 #define ROGUE_CR_SLC_IDLE_VXD_CONV_CLRMSK 0xFFFFFFFBU
4141 #define ROGUE_CR_SLC_IDLE_VXD_CONV_EN 0x00000004U
4142 #define ROGUE_CR_SLC_IDLE_BIF1_CONV_SHIFT 1U
4143 #define ROGUE_CR_SLC_IDLE_BIF1_CONV_CLRMSK 0xFFFFFFFDU
4144 #define ROGUE_CR_SLC_IDLE_BIF1_CONV_EN 0x00000002U
4145 #define ROGUE_CR_SLC_IDLE_CBAR_SHIFT 0U
4146 #define ROGUE_CR_SLC_IDLE_CBAR_CLRMSK 0xFFFFFFFEU
4147 #define ROGUE_CR_SLC_IDLE_CBAR_EN 0x00000001U
4148 
4149 /* Register ROGUE_CR_SLC_STATUS2 */
4150 #define ROGUE_CR_SLC_STATUS2 0x3908U
4151 #define ROGUE_CR_SLC_STATUS2_MASKFULL 0x000003FF03FFFFFFULL
4152 #define ROGUE_CR_SLC_STATUS2_READS3_SHIFT 32U
4153 #define ROGUE_CR_SLC_STATUS2_READS3_CLRMSK 0xFFFFFC00FFFFFFFFULL
4154 #define ROGUE_CR_SLC_STATUS2_READS2_SHIFT 16U
4155 #define ROGUE_CR_SLC_STATUS2_READS2_CLRMSK 0xFFFFFFFFFC00FFFFULL
4156 #define ROGUE_CR_SLC_STATUS2_READS3_EXT_SHIFT 8U
4157 #define ROGUE_CR_SLC_STATUS2_READS3_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL
4158 #define ROGUE_CR_SLC_STATUS2_READS2_EXT_SHIFT 0U
4159 #define ROGUE_CR_SLC_STATUS2_READS2_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL
4160 
4161 /* Register ROGUE_CR_SLC_CTRL_MISC2 */
4162 #define ROGUE_CR_SLC_CTRL_MISC2 0x3930U
4163 #define ROGUE_CR_SLC_CTRL_MISC2_MASKFULL 0x00000000FFFFFFFFULL
4164 #define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_SHIFT 0U
4165 #define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_CLRMSK 0x00000000U
4166 
4167 /* Register ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE */
4168 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE 0x3938U
4169 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_MASKFULL 0x0000000000000001ULL
4170 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_SHIFT 0U
4171 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_CLRMSK 0xFFFFFFFEU
4172 #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_EN 0x00000001U
4173 
4174 /* Register ROGUE_CR_USC_UVS0_CHECKSUM */
4175 #define ROGUE_CR_USC_UVS0_CHECKSUM 0x5000U
4176 #define ROGUE_CR_USC_UVS0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4177 #define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_SHIFT 0U
4178 #define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_CLRMSK 0x00000000U
4179 
4180 /* Register ROGUE_CR_USC_UVS1_CHECKSUM */
4181 #define ROGUE_CR_USC_UVS1_CHECKSUM 0x5008U
4182 #define ROGUE_CR_USC_UVS1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4183 #define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_SHIFT 0U
4184 #define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_CLRMSK 0x00000000U
4185 
4186 /* Register ROGUE_CR_USC_UVS2_CHECKSUM */
4187 #define ROGUE_CR_USC_UVS2_CHECKSUM 0x5010U
4188 #define ROGUE_CR_USC_UVS2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4189 #define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_SHIFT 0U
4190 #define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_CLRMSK 0x00000000U
4191 
4192 /* Register ROGUE_CR_USC_UVS3_CHECKSUM */
4193 #define ROGUE_CR_USC_UVS3_CHECKSUM 0x5018U
4194 #define ROGUE_CR_USC_UVS3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4195 #define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_SHIFT 0U
4196 #define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_CLRMSK 0x00000000U
4197 
4198 /* Register ROGUE_CR_PPP_SIGNATURE */
4199 #define ROGUE_CR_PPP_SIGNATURE 0x5020U
4200 #define ROGUE_CR_PPP_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
4201 #define ROGUE_CR_PPP_SIGNATURE_VALUE_SHIFT 0U
4202 #define ROGUE_CR_PPP_SIGNATURE_VALUE_CLRMSK 0x00000000U
4203 
4204 /* Register ROGUE_CR_TE_SIGNATURE */
4205 #define ROGUE_CR_TE_SIGNATURE 0x5028U
4206 #define ROGUE_CR_TE_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
4207 #define ROGUE_CR_TE_SIGNATURE_VALUE_SHIFT 0U
4208 #define ROGUE_CR_TE_SIGNATURE_VALUE_CLRMSK 0x00000000U
4209 
4210 /* Register ROGUE_CR_TE_CHECKSUM */
4211 #define ROGUE_CR_TE_CHECKSUM 0x5110U
4212 #define ROGUE_CR_TE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4213 #define ROGUE_CR_TE_CHECKSUM_VALUE_SHIFT 0U
4214 #define ROGUE_CR_TE_CHECKSUM_VALUE_CLRMSK 0x00000000U
4215 
4216 /* Register ROGUE_CR_USC_UVB_CHECKSUM */
4217 #define ROGUE_CR_USC_UVB_CHECKSUM 0x5118U
4218 #define ROGUE_CR_USC_UVB_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4219 #define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_SHIFT 0U
4220 #define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_CLRMSK 0x00000000U
4221 
4222 /* Register ROGUE_CR_VCE_CHECKSUM */
4223 #define ROGUE_CR_VCE_CHECKSUM 0x5030U
4224 #define ROGUE_CR_VCE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4225 #define ROGUE_CR_VCE_CHECKSUM_VALUE_SHIFT 0U
4226 #define ROGUE_CR_VCE_CHECKSUM_VALUE_CLRMSK 0x00000000U
4227 
4228 /* Register ROGUE_CR_ISP_PDS_CHECKSUM */
4229 #define ROGUE_CR_ISP_PDS_CHECKSUM 0x5038U
4230 #define ROGUE_CR_ISP_PDS_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4231 #define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT 0U
4232 #define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_CLRMSK 0x00000000U
4233 
4234 /* Register ROGUE_CR_ISP_TPF_CHECKSUM */
4235 #define ROGUE_CR_ISP_TPF_CHECKSUM 0x5040U
4236 #define ROGUE_CR_ISP_TPF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4237 #define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT 0U
4238 #define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_CLRMSK 0x00000000U
4239 
4240 /* Register ROGUE_CR_TFPU_PLANE0_CHECKSUM */
4241 #define ROGUE_CR_TFPU_PLANE0_CHECKSUM 0x5048U
4242 #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4243 #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_SHIFT 0U
4244 #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_CLRMSK 0x00000000U
4245 
4246 /* Register ROGUE_CR_TFPU_PLANE1_CHECKSUM */
4247 #define ROGUE_CR_TFPU_PLANE1_CHECKSUM 0x5050U
4248 #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4249 #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_SHIFT 0U
4250 #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_CLRMSK 0x00000000U
4251 
4252 /* Register ROGUE_CR_PBE_CHECKSUM */
4253 #define ROGUE_CR_PBE_CHECKSUM 0x5058U
4254 #define ROGUE_CR_PBE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4255 #define ROGUE_CR_PBE_CHECKSUM_VALUE_SHIFT 0U
4256 #define ROGUE_CR_PBE_CHECKSUM_VALUE_CLRMSK 0x00000000U
4257 
4258 /* Register ROGUE_CR_PDS_DOUTM_STM_SIGNATURE */
4259 #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE 0x5060U
4260 #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
4261 #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_SHIFT 0U
4262 #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_CLRMSK 0x00000000U
4263 
4264 /* Register ROGUE_CR_IFPU_ISP_CHECKSUM */
4265 #define ROGUE_CR_IFPU_ISP_CHECKSUM 0x5068U
4266 #define ROGUE_CR_IFPU_ISP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4267 #define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT 0U
4268 #define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_CLRMSK 0x00000000U
4269 
4270 /* Register ROGUE_CR_USC_UVS4_CHECKSUM */
4271 #define ROGUE_CR_USC_UVS4_CHECKSUM 0x5100U
4272 #define ROGUE_CR_USC_UVS4_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4273 #define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_SHIFT 0U
4274 #define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_CLRMSK 0x00000000U
4275 
4276 /* Register ROGUE_CR_USC_UVS5_CHECKSUM */
4277 #define ROGUE_CR_USC_UVS5_CHECKSUM 0x5108U
4278 #define ROGUE_CR_USC_UVS5_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4279 #define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_SHIFT 0U
4280 #define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_CLRMSK 0x00000000U
4281 
4282 /* Register ROGUE_CR_PPP_CLIP_CHECKSUM */
4283 #define ROGUE_CR_PPP_CLIP_CHECKSUM 0x5120U
4284 #define ROGUE_CR_PPP_CLIP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
4285 #define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT 0U
4286 #define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_CLRMSK 0x00000000U
4287 
4288 /* Register ROGUE_CR_PERF_TA_PHASE */
4289 #define ROGUE_CR_PERF_TA_PHASE 0x6008U
4290 #define ROGUE_CR_PERF_TA_PHASE_MASKFULL 0x00000000FFFFFFFFULL
4291 #define ROGUE_CR_PERF_TA_PHASE_COUNT_SHIFT 0U
4292 #define ROGUE_CR_PERF_TA_PHASE_COUNT_CLRMSK 0x00000000U
4293 
4294 /* Register ROGUE_CR_PERF_3D_PHASE */
4295 #define ROGUE_CR_PERF_3D_PHASE 0x6010U
4296 #define ROGUE_CR_PERF_3D_PHASE_MASKFULL 0x00000000FFFFFFFFULL
4297 #define ROGUE_CR_PERF_3D_PHASE_COUNT_SHIFT 0U
4298 #define ROGUE_CR_PERF_3D_PHASE_COUNT_CLRMSK 0x00000000U
4299 
4300 /* Register ROGUE_CR_PERF_COMPUTE_PHASE */
4301 #define ROGUE_CR_PERF_COMPUTE_PHASE 0x6018U
4302 #define ROGUE_CR_PERF_COMPUTE_PHASE_MASKFULL 0x00000000FFFFFFFFULL
4303 #define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_SHIFT 0U
4304 #define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_CLRMSK 0x00000000U
4305 
4306 /* Register ROGUE_CR_PERF_TA_CYCLE */
4307 #define ROGUE_CR_PERF_TA_CYCLE 0x6020U
4308 #define ROGUE_CR_PERF_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
4309 #define ROGUE_CR_PERF_TA_CYCLE_COUNT_SHIFT 0U
4310 #define ROGUE_CR_PERF_TA_CYCLE_COUNT_CLRMSK 0x00000000U
4311 
4312 /* Register ROGUE_CR_PERF_3D_CYCLE */
4313 #define ROGUE_CR_PERF_3D_CYCLE 0x6028U
4314 #define ROGUE_CR_PERF_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
4315 #define ROGUE_CR_PERF_3D_CYCLE_COUNT_SHIFT 0U
4316 #define ROGUE_CR_PERF_3D_CYCLE_COUNT_CLRMSK 0x00000000U
4317 
4318 /* Register ROGUE_CR_PERF_COMPUTE_CYCLE */
4319 #define ROGUE_CR_PERF_COMPUTE_CYCLE 0x6030U
4320 #define ROGUE_CR_PERF_COMPUTE_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
4321 #define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_SHIFT 0U
4322 #define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_CLRMSK 0x00000000U
4323 
4324 /* Register ROGUE_CR_PERF_TA_OR_3D_CYCLE */
4325 #define ROGUE_CR_PERF_TA_OR_3D_CYCLE 0x6038U
4326 #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
4327 #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_SHIFT 0U
4328 #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_CLRMSK 0x00000000U
4329 
4330 /* Register ROGUE_CR_PERF_INITIAL_TA_CYCLE */
4331 #define ROGUE_CR_PERF_INITIAL_TA_CYCLE 0x6040U
4332 #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
4333 #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_SHIFT 0U
4334 #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_CLRMSK 0x00000000U
4335 
4336 /* Register ROGUE_CR_PERF_SLC0_READ_STALL */
4337 #define ROGUE_CR_PERF_SLC0_READ_STALL 0x60B8U
4338 #define ROGUE_CR_PERF_SLC0_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
4339 #define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT 0U
4340 #define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK 0x00000000U
4341 
4342 /* Register ROGUE_CR_PERF_SLC0_WRITE_STALL */
4343 #define ROGUE_CR_PERF_SLC0_WRITE_STALL 0x60C0U
4344 #define ROGUE_CR_PERF_SLC0_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
4345 #define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT 0U
4346 #define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK 0x00000000U
4347 
4348 /* Register ROGUE_CR_PERF_SLC1_READ_STALL */
4349 #define ROGUE_CR_PERF_SLC1_READ_STALL 0x60E0U
4350 #define ROGUE_CR_PERF_SLC1_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
4351 #define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT 0U
4352 #define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_CLRMSK 0x00000000U
4353 
4354 /* Register ROGUE_CR_PERF_SLC1_WRITE_STALL */
4355 #define ROGUE_CR_PERF_SLC1_WRITE_STALL 0x60E8U
4356 #define ROGUE_CR_PERF_SLC1_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
4357 #define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT 0U
4358 #define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_CLRMSK 0x00000000U
4359 
4360 /* Register ROGUE_CR_PERF_SLC2_READ_STALL */
4361 #define ROGUE_CR_PERF_SLC2_READ_STALL 0x6158U
4362 #define ROGUE_CR_PERF_SLC2_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
4363 #define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT 0U
4364 #define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_CLRMSK 0x00000000U
4365 
4366 /* Register ROGUE_CR_PERF_SLC2_WRITE_STALL */
4367 #define ROGUE_CR_PERF_SLC2_WRITE_STALL 0x6160U
4368 #define ROGUE_CR_PERF_SLC2_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
4369 #define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT 0U
4370 #define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_CLRMSK 0x00000000U
4371 
4372 /* Register ROGUE_CR_PERF_SLC3_READ_STALL */
4373 #define ROGUE_CR_PERF_SLC3_READ_STALL 0x6180U
4374 #define ROGUE_CR_PERF_SLC3_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
4375 #define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT 0U
4376 #define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_CLRMSK 0x00000000U
4377 
4378 /* Register ROGUE_CR_PERF_SLC3_WRITE_STALL */
4379 #define ROGUE_CR_PERF_SLC3_WRITE_STALL 0x6188U
4380 #define ROGUE_CR_PERF_SLC3_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
4381 #define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT 0U
4382 #define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_CLRMSK 0x00000000U
4383 
4384 /* Register ROGUE_CR_PERF_3D_SPINUP */
4385 #define ROGUE_CR_PERF_3D_SPINUP 0x6220U
4386 #define ROGUE_CR_PERF_3D_SPINUP_MASKFULL 0x00000000FFFFFFFFULL
4387 #define ROGUE_CR_PERF_3D_SPINUP_CYCLES_SHIFT 0U
4388 #define ROGUE_CR_PERF_3D_SPINUP_CYCLES_CLRMSK 0x00000000U
4389 
4390 /* Register ROGUE_CR_AXI_ACE_LITE_CONFIGURATION */
4391 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION 0x38C0U
4392 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_MASKFULL 0x00003FFFFFFFFFFFULL
4393 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT 45U
4394 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_CLRMSK 0xFFFFDFFFFFFFFFFFULL
4395 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_EN 0x0000200000000000ULL
4396 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_SHIFT 37U
4397 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_CLRMSK 0xFFFFE01FFFFFFFFFULL
4398 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT 36U
4399 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_CLRMSK \
4400 	0xFFFFFFEFFFFFFFFFULL
4401 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_EN \
4402 	0x0000001000000000ULL
4403 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_SHIFT 35U
4404 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_CLRMSK 0xFFFFFFF7FFFFFFFFULL
4405 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_EN 0x0000000800000000ULL
4406 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_SHIFT 34U
4407 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_CLRMSK 0xFFFFFFFBFFFFFFFFULL
4408 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_EN 0x0000000400000000ULL
4409 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT 30U
4410 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFC3FFFFFFFULL
4411 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT 26U
4412 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_CLRMSK 0xFFFFFFFFC3FFFFFFULL
4413 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT 22U
4414 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_CLRMSK 0xFFFFFFFFFC3FFFFFULL
4415 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_SHIFT 20U
4416 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFCFFFFFULL
4417 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_SHIFT 18U
4418 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFF3FFFFULL
4419 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT 16U
4420 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFFFFFCFFFFULL
4421 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT 14U
4422 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFF3FFFULL
4423 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT 12U
4424 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFFCFFFULL
4425 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT 10U
4426 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFF3FFULL
4427 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT 8U
4428 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFCFFULL
4429 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_SHIFT 4U
4430 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFF0FULL
4431 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_SHIFT 0U
4432 #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFFF0ULL
4433 
4434 /* Register ROGUE_CR_POWER_ESTIMATE_RESULT */
4435 #define ROGUE_CR_POWER_ESTIMATE_RESULT 0x6328U
4436 #define ROGUE_CR_POWER_ESTIMATE_RESULT_MASKFULL 0x00000000FFFFFFFFULL
4437 #define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_SHIFT 0U
4438 #define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_CLRMSK 0x00000000U
4439 
4440 /* Register ROGUE_CR_TA_PERF */
4441 #define ROGUE_CR_TA_PERF 0x7600U
4442 #define ROGUE_CR_TA_PERF_MASKFULL 0x000000000000001FULL
4443 #define ROGUE_CR_TA_PERF_CLR_3_SHIFT 4U
4444 #define ROGUE_CR_TA_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4445 #define ROGUE_CR_TA_PERF_CLR_3_EN 0x00000010U
4446 #define ROGUE_CR_TA_PERF_CLR_2_SHIFT 3U
4447 #define ROGUE_CR_TA_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4448 #define ROGUE_CR_TA_PERF_CLR_2_EN 0x00000008U
4449 #define ROGUE_CR_TA_PERF_CLR_1_SHIFT 2U
4450 #define ROGUE_CR_TA_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4451 #define ROGUE_CR_TA_PERF_CLR_1_EN 0x00000004U
4452 #define ROGUE_CR_TA_PERF_CLR_0_SHIFT 1U
4453 #define ROGUE_CR_TA_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4454 #define ROGUE_CR_TA_PERF_CLR_0_EN 0x00000002U
4455 #define ROGUE_CR_TA_PERF_CTRL_ENABLE_SHIFT 0U
4456 #define ROGUE_CR_TA_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4457 #define ROGUE_CR_TA_PERF_CTRL_ENABLE_EN 0x00000001U
4458 
4459 /* Register ROGUE_CR_TA_PERF_SELECT0 */
4460 #define ROGUE_CR_TA_PERF_SELECT0 0x7608U
4461 #define ROGUE_CR_TA_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4462 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4463 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4464 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4465 #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4466 #define ROGUE_CR_TA_PERF_SELECT0_MODE_SHIFT 21U
4467 #define ROGUE_CR_TA_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4468 #define ROGUE_CR_TA_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4469 #define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4470 #define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4471 #define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4472 #define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4473 
4474 /* Register ROGUE_CR_TA_PERF_SELECT1 */
4475 #define ROGUE_CR_TA_PERF_SELECT1 0x7610U
4476 #define ROGUE_CR_TA_PERF_SELECT1_MASKFULL 0x3FFF3FFF003FFFFFULL
4477 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_SHIFT 48U
4478 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4479 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_SHIFT 32U
4480 #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4481 #define ROGUE_CR_TA_PERF_SELECT1_MODE_SHIFT 21U
4482 #define ROGUE_CR_TA_PERF_SELECT1_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4483 #define ROGUE_CR_TA_PERF_SELECT1_MODE_EN 0x0000000000200000ULL
4484 #define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_SHIFT 16U
4485 #define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4486 #define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_SHIFT 0U
4487 #define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4488 
4489 /* Register ROGUE_CR_TA_PERF_SELECT2 */
4490 #define ROGUE_CR_TA_PERF_SELECT2 0x7618U
4491 #define ROGUE_CR_TA_PERF_SELECT2_MASKFULL 0x3FFF3FFF003FFFFFULL
4492 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_SHIFT 48U
4493 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4494 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_SHIFT 32U
4495 #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4496 #define ROGUE_CR_TA_PERF_SELECT2_MODE_SHIFT 21U
4497 #define ROGUE_CR_TA_PERF_SELECT2_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4498 #define ROGUE_CR_TA_PERF_SELECT2_MODE_EN 0x0000000000200000ULL
4499 #define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_SHIFT 16U
4500 #define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4501 #define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_SHIFT 0U
4502 #define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4503 
4504 /* Register ROGUE_CR_TA_PERF_SELECT3 */
4505 #define ROGUE_CR_TA_PERF_SELECT3 0x7620U
4506 #define ROGUE_CR_TA_PERF_SELECT3_MASKFULL 0x3FFF3FFF003FFFFFULL
4507 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_SHIFT 48U
4508 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4509 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_SHIFT 32U
4510 #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4511 #define ROGUE_CR_TA_PERF_SELECT3_MODE_SHIFT 21U
4512 #define ROGUE_CR_TA_PERF_SELECT3_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4513 #define ROGUE_CR_TA_PERF_SELECT3_MODE_EN 0x0000000000200000ULL
4514 #define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_SHIFT 16U
4515 #define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4516 #define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_SHIFT 0U
4517 #define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4518 
4519 /* Register ROGUE_CR_TA_PERF_SELECTED_BITS */
4520 #define ROGUE_CR_TA_PERF_SELECTED_BITS 0x7648U
4521 #define ROGUE_CR_TA_PERF_SELECTED_BITS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
4522 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_SHIFT 48U
4523 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_CLRMSK 0x0000FFFFFFFFFFFFULL
4524 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_SHIFT 32U
4525 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_CLRMSK 0xFFFF0000FFFFFFFFULL
4526 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_SHIFT 16U
4527 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_CLRMSK 0xFFFFFFFF0000FFFFULL
4528 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_SHIFT 0U
4529 #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_CLRMSK 0xFFFFFFFFFFFF0000ULL
4530 
4531 /* Register ROGUE_CR_TA_PERF_COUNTER_0 */
4532 #define ROGUE_CR_TA_PERF_COUNTER_0 0x7650U
4533 #define ROGUE_CR_TA_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4534 #define ROGUE_CR_TA_PERF_COUNTER_0_REG_SHIFT 0U
4535 #define ROGUE_CR_TA_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4536 
4537 /* Register ROGUE_CR_TA_PERF_COUNTER_1 */
4538 #define ROGUE_CR_TA_PERF_COUNTER_1 0x7658U
4539 #define ROGUE_CR_TA_PERF_COUNTER_1_MASKFULL 0x00000000FFFFFFFFULL
4540 #define ROGUE_CR_TA_PERF_COUNTER_1_REG_SHIFT 0U
4541 #define ROGUE_CR_TA_PERF_COUNTER_1_REG_CLRMSK 0x00000000U
4542 
4543 /* Register ROGUE_CR_TA_PERF_COUNTER_2 */
4544 #define ROGUE_CR_TA_PERF_COUNTER_2 0x7660U
4545 #define ROGUE_CR_TA_PERF_COUNTER_2_MASKFULL 0x00000000FFFFFFFFULL
4546 #define ROGUE_CR_TA_PERF_COUNTER_2_REG_SHIFT 0U
4547 #define ROGUE_CR_TA_PERF_COUNTER_2_REG_CLRMSK 0x00000000U
4548 
4549 /* Register ROGUE_CR_TA_PERF_COUNTER_3 */
4550 #define ROGUE_CR_TA_PERF_COUNTER_3 0x7668U
4551 #define ROGUE_CR_TA_PERF_COUNTER_3_MASKFULL 0x00000000FFFFFFFFULL
4552 #define ROGUE_CR_TA_PERF_COUNTER_3_REG_SHIFT 0U
4553 #define ROGUE_CR_TA_PERF_COUNTER_3_REG_CLRMSK 0x00000000U
4554 
4555 /* Register ROGUE_CR_RASTERISATION_PERF */
4556 #define ROGUE_CR_RASTERISATION_PERF 0x7700U
4557 #define ROGUE_CR_RASTERISATION_PERF_MASKFULL 0x000000000000001FULL
4558 #define ROGUE_CR_RASTERISATION_PERF_CLR_3_SHIFT 4U
4559 #define ROGUE_CR_RASTERISATION_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4560 #define ROGUE_CR_RASTERISATION_PERF_CLR_3_EN 0x00000010U
4561 #define ROGUE_CR_RASTERISATION_PERF_CLR_2_SHIFT 3U
4562 #define ROGUE_CR_RASTERISATION_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4563 #define ROGUE_CR_RASTERISATION_PERF_CLR_2_EN 0x00000008U
4564 #define ROGUE_CR_RASTERISATION_PERF_CLR_1_SHIFT 2U
4565 #define ROGUE_CR_RASTERISATION_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4566 #define ROGUE_CR_RASTERISATION_PERF_CLR_1_EN 0x00000004U
4567 #define ROGUE_CR_RASTERISATION_PERF_CLR_0_SHIFT 1U
4568 #define ROGUE_CR_RASTERISATION_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4569 #define ROGUE_CR_RASTERISATION_PERF_CLR_0_EN 0x00000002U
4570 #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_SHIFT 0U
4571 #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4572 #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_EN 0x00000001U
4573 
4574 /* Register ROGUE_CR_RASTERISATION_PERF_SELECT0 */
4575 #define ROGUE_CR_RASTERISATION_PERF_SELECT0 0x7708U
4576 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4577 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4578 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4579 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4580 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4581 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_SHIFT 21U
4582 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4583 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4584 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4585 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4586 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4587 #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4588 
4589 /* Register ROGUE_CR_RASTERISATION_PERF_COUNTER_0 */
4590 #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0 0x7750U
4591 #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4592 #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_SHIFT 0U
4593 #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4594 
4595 /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF */
4596 #define ROGUE_CR_HUB_BIFPMCACHE_PERF 0x7800U
4597 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_MASKFULL 0x000000000000001FULL
4598 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_SHIFT 4U
4599 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4600 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_EN 0x00000010U
4601 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_SHIFT 3U
4602 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4603 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_EN 0x00000008U
4604 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_SHIFT 2U
4605 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4606 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_EN 0x00000004U
4607 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_SHIFT 1U
4608 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4609 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_EN 0x00000002U
4610 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_SHIFT 0U
4611 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4612 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_EN 0x00000001U
4613 
4614 /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 */
4615 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 0x7808U
4616 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4617 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4618 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4619 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4620 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4621 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_SHIFT 21U
4622 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4623 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4624 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4625 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4626 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4627 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4628 
4629 /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 */
4630 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 0x7850U
4631 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4632 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_SHIFT 0U
4633 #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4634 
4635 /* Register ROGUE_CR_TPU_MCU_L0_PERF */
4636 #define ROGUE_CR_TPU_MCU_L0_PERF 0x7900U
4637 #define ROGUE_CR_TPU_MCU_L0_PERF_MASKFULL 0x000000000000001FULL
4638 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_SHIFT 4U
4639 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4640 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_EN 0x00000010U
4641 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_SHIFT 3U
4642 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4643 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_EN 0x00000008U
4644 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_SHIFT 2U
4645 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4646 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_EN 0x00000004U
4647 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_SHIFT 1U
4648 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4649 #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_EN 0x00000002U
4650 #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_SHIFT 0U
4651 #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4652 #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_EN 0x00000001U
4653 
4654 /* Register ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 */
4655 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 0x7908U
4656 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4657 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4658 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4659 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4660 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4661 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_SHIFT 21U
4662 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4663 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4664 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4665 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4666 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4667 #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4668 
4669 /* Register ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 */
4670 #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 0x7950U
4671 #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4672 #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_SHIFT 0U
4673 #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4674 
4675 /* Register ROGUE_CR_USC_PERF */
4676 #define ROGUE_CR_USC_PERF 0x8100U
4677 #define ROGUE_CR_USC_PERF_MASKFULL 0x000000000000001FULL
4678 #define ROGUE_CR_USC_PERF_CLR_3_SHIFT 4U
4679 #define ROGUE_CR_USC_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4680 #define ROGUE_CR_USC_PERF_CLR_3_EN 0x00000010U
4681 #define ROGUE_CR_USC_PERF_CLR_2_SHIFT 3U
4682 #define ROGUE_CR_USC_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4683 #define ROGUE_CR_USC_PERF_CLR_2_EN 0x00000008U
4684 #define ROGUE_CR_USC_PERF_CLR_1_SHIFT 2U
4685 #define ROGUE_CR_USC_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4686 #define ROGUE_CR_USC_PERF_CLR_1_EN 0x00000004U
4687 #define ROGUE_CR_USC_PERF_CLR_0_SHIFT 1U
4688 #define ROGUE_CR_USC_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4689 #define ROGUE_CR_USC_PERF_CLR_0_EN 0x00000002U
4690 #define ROGUE_CR_USC_PERF_CTRL_ENABLE_SHIFT 0U
4691 #define ROGUE_CR_USC_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4692 #define ROGUE_CR_USC_PERF_CTRL_ENABLE_EN 0x00000001U
4693 
4694 /* Register ROGUE_CR_USC_PERF_SELECT0 */
4695 #define ROGUE_CR_USC_PERF_SELECT0 0x8108U
4696 #define ROGUE_CR_USC_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4697 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4698 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4699 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4700 #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4701 #define ROGUE_CR_USC_PERF_SELECT0_MODE_SHIFT 21U
4702 #define ROGUE_CR_USC_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4703 #define ROGUE_CR_USC_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4704 #define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4705 #define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4706 #define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4707 #define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4708 
4709 /* Register ROGUE_CR_USC_PERF_COUNTER_0 */
4710 #define ROGUE_CR_USC_PERF_COUNTER_0 0x8150U
4711 #define ROGUE_CR_USC_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4712 #define ROGUE_CR_USC_PERF_COUNTER_0_REG_SHIFT 0U
4713 #define ROGUE_CR_USC_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4714 
4715 /* Register ROGUE_CR_JONES_IDLE */
4716 #define ROGUE_CR_JONES_IDLE 0x8328U
4717 #define ROGUE_CR_JONES_IDLE_MASKFULL 0x0000000000007FFFULL
4718 #define ROGUE_CR_JONES_IDLE_TDM_SHIFT 14U
4719 #define ROGUE_CR_JONES_IDLE_TDM_CLRMSK 0xFFFFBFFFU
4720 #define ROGUE_CR_JONES_IDLE_TDM_EN 0x00004000U
4721 #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_SHIFT 13U
4722 #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_CLRMSK 0xFFFFDFFFU
4723 #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_EN 0x00002000U
4724 #define ROGUE_CR_JONES_IDLE_FB_CDC_SHIFT 12U
4725 #define ROGUE_CR_JONES_IDLE_FB_CDC_CLRMSK 0xFFFFEFFFU
4726 #define ROGUE_CR_JONES_IDLE_FB_CDC_EN 0x00001000U
4727 #define ROGUE_CR_JONES_IDLE_MMU_SHIFT 11U
4728 #define ROGUE_CR_JONES_IDLE_MMU_CLRMSK 0xFFFFF7FFU
4729 #define ROGUE_CR_JONES_IDLE_MMU_EN 0x00000800U
4730 #define ROGUE_CR_JONES_IDLE_TLA_SHIFT 10U
4731 #define ROGUE_CR_JONES_IDLE_TLA_CLRMSK 0xFFFFFBFFU
4732 #define ROGUE_CR_JONES_IDLE_TLA_EN 0x00000400U
4733 #define ROGUE_CR_JONES_IDLE_GARTEN_SHIFT 9U
4734 #define ROGUE_CR_JONES_IDLE_GARTEN_CLRMSK 0xFFFFFDFFU
4735 #define ROGUE_CR_JONES_IDLE_GARTEN_EN 0x00000200U
4736 #define ROGUE_CR_JONES_IDLE_HOSTIF_SHIFT 8U
4737 #define ROGUE_CR_JONES_IDLE_HOSTIF_CLRMSK 0xFFFFFEFFU
4738 #define ROGUE_CR_JONES_IDLE_HOSTIF_EN 0x00000100U
4739 #define ROGUE_CR_JONES_IDLE_SOCIF_SHIFT 7U
4740 #define ROGUE_CR_JONES_IDLE_SOCIF_CLRMSK 0xFFFFFF7FU
4741 #define ROGUE_CR_JONES_IDLE_SOCIF_EN 0x00000080U
4742 #define ROGUE_CR_JONES_IDLE_TILING_SHIFT 6U
4743 #define ROGUE_CR_JONES_IDLE_TILING_CLRMSK 0xFFFFFFBFU
4744 #define ROGUE_CR_JONES_IDLE_TILING_EN 0x00000040U
4745 #define ROGUE_CR_JONES_IDLE_IPP_SHIFT 5U
4746 #define ROGUE_CR_JONES_IDLE_IPP_CLRMSK 0xFFFFFFDFU
4747 #define ROGUE_CR_JONES_IDLE_IPP_EN 0x00000020U
4748 #define ROGUE_CR_JONES_IDLE_USCS_SHIFT 4U
4749 #define ROGUE_CR_JONES_IDLE_USCS_CLRMSK 0xFFFFFFEFU
4750 #define ROGUE_CR_JONES_IDLE_USCS_EN 0x00000010U
4751 #define ROGUE_CR_JONES_IDLE_PM_SHIFT 3U
4752 #define ROGUE_CR_JONES_IDLE_PM_CLRMSK 0xFFFFFFF7U
4753 #define ROGUE_CR_JONES_IDLE_PM_EN 0x00000008U
4754 #define ROGUE_CR_JONES_IDLE_CDM_SHIFT 2U
4755 #define ROGUE_CR_JONES_IDLE_CDM_CLRMSK 0xFFFFFFFBU
4756 #define ROGUE_CR_JONES_IDLE_CDM_EN 0x00000004U
4757 #define ROGUE_CR_JONES_IDLE_VDM_SHIFT 1U
4758 #define ROGUE_CR_JONES_IDLE_VDM_CLRMSK 0xFFFFFFFDU
4759 #define ROGUE_CR_JONES_IDLE_VDM_EN 0x00000002U
4760 #define ROGUE_CR_JONES_IDLE_BIF_SHIFT 0U
4761 #define ROGUE_CR_JONES_IDLE_BIF_CLRMSK 0xFFFFFFFEU
4762 #define ROGUE_CR_JONES_IDLE_BIF_EN 0x00000001U
4763 
4764 /* Register ROGUE_CR_TORNADO_PERF */
4765 #define ROGUE_CR_TORNADO_PERF 0x8228U
4766 #define ROGUE_CR_TORNADO_PERF_MASKFULL 0x000000000000001FULL
4767 #define ROGUE_CR_TORNADO_PERF_CLR_3_SHIFT 4U
4768 #define ROGUE_CR_TORNADO_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4769 #define ROGUE_CR_TORNADO_PERF_CLR_3_EN 0x00000010U
4770 #define ROGUE_CR_TORNADO_PERF_CLR_2_SHIFT 3U
4771 #define ROGUE_CR_TORNADO_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4772 #define ROGUE_CR_TORNADO_PERF_CLR_2_EN 0x00000008U
4773 #define ROGUE_CR_TORNADO_PERF_CLR_1_SHIFT 2U
4774 #define ROGUE_CR_TORNADO_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4775 #define ROGUE_CR_TORNADO_PERF_CLR_1_EN 0x00000004U
4776 #define ROGUE_CR_TORNADO_PERF_CLR_0_SHIFT 1U
4777 #define ROGUE_CR_TORNADO_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4778 #define ROGUE_CR_TORNADO_PERF_CLR_0_EN 0x00000002U
4779 #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_SHIFT 0U
4780 #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4781 #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_EN 0x00000001U
4782 
4783 /* Register ROGUE_CR_TORNADO_PERF_SELECT0 */
4784 #define ROGUE_CR_TORNADO_PERF_SELECT0 0x8230U
4785 #define ROGUE_CR_TORNADO_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4786 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4787 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4788 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4789 #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4790 #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_SHIFT 21U
4791 #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4792 #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4793 #define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4794 #define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4795 #define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4796 #define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4797 
4798 /* Register ROGUE_CR_TORNADO_PERF_COUNTER_0 */
4799 #define ROGUE_CR_TORNADO_PERF_COUNTER_0 0x8268U
4800 #define ROGUE_CR_TORNADO_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4801 #define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_SHIFT 0U
4802 #define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4803 
4804 /* Register ROGUE_CR_TEXAS_PERF */
4805 #define ROGUE_CR_TEXAS_PERF 0x8290U
4806 #define ROGUE_CR_TEXAS_PERF_MASKFULL 0x000000000000007FULL
4807 #define ROGUE_CR_TEXAS_PERF_CLR_5_SHIFT 6U
4808 #define ROGUE_CR_TEXAS_PERF_CLR_5_CLRMSK 0xFFFFFFBFU
4809 #define ROGUE_CR_TEXAS_PERF_CLR_5_EN 0x00000040U
4810 #define ROGUE_CR_TEXAS_PERF_CLR_4_SHIFT 5U
4811 #define ROGUE_CR_TEXAS_PERF_CLR_4_CLRMSK 0xFFFFFFDFU
4812 #define ROGUE_CR_TEXAS_PERF_CLR_4_EN 0x00000020U
4813 #define ROGUE_CR_TEXAS_PERF_CLR_3_SHIFT 4U
4814 #define ROGUE_CR_TEXAS_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4815 #define ROGUE_CR_TEXAS_PERF_CLR_3_EN 0x00000010U
4816 #define ROGUE_CR_TEXAS_PERF_CLR_2_SHIFT 3U
4817 #define ROGUE_CR_TEXAS_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4818 #define ROGUE_CR_TEXAS_PERF_CLR_2_EN 0x00000008U
4819 #define ROGUE_CR_TEXAS_PERF_CLR_1_SHIFT 2U
4820 #define ROGUE_CR_TEXAS_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4821 #define ROGUE_CR_TEXAS_PERF_CLR_1_EN 0x00000004U
4822 #define ROGUE_CR_TEXAS_PERF_CLR_0_SHIFT 1U
4823 #define ROGUE_CR_TEXAS_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4824 #define ROGUE_CR_TEXAS_PERF_CLR_0_EN 0x00000002U
4825 #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_SHIFT 0U
4826 #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4827 #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_EN 0x00000001U
4828 
4829 /* Register ROGUE_CR_TEXAS_PERF_SELECT0 */
4830 #define ROGUE_CR_TEXAS_PERF_SELECT0 0x8298U
4831 #define ROGUE_CR_TEXAS_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL
4832 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4833 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4834 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4835 #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4836 #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_SHIFT 31U
4837 #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
4838 #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_EN 0x0000000080000000ULL
4839 #define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4840 #define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL
4841 #define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4842 #define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4843 
4844 /* Register ROGUE_CR_TEXAS_PERF_COUNTER_0 */
4845 #define ROGUE_CR_TEXAS_PERF_COUNTER_0 0x82D8U
4846 #define ROGUE_CR_TEXAS_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4847 #define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_SHIFT 0U
4848 #define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4849 
4850 /* Register ROGUE_CR_JONES_PERF */
4851 #define ROGUE_CR_JONES_PERF 0x8330U
4852 #define ROGUE_CR_JONES_PERF_MASKFULL 0x000000000000001FULL
4853 #define ROGUE_CR_JONES_PERF_CLR_3_SHIFT 4U
4854 #define ROGUE_CR_JONES_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4855 #define ROGUE_CR_JONES_PERF_CLR_3_EN 0x00000010U
4856 #define ROGUE_CR_JONES_PERF_CLR_2_SHIFT 3U
4857 #define ROGUE_CR_JONES_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4858 #define ROGUE_CR_JONES_PERF_CLR_2_EN 0x00000008U
4859 #define ROGUE_CR_JONES_PERF_CLR_1_SHIFT 2U
4860 #define ROGUE_CR_JONES_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4861 #define ROGUE_CR_JONES_PERF_CLR_1_EN 0x00000004U
4862 #define ROGUE_CR_JONES_PERF_CLR_0_SHIFT 1U
4863 #define ROGUE_CR_JONES_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4864 #define ROGUE_CR_JONES_PERF_CLR_0_EN 0x00000002U
4865 #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_SHIFT 0U
4866 #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4867 #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_EN 0x00000001U
4868 
4869 /* Register ROGUE_CR_JONES_PERF_SELECT0 */
4870 #define ROGUE_CR_JONES_PERF_SELECT0 0x8338U
4871 #define ROGUE_CR_JONES_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4872 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4873 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4874 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4875 #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4876 #define ROGUE_CR_JONES_PERF_SELECT0_MODE_SHIFT 21U
4877 #define ROGUE_CR_JONES_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4878 #define ROGUE_CR_JONES_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4879 #define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4880 #define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4881 #define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4882 #define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4883 
4884 /* Register ROGUE_CR_JONES_PERF_COUNTER_0 */
4885 #define ROGUE_CR_JONES_PERF_COUNTER_0 0x8368U
4886 #define ROGUE_CR_JONES_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4887 #define ROGUE_CR_JONES_PERF_COUNTER_0_REG_SHIFT 0U
4888 #define ROGUE_CR_JONES_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4889 
4890 /* Register ROGUE_CR_BLACKPEARL_PERF */
4891 #define ROGUE_CR_BLACKPEARL_PERF 0x8400U
4892 #define ROGUE_CR_BLACKPEARL_PERF_MASKFULL 0x000000000000007FULL
4893 #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_SHIFT 6U
4894 #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_CLRMSK 0xFFFFFFBFU
4895 #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_EN 0x00000040U
4896 #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_SHIFT 5U
4897 #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_CLRMSK 0xFFFFFFDFU
4898 #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_EN 0x00000020U
4899 #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_SHIFT 4U
4900 #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4901 #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_EN 0x00000010U
4902 #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_SHIFT 3U
4903 #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4904 #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_EN 0x00000008U
4905 #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_SHIFT 2U
4906 #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4907 #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_EN 0x00000004U
4908 #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_SHIFT 1U
4909 #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4910 #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_EN 0x00000002U
4911 #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_SHIFT 0U
4912 #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4913 #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_EN 0x00000001U
4914 
4915 /* Register ROGUE_CR_BLACKPEARL_PERF_SELECT0 */
4916 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0 0x8408U
4917 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL
4918 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4919 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4920 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4921 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4922 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_SHIFT 31U
4923 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
4924 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_EN 0x0000000080000000ULL
4925 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4926 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL
4927 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4928 #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4929 
4930 /* Register ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 */
4931 #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 0x8448U
4932 #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4933 #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_SHIFT 0U
4934 #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4935 
4936 /* Register ROGUE_CR_PBE_PERF */
4937 #define ROGUE_CR_PBE_PERF 0x8478U
4938 #define ROGUE_CR_PBE_PERF_MASKFULL 0x000000000000001FULL
4939 #define ROGUE_CR_PBE_PERF_CLR_3_SHIFT 4U
4940 #define ROGUE_CR_PBE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
4941 #define ROGUE_CR_PBE_PERF_CLR_3_EN 0x00000010U
4942 #define ROGUE_CR_PBE_PERF_CLR_2_SHIFT 3U
4943 #define ROGUE_CR_PBE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
4944 #define ROGUE_CR_PBE_PERF_CLR_2_EN 0x00000008U
4945 #define ROGUE_CR_PBE_PERF_CLR_1_SHIFT 2U
4946 #define ROGUE_CR_PBE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
4947 #define ROGUE_CR_PBE_PERF_CLR_1_EN 0x00000004U
4948 #define ROGUE_CR_PBE_PERF_CLR_0_SHIFT 1U
4949 #define ROGUE_CR_PBE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
4950 #define ROGUE_CR_PBE_PERF_CLR_0_EN 0x00000002U
4951 #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_SHIFT 0U
4952 #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
4953 #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_EN 0x00000001U
4954 
4955 /* Register ROGUE_CR_PBE_PERF_SELECT0 */
4956 #define ROGUE_CR_PBE_PERF_SELECT0 0x8480U
4957 #define ROGUE_CR_PBE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
4958 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
4959 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
4960 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
4961 #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
4962 #define ROGUE_CR_PBE_PERF_SELECT0_MODE_SHIFT 21U
4963 #define ROGUE_CR_PBE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
4964 #define ROGUE_CR_PBE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
4965 #define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
4966 #define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
4967 #define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
4968 #define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
4969 
4970 /* Register ROGUE_CR_PBE_PERF_COUNTER_0 */
4971 #define ROGUE_CR_PBE_PERF_COUNTER_0 0x84B0U
4972 #define ROGUE_CR_PBE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
4973 #define ROGUE_CR_PBE_PERF_COUNTER_0_REG_SHIFT 0U
4974 #define ROGUE_CR_PBE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
4975 
4976 /* Register ROGUE_CR_OCP_REVINFO */
4977 #define ROGUE_CR_OCP_REVINFO 0x9000U
4978 #define ROGUE_CR_OCP_REVINFO_MASKFULL 0x00000007FFFFFFFFULL
4979 #define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_SHIFT 33U
4980 #define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_CLRMSK 0xFFFFFFF9FFFFFFFFULL
4981 #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_SHIFT 32U
4982 #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_CLRMSK 0xFFFFFFFEFFFFFFFFULL
4983 #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_EN 0x0000000100000000ULL
4984 #define ROGUE_CR_OCP_REVINFO_REVISION_SHIFT 0U
4985 #define ROGUE_CR_OCP_REVINFO_REVISION_CLRMSK 0xFFFFFFFF00000000ULL
4986 
4987 /* Register ROGUE_CR_OCP_SYSCONFIG */
4988 #define ROGUE_CR_OCP_SYSCONFIG 0x9010U
4989 #define ROGUE_CR_OCP_SYSCONFIG_MASKFULL 0x0000000000000FFFULL
4990 #define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_SHIFT 10U
4991 #define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_CLRMSK 0xFFFFF3FFU
4992 #define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_SHIFT 8U
4993 #define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_CLRMSK 0xFFFFFCFFU
4994 #define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_SHIFT 6U
4995 #define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_CLRMSK 0xFFFFFF3FU
4996 #define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_SHIFT 4U
4997 #define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_CLRMSK 0xFFFFFFCFU
4998 #define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 2U
4999 #define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_CLRMSK 0xFFFFFFF3U
5000 #define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 0U
5001 #define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_CLRMSK 0xFFFFFFFCU
5002 
5003 /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_0 */
5004 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0 0x9020U
5005 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_MASKFULL 0x0000000000000001ULL
5006 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT 0U
5007 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU
5008 #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_EN 0x00000001U
5009 
5010 /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_1 */
5011 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1 0x9028U
5012 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_MASKFULL 0x0000000000000001ULL
5013 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT 0U
5014 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU
5015 #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_EN 0x00000001U
5016 
5017 /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_2 */
5018 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2 0x9030U
5019 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_MASKFULL 0x0000000000000001ULL
5020 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_SHIFT 0U
5021 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_CLRMSK 0xFFFFFFFEU
5022 #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_EN 0x00000001U
5023 
5024 /* Register ROGUE_CR_OCP_IRQSTATUS_0 */
5025 #define ROGUE_CR_OCP_IRQSTATUS_0 0x9038U
5026 #define ROGUE_CR_OCP_IRQSTATUS_0_MASKFULL 0x0000000000000001ULL
5027 #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT 0U
5028 #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU
5029 #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_EN 0x00000001U
5030 
5031 /* Register ROGUE_CR_OCP_IRQSTATUS_1 */
5032 #define ROGUE_CR_OCP_IRQSTATUS_1 0x9040U
5033 #define ROGUE_CR_OCP_IRQSTATUS_1_MASKFULL 0x0000000000000001ULL
5034 #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT 0U
5035 #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU
5036 #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_EN 0x00000001U
5037 
5038 /* Register ROGUE_CR_OCP_IRQSTATUS_2 */
5039 #define ROGUE_CR_OCP_IRQSTATUS_2 0x9048U
5040 #define ROGUE_CR_OCP_IRQSTATUS_2_MASKFULL 0x0000000000000001ULL
5041 #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_SHIFT 0U
5042 #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_CLRMSK 0xFFFFFFFEU
5043 #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_EN 0x00000001U
5044 
5045 /* Register ROGUE_CR_OCP_IRQENABLE_SET_0 */
5046 #define ROGUE_CR_OCP_IRQENABLE_SET_0 0x9050U
5047 #define ROGUE_CR_OCP_IRQENABLE_SET_0_MASKFULL 0x0000000000000001ULL
5048 #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT 0U
5049 #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU
5050 #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_EN 0x00000001U
5051 
5052 /* Register ROGUE_CR_OCP_IRQENABLE_SET_1 */
5053 #define ROGUE_CR_OCP_IRQENABLE_SET_1 0x9058U
5054 #define ROGUE_CR_OCP_IRQENABLE_SET_1_MASKFULL 0x0000000000000001ULL
5055 #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT 0U
5056 #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU
5057 #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_EN 0x00000001U
5058 
5059 /* Register ROGUE_CR_OCP_IRQENABLE_SET_2 */
5060 #define ROGUE_CR_OCP_IRQENABLE_SET_2 0x9060U
5061 #define ROGUE_CR_OCP_IRQENABLE_SET_2_MASKFULL 0x0000000000000001ULL
5062 #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_SHIFT 0U
5063 #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_CLRMSK 0xFFFFFFFEU
5064 #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_EN 0x00000001U
5065 
5066 /* Register ROGUE_CR_OCP_IRQENABLE_CLR_0 */
5067 #define ROGUE_CR_OCP_IRQENABLE_CLR_0 0x9068U
5068 #define ROGUE_CR_OCP_IRQENABLE_CLR_0_MASKFULL 0x0000000000000001ULL
5069 #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT 0U
5070 #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU
5071 #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_EN 0x00000001U
5072 
5073 /* Register ROGUE_CR_OCP_IRQENABLE_CLR_1 */
5074 #define ROGUE_CR_OCP_IRQENABLE_CLR_1 0x9070U
5075 #define ROGUE_CR_OCP_IRQENABLE_CLR_1_MASKFULL 0x0000000000000001ULL
5076 #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT 0U
5077 #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU
5078 #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_EN 0x00000001U
5079 
5080 /* Register ROGUE_CR_OCP_IRQENABLE_CLR_2 */
5081 #define ROGUE_CR_OCP_IRQENABLE_CLR_2 0x9078U
5082 #define ROGUE_CR_OCP_IRQENABLE_CLR_2_MASKFULL 0x0000000000000001ULL
5083 #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_SHIFT 0U
5084 #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_CLRMSK 0xFFFFFFFEU
5085 #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_EN 0x00000001U
5086 
5087 /* Register ROGUE_CR_OCP_IRQ_EVENT */
5088 #define ROGUE_CR_OCP_IRQ_EVENT 0x9080U
5089 #define ROGUE_CR_OCP_IRQ_EVENT_MASKFULL 0x00000000000FFFFFULL
5090 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_SHIFT 19U
5091 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFF7FFFFULL
5092 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_EN 0x0000000000080000ULL
5093 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_SHIFT 18U
5094 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFBFFFFULL
5095 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000040000ULL
5096 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_SHIFT 17U
5097 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFFDFFFFULL
5098 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_EN 0x0000000000020000ULL
5099 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_SHIFT 16U
5100 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFEFFFFULL
5101 #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000010000ULL
5102 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_SHIFT 15U
5103 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFF7FFFULL
5104 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000008000ULL
5105 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_SHIFT 14U
5106 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFBFFFULL
5107 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_EN 0x0000000000004000ULL
5108 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_SHIFT 13U
5109 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFDFFFULL
5110 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_EN 0x0000000000002000ULL
5111 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_SHIFT 12U
5112 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFEFFFULL
5113 #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_EN 0x0000000000001000ULL
5114 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_SHIFT 11U
5115 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFF7FFULL
5116 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000800ULL
5117 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_SHIFT 10U
5118 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFBFFULL
5119 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_EN 0x0000000000000400ULL
5120 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_SHIFT 9U
5121 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFDFFULL
5122 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_EN 0x0000000000000200ULL
5123 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_SHIFT 8U
5124 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFEFFULL
5125 #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_EN 0x0000000000000100ULL
5126 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_SHIFT 7U
5127 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFF7FULL
5128 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000080ULL
5129 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_SHIFT 6U
5130 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFBFULL
5131 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_EN 0x0000000000000040ULL
5132 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_SHIFT 5U
5133 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFDFULL
5134 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_EN 0x0000000000000020ULL
5135 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_SHIFT 4U
5136 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFEFULL
5137 #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_EN 0x0000000000000010ULL
5138 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_SHIFT 3U
5139 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
5140 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000008ULL
5141 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_SHIFT 2U
5142 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
5143 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_EN 0x0000000000000004ULL
5144 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_SHIFT 1U
5145 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFFDULL
5146 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_EN 0x0000000000000002ULL
5147 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_SHIFT 0U
5148 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
5149 #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_EN 0x0000000000000001ULL
5150 
5151 /* Register ROGUE_CR_OCP_DEBUG_CONFIG */
5152 #define ROGUE_CR_OCP_DEBUG_CONFIG 0x9088U
5153 #define ROGUE_CR_OCP_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL
5154 #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_SHIFT 0U
5155 #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_CLRMSK 0xFFFFFFFEU
5156 #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_EN 0x00000001U
5157 
5158 /* Register ROGUE_CR_OCP_DEBUG_STATUS */
5159 #define ROGUE_CR_OCP_DEBUG_STATUS 0x9090U
5160 #define ROGUE_CR_OCP_DEBUG_STATUS_MASKFULL 0x001F1F77FFFFFFFFULL
5161 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_SHIFT 51U
5162 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_CLRMSK 0xFFE7FFFFFFFFFFFFULL
5163 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_SHIFT 50U
5164 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_CLRMSK 0xFFFBFFFFFFFFFFFFULL
5165 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_EN 0x0004000000000000ULL
5166 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_SHIFT 48U
5167 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_CLRMSK 0xFFFCFFFFFFFFFFFFULL
5168 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_SHIFT 43U
5169 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_CLRMSK 0xFFFFE7FFFFFFFFFFULL
5170 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_SHIFT 42U
5171 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_CLRMSK 0xFFFFFBFFFFFFFFFFULL
5172 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_EN 0x0000040000000000ULL
5173 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_SHIFT 40U
5174 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_CLRMSK 0xFFFFFCFFFFFFFFFFULL
5175 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_SHIFT 38U
5176 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_CLRMSK 0xFFFFFFBFFFFFFFFFULL
5177 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_EN 0x0000004000000000ULL
5178 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_SHIFT 37U
5179 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_CLRMSK 0xFFFFFFDFFFFFFFFFULL
5180 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_EN 0x0000002000000000ULL
5181 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_SHIFT 36U
5182 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_CLRMSK 0xFFFFFFEFFFFFFFFFULL
5183 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_EN 0x0000001000000000ULL
5184 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_SHIFT 34U
5185 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_CLRMSK 0xFFFFFFFBFFFFFFFFULL
5186 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_EN 0x0000000400000000ULL
5187 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_SHIFT 33U
5188 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_CLRMSK 0xFFFFFFFDFFFFFFFFULL
5189 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_EN 0x0000000200000000ULL
5190 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_SHIFT 32U
5191 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_CLRMSK 0xFFFFFFFEFFFFFFFFULL
5192 #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_EN 0x0000000100000000ULL
5193 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_SHIFT 31U
5194 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_CLRMSK 0xFFFFFFFF7FFFFFFFULL
5195 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_EN 0x0000000080000000ULL
5196 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_SHIFT 30U
5197 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_CLRMSK 0xFFFFFFFFBFFFFFFFULL
5198 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_EN 0x0000000040000000ULL
5199 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_SHIFT 29U
5200 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_CLRMSK 0xFFFFFFFFDFFFFFFFULL
5201 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_EN 0x0000000020000000ULL
5202 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_SHIFT 27U
5203 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_CLRMSK 0xFFFFFFFFE7FFFFFFULL
5204 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_SHIFT 26U
5205 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_CLRMSK 0xFFFFFFFFFBFFFFFFULL
5206 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_EN 0x0000000004000000ULL
5207 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_SHIFT 24U
5208 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_CLRMSK 0xFFFFFFFFFCFFFFFFULL
5209 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_SHIFT 23U
5210 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_CLRMSK 0xFFFFFFFFFF7FFFFFULL
5211 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_EN 0x0000000000800000ULL
5212 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_SHIFT 22U
5213 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_CLRMSK 0xFFFFFFFFFFBFFFFFULL
5214 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_EN 0x0000000000400000ULL
5215 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_SHIFT 21U
5216 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5217 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_EN 0x0000000000200000ULL
5218 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_SHIFT 19U
5219 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_CLRMSK 0xFFFFFFFFFFE7FFFFULL
5220 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_SHIFT 18U
5221 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_CLRMSK 0xFFFFFFFFFFFBFFFFULL
5222 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_EN 0x0000000000040000ULL
5223 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_SHIFT 16U
5224 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_CLRMSK 0xFFFFFFFFFFFCFFFFULL
5225 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_SHIFT 15U
5226 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_CLRMSK 0xFFFFFFFFFFFF7FFFULL
5227 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_EN 0x0000000000008000ULL
5228 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_SHIFT 14U
5229 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_CLRMSK 0xFFFFFFFFFFFFBFFFULL
5230 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_EN 0x0000000000004000ULL
5231 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_SHIFT 13U
5232 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFDFFFULL
5233 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_EN 0x0000000000002000ULL
5234 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_SHIFT 11U
5235 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_CLRMSK 0xFFFFFFFFFFFFE7FFULL
5236 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_SHIFT 10U
5237 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFBFFULL
5238 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_EN 0x0000000000000400ULL
5239 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_SHIFT 8U
5240 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFCFFULL
5241 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_SHIFT 7U
5242 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_CLRMSK 0xFFFFFFFFFFFFFF7FULL
5243 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_EN 0x0000000000000080ULL
5244 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_SHIFT 6U
5245 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_CLRMSK 0xFFFFFFFFFFFFFFBFULL
5246 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_EN 0x0000000000000040ULL
5247 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_SHIFT 5U
5248 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFFFDFULL
5249 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_EN 0x0000000000000020ULL
5250 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_SHIFT 3U
5251 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_CLRMSK 0xFFFFFFFFFFFFFFE7ULL
5252 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_SHIFT 2U
5253 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFBULL
5254 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_EN 0x0000000000000004ULL
5255 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_SHIFT 0U
5256 #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFCULL
5257 
5258 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_SHIFT 6U
5259 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_CLRMSK 0xFFFFFFBFU
5260 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_EN 0x00000040U
5261 #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_SHIFT 5U
5262 #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_CLRMSK 0xFFFFFFDFU
5263 #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_EN 0x00000020U
5264 #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_SHIFT 4U
5265 #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_CLRMSK 0xFFFFFFEFU
5266 #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_EN 0x00000010U
5267 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_SHIFT 3U
5268 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_CLRMSK 0xFFFFFFF7U
5269 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_EN 0x00000008U
5270 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_SHIFT 2U
5271 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_CLRMSK 0xFFFFFFFBU
5272 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_EN 0x00000004U
5273 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_SHIFT 1U
5274 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_CLRMSK 0xFFFFFFFDU
5275 #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_EN 0x00000002U
5276 #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_SHIFT 0U
5277 #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_CLRMSK 0xFFFFFFFEU
5278 #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_EN 0x00000001U
5279 
5280 #define ROGUE_CR_BIF_TRUST_DM_MASK 0x0000007FU
5281 
5282 /* Register ROGUE_CR_BIF_TRUST */
5283 #define ROGUE_CR_BIF_TRUST 0xA000U
5284 #define ROGUE_CR_BIF_TRUST_MASKFULL 0x00000000001FFFFFULL
5285 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_SHIFT 20U
5286 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFEFFFFFU
5287 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_EN 0x00100000U
5288 #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_SHIFT 19U
5289 #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFF7FFFFU
5290 #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_EN 0x00080000U
5291 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_SHIFT 18U
5292 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_CLRMSK 0xFFFBFFFFU
5293 #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_EN 0x00040000U
5294 #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_SHIFT 17U
5295 #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_CLRMSK 0xFFFDFFFFU
5296 #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_EN 0x00020000U
5297 #define ROGUE_CR_BIF_TRUST_ENABLE_SHIFT 16U
5298 #define ROGUE_CR_BIF_TRUST_ENABLE_CLRMSK 0xFFFEFFFFU
5299 #define ROGUE_CR_BIF_TRUST_ENABLE_EN 0x00010000U
5300 #define ROGUE_CR_BIF_TRUST_DM_TRUSTED_SHIFT 9U
5301 #define ROGUE_CR_BIF_TRUST_DM_TRUSTED_CLRMSK 0xFFFF01FFU
5302 #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_SHIFT 8U
5303 #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFEFFU
5304 #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_EN 0x00000100U
5305 #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_SHIFT 7U
5306 #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFF7FU
5307 #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_EN 0x00000080U
5308 #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_SHIFT 6U
5309 #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFFBFU
5310 #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_EN 0x00000040U
5311 #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_SHIFT 5U
5312 #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFDFU
5313 #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_EN 0x00000020U
5314 #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_SHIFT 4U
5315 #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFEFU
5316 #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_EN 0x00000010U
5317 #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_SHIFT 3U
5318 #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFF7U
5319 #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_EN 0x00000008U
5320 #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_SHIFT 2U
5321 #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFBU
5322 #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_EN 0x00000004U
5323 #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_SHIFT 1U
5324 #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFDU
5325 #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_EN 0x00000002U
5326 #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_SHIFT 0U
5327 #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFEU
5328 #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_EN 0x00000001U
5329 
5330 /* Register ROGUE_CR_SYS_BUS_SECURE */
5331 #define ROGUE_CR_SYS_BUS_SECURE 0xA100U
5332 #define ROGUE_CR_SYS_BUS_SECURE__SECR__MASKFULL 0x0000000000000001ULL
5333 #define ROGUE_CR_SYS_BUS_SECURE_MASKFULL 0x0000000000000001ULL
5334 #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_SHIFT 0U
5335 #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_CLRMSK 0xFFFFFFFEU
5336 #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_EN 0x00000001U
5337 
5338 /* Register ROGUE_CR_FBA_FC0_CHECKSUM */
5339 #define ROGUE_CR_FBA_FC0_CHECKSUM 0xD170U
5340 #define ROGUE_CR_FBA_FC0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5341 #define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_SHIFT 0U
5342 #define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_CLRMSK 0x00000000U
5343 
5344 /* Register ROGUE_CR_FBA_FC1_CHECKSUM */
5345 #define ROGUE_CR_FBA_FC1_CHECKSUM 0xD178U
5346 #define ROGUE_CR_FBA_FC1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5347 #define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_SHIFT 0U
5348 #define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_CLRMSK 0x00000000U
5349 
5350 /* Register ROGUE_CR_FBA_FC2_CHECKSUM */
5351 #define ROGUE_CR_FBA_FC2_CHECKSUM 0xD180U
5352 #define ROGUE_CR_FBA_FC2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5353 #define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_SHIFT 0U
5354 #define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_CLRMSK 0x00000000U
5355 
5356 /* Register ROGUE_CR_FBA_FC3_CHECKSUM */
5357 #define ROGUE_CR_FBA_FC3_CHECKSUM 0xD188U
5358 #define ROGUE_CR_FBA_FC3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5359 #define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_SHIFT 0U
5360 #define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_CLRMSK 0x00000000U
5361 
5362 /* Register ROGUE_CR_CLK_CTRL2 */
5363 #define ROGUE_CR_CLK_CTRL2 0xD200U
5364 #define ROGUE_CR_CLK_CTRL2_MASKFULL 0x0000000000000F33ULL
5365 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_SHIFT 10U
5366 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_CLRMSK 0xFFFFFFFFFFFFF3FFULL
5367 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_OFF 0x0000000000000000ULL
5368 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_ON 0x0000000000000400ULL
5369 #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_AUTO 0x0000000000000800ULL
5370 #define ROGUE_CR_CLK_CTRL2_VRDM_SHIFT 8U
5371 #define ROGUE_CR_CLK_CTRL2_VRDM_CLRMSK 0xFFFFFFFFFFFFFCFFULL
5372 #define ROGUE_CR_CLK_CTRL2_VRDM_OFF 0x0000000000000000ULL
5373 #define ROGUE_CR_CLK_CTRL2_VRDM_ON 0x0000000000000100ULL
5374 #define ROGUE_CR_CLK_CTRL2_VRDM_AUTO 0x0000000000000200ULL
5375 #define ROGUE_CR_CLK_CTRL2_SH_SHIFT 4U
5376 #define ROGUE_CR_CLK_CTRL2_SH_CLRMSK 0xFFFFFFFFFFFFFFCFULL
5377 #define ROGUE_CR_CLK_CTRL2_SH_OFF 0x0000000000000000ULL
5378 #define ROGUE_CR_CLK_CTRL2_SH_ON 0x0000000000000010ULL
5379 #define ROGUE_CR_CLK_CTRL2_SH_AUTO 0x0000000000000020ULL
5380 #define ROGUE_CR_CLK_CTRL2_FBA_SHIFT 0U
5381 #define ROGUE_CR_CLK_CTRL2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFCULL
5382 #define ROGUE_CR_CLK_CTRL2_FBA_OFF 0x0000000000000000ULL
5383 #define ROGUE_CR_CLK_CTRL2_FBA_ON 0x0000000000000001ULL
5384 #define ROGUE_CR_CLK_CTRL2_FBA_AUTO 0x0000000000000002ULL
5385 
5386 /* Register ROGUE_CR_CLK_STATUS2 */
5387 #define ROGUE_CR_CLK_STATUS2 0xD208U
5388 #define ROGUE_CR_CLK_STATUS2_MASKFULL 0x0000000000000015ULL
5389 #define ROGUE_CR_CLK_STATUS2_VRDM_SHIFT 4U
5390 #define ROGUE_CR_CLK_STATUS2_VRDM_CLRMSK 0xFFFFFFFFFFFFFFEFULL
5391 #define ROGUE_CR_CLK_STATUS2_VRDM_GATED 0x0000000000000000ULL
5392 #define ROGUE_CR_CLK_STATUS2_VRDM_RUNNING 0x0000000000000010ULL
5393 #define ROGUE_CR_CLK_STATUS2_SH_SHIFT 2U
5394 #define ROGUE_CR_CLK_STATUS2_SH_CLRMSK 0xFFFFFFFFFFFFFFFBULL
5395 #define ROGUE_CR_CLK_STATUS2_SH_GATED 0x0000000000000000ULL
5396 #define ROGUE_CR_CLK_STATUS2_SH_RUNNING 0x0000000000000004ULL
5397 #define ROGUE_CR_CLK_STATUS2_FBA_SHIFT 0U
5398 #define ROGUE_CR_CLK_STATUS2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFEULL
5399 #define ROGUE_CR_CLK_STATUS2_FBA_GATED 0x0000000000000000ULL
5400 #define ROGUE_CR_CLK_STATUS2_FBA_RUNNING 0x0000000000000001ULL
5401 
5402 /* Register ROGUE_CR_RPM_SHF_FPL */
5403 #define ROGUE_CR_RPM_SHF_FPL 0xD520U
5404 #define ROGUE_CR_RPM_SHF_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL
5405 #define ROGUE_CR_RPM_SHF_FPL_SIZE_SHIFT 40U
5406 #define ROGUE_CR_RPM_SHF_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL
5407 #define ROGUE_CR_RPM_SHF_FPL_BASE_SHIFT 2U
5408 #define ROGUE_CR_RPM_SHF_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL
5409 #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSHIFT 2U
5410 #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSIZE 4U
5411 
5412 /* Register ROGUE_CR_RPM_SHF_FPL_READ */
5413 #define ROGUE_CR_RPM_SHF_FPL_READ 0xD528U
5414 #define ROGUE_CR_RPM_SHF_FPL_READ_MASKFULL 0x00000000007FFFFFULL
5415 #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_SHIFT 22U
5416 #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU
5417 #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_EN 0x00400000U
5418 #define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_SHIFT 0U
5419 #define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_CLRMSK 0xFFC00000U
5420 
5421 /* Register ROGUE_CR_RPM_SHF_FPL_WRITE */
5422 #define ROGUE_CR_RPM_SHF_FPL_WRITE 0xD530U
5423 #define ROGUE_CR_RPM_SHF_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL
5424 #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_SHIFT 22U
5425 #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU
5426 #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_EN 0x00400000U
5427 #define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_SHIFT 0U
5428 #define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U
5429 
5430 /* Register ROGUE_CR_RPM_SHG_FPL */
5431 #define ROGUE_CR_RPM_SHG_FPL 0xD538U
5432 #define ROGUE_CR_RPM_SHG_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL
5433 #define ROGUE_CR_RPM_SHG_FPL_SIZE_SHIFT 40U
5434 #define ROGUE_CR_RPM_SHG_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL
5435 #define ROGUE_CR_RPM_SHG_FPL_BASE_SHIFT 2U
5436 #define ROGUE_CR_RPM_SHG_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL
5437 #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSHIFT 2U
5438 #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSIZE 4U
5439 
5440 /* Register ROGUE_CR_RPM_SHG_FPL_READ */
5441 #define ROGUE_CR_RPM_SHG_FPL_READ 0xD540U
5442 #define ROGUE_CR_RPM_SHG_FPL_READ_MASKFULL 0x00000000007FFFFFULL
5443 #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_SHIFT 22U
5444 #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU
5445 #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_EN 0x00400000U
5446 #define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_SHIFT 0U
5447 #define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_CLRMSK 0xFFC00000U
5448 
5449 /* Register ROGUE_CR_RPM_SHG_FPL_WRITE */
5450 #define ROGUE_CR_RPM_SHG_FPL_WRITE 0xD548U
5451 #define ROGUE_CR_RPM_SHG_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL
5452 #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_SHIFT 22U
5453 #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU
5454 #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_EN 0x00400000U
5455 #define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_SHIFT 0U
5456 #define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U
5457 
5458 /* Register ROGUE_CR_SH_PERF */
5459 #define ROGUE_CR_SH_PERF 0xD5F8U
5460 #define ROGUE_CR_SH_PERF_MASKFULL 0x000000000000001FULL
5461 #define ROGUE_CR_SH_PERF_CLR_3_SHIFT 4U
5462 #define ROGUE_CR_SH_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
5463 #define ROGUE_CR_SH_PERF_CLR_3_EN 0x00000010U
5464 #define ROGUE_CR_SH_PERF_CLR_2_SHIFT 3U
5465 #define ROGUE_CR_SH_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
5466 #define ROGUE_CR_SH_PERF_CLR_2_EN 0x00000008U
5467 #define ROGUE_CR_SH_PERF_CLR_1_SHIFT 2U
5468 #define ROGUE_CR_SH_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
5469 #define ROGUE_CR_SH_PERF_CLR_1_EN 0x00000004U
5470 #define ROGUE_CR_SH_PERF_CLR_0_SHIFT 1U
5471 #define ROGUE_CR_SH_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
5472 #define ROGUE_CR_SH_PERF_CLR_0_EN 0x00000002U
5473 #define ROGUE_CR_SH_PERF_CTRL_ENABLE_SHIFT 0U
5474 #define ROGUE_CR_SH_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
5475 #define ROGUE_CR_SH_PERF_CTRL_ENABLE_EN 0x00000001U
5476 
5477 /* Register ROGUE_CR_SH_PERF_SELECT0 */
5478 #define ROGUE_CR_SH_PERF_SELECT0 0xD600U
5479 #define ROGUE_CR_SH_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
5480 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5481 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
5482 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5483 #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
5484 #define ROGUE_CR_SH_PERF_SELECT0_MODE_SHIFT 21U
5485 #define ROGUE_CR_SH_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5486 #define ROGUE_CR_SH_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
5487 #define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5488 #define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
5489 #define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5490 #define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
5491 
5492 /* Register ROGUE_CR_SH_PERF_COUNTER_0 */
5493 #define ROGUE_CR_SH_PERF_COUNTER_0 0xD628U
5494 #define ROGUE_CR_SH_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
5495 #define ROGUE_CR_SH_PERF_COUNTER_0_REG_SHIFT 0U
5496 #define ROGUE_CR_SH_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
5497 
5498 /* Register ROGUE_CR_SHF_SHG_CHECKSUM */
5499 #define ROGUE_CR_SHF_SHG_CHECKSUM 0xD1C0U
5500 #define ROGUE_CR_SHF_SHG_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5501 #define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_SHIFT 0U
5502 #define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_CLRMSK 0x00000000U
5503 
5504 /* Register ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM */
5505 #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM 0xD1C8U
5506 #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5507 #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_SHIFT 0U
5508 #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
5509 
5510 /* Register ROGUE_CR_SHF_VARY_BIF_CHECKSUM */
5511 #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM 0xD1D0U
5512 #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5513 #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_SHIFT 0U
5514 #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
5515 
5516 /* Register ROGUE_CR_RPM_BIF_CHECKSUM */
5517 #define ROGUE_CR_RPM_BIF_CHECKSUM 0xD1D8U
5518 #define ROGUE_CR_RPM_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5519 #define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_SHIFT 0U
5520 #define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
5521 
5522 /* Register ROGUE_CR_SHG_BIF_CHECKSUM */
5523 #define ROGUE_CR_SHG_BIF_CHECKSUM 0xD1E0U
5524 #define ROGUE_CR_SHG_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5525 #define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_SHIFT 0U
5526 #define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
5527 
5528 /* Register ROGUE_CR_SHG_FE_BE_CHECKSUM */
5529 #define ROGUE_CR_SHG_FE_BE_CHECKSUM 0xD1E8U
5530 #define ROGUE_CR_SHG_FE_BE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5531 #define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_SHIFT 0U
5532 #define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_CLRMSK 0x00000000U
5533 
5534 /* Register DPX_CR_BF_PERF */
5535 #define DPX_CR_BF_PERF 0xC458U
5536 #define DPX_CR_BF_PERF_MASKFULL 0x000000000000001FULL
5537 #define DPX_CR_BF_PERF_CLR_3_SHIFT 4U
5538 #define DPX_CR_BF_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
5539 #define DPX_CR_BF_PERF_CLR_3_EN 0x00000010U
5540 #define DPX_CR_BF_PERF_CLR_2_SHIFT 3U
5541 #define DPX_CR_BF_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
5542 #define DPX_CR_BF_PERF_CLR_2_EN 0x00000008U
5543 #define DPX_CR_BF_PERF_CLR_1_SHIFT 2U
5544 #define DPX_CR_BF_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
5545 #define DPX_CR_BF_PERF_CLR_1_EN 0x00000004U
5546 #define DPX_CR_BF_PERF_CLR_0_SHIFT 1U
5547 #define DPX_CR_BF_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
5548 #define DPX_CR_BF_PERF_CLR_0_EN 0x00000002U
5549 #define DPX_CR_BF_PERF_CTRL_ENABLE_SHIFT 0U
5550 #define DPX_CR_BF_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
5551 #define DPX_CR_BF_PERF_CTRL_ENABLE_EN 0x00000001U
5552 
5553 /* Register DPX_CR_BF_PERF_SELECT0 */
5554 #define DPX_CR_BF_PERF_SELECT0 0xC460U
5555 #define DPX_CR_BF_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
5556 #define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5557 #define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
5558 #define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5559 #define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
5560 #define DPX_CR_BF_PERF_SELECT0_MODE_SHIFT 21U
5561 #define DPX_CR_BF_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5562 #define DPX_CR_BF_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
5563 #define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5564 #define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
5565 #define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5566 #define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
5567 
5568 /* Register DPX_CR_BF_PERF_COUNTER_0 */
5569 #define DPX_CR_BF_PERF_COUNTER_0 0xC488U
5570 #define DPX_CR_BF_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
5571 #define DPX_CR_BF_PERF_COUNTER_0_REG_SHIFT 0U
5572 #define DPX_CR_BF_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
5573 
5574 /* Register DPX_CR_BT_PERF */
5575 #define DPX_CR_BT_PERF 0xC3D0U
5576 #define DPX_CR_BT_PERF_MASKFULL 0x000000000000001FULL
5577 #define DPX_CR_BT_PERF_CLR_3_SHIFT 4U
5578 #define DPX_CR_BT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
5579 #define DPX_CR_BT_PERF_CLR_3_EN 0x00000010U
5580 #define DPX_CR_BT_PERF_CLR_2_SHIFT 3U
5581 #define DPX_CR_BT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
5582 #define DPX_CR_BT_PERF_CLR_2_EN 0x00000008U
5583 #define DPX_CR_BT_PERF_CLR_1_SHIFT 2U
5584 #define DPX_CR_BT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
5585 #define DPX_CR_BT_PERF_CLR_1_EN 0x00000004U
5586 #define DPX_CR_BT_PERF_CLR_0_SHIFT 1U
5587 #define DPX_CR_BT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
5588 #define DPX_CR_BT_PERF_CLR_0_EN 0x00000002U
5589 #define DPX_CR_BT_PERF_CTRL_ENABLE_SHIFT 0U
5590 #define DPX_CR_BT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
5591 #define DPX_CR_BT_PERF_CTRL_ENABLE_EN 0x00000001U
5592 
5593 /* Register DPX_CR_BT_PERF_SELECT0 */
5594 #define DPX_CR_BT_PERF_SELECT0 0xC3D8U
5595 #define DPX_CR_BT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
5596 #define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5597 #define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
5598 #define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5599 #define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
5600 #define DPX_CR_BT_PERF_SELECT0_MODE_SHIFT 21U
5601 #define DPX_CR_BT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5602 #define DPX_CR_BT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
5603 #define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5604 #define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
5605 #define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5606 #define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
5607 
5608 /* Register DPX_CR_BT_PERF_COUNTER_0 */
5609 #define DPX_CR_BT_PERF_COUNTER_0 0xC420U
5610 #define DPX_CR_BT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
5611 #define DPX_CR_BT_PERF_COUNTER_0_REG_SHIFT 0U
5612 #define DPX_CR_BT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
5613 
5614 /* Register DPX_CR_RQ_USC_DEBUG */
5615 #define DPX_CR_RQ_USC_DEBUG 0xC110U
5616 #define DPX_CR_RQ_USC_DEBUG_MASKFULL 0x00000000FFFFFFFFULL
5617 #define DPX_CR_RQ_USC_DEBUG_CHECKSUM_SHIFT 0U
5618 #define DPX_CR_RQ_USC_DEBUG_CHECKSUM_CLRMSK 0xFFFFFFFF00000000ULL
5619 
5620 /* Register DPX_CR_BIF_FAULT_BANK_MMU_STATUS */
5621 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS 0xC5C8U
5622 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_MASKFULL 0x000000000000F775ULL
5623 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_SHIFT 12U
5624 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
5625 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_SHIFT 8U
5626 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
5627 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_SHIFT 5U
5628 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
5629 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_SHIFT 4U
5630 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
5631 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_EN 0x00000010U
5632 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
5633 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
5634 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
5635 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_SHIFT 0U
5636 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
5637 #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_EN 0x00000001U
5638 
5639 /* Register DPX_CR_BIF_FAULT_BANK_REQ_STATUS */
5640 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS 0xC5D0U
5641 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_MASKFULL 0x03FFFFFFFFFFFFF0ULL
5642 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_SHIFT 57U
5643 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_CLRMSK 0xFDFFFFFFFFFFFFFFULL
5644 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_EN 0x0200000000000000ULL
5645 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_SHIFT 44U
5646 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_CLRMSK 0xFE000FFFFFFFFFFFULL
5647 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_SHIFT 40U
5648 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
5649 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_SHIFT 4U
5650 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
5651 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
5652 #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
5653 
5654 /* Register DPX_CR_BIF_MMU_STATUS */
5655 #define DPX_CR_BIF_MMU_STATUS 0xC5D8U
5656 #define DPX_CR_BIF_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL
5657 #define DPX_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
5658 #define DPX_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
5659 #define DPX_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
5660 #define DPX_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
5661 #define DPX_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
5662 #define DPX_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
5663 #define DPX_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
5664 #define DPX_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
5665 #define DPX_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U
5666 #define DPX_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
5667 #define DPX_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
5668 #define DPX_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U
5669 #define DPX_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
5670 #define DPX_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
5671 #define DPX_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U
5672 
5673 /* Register DPX_CR_RT_PERF */
5674 #define DPX_CR_RT_PERF 0xC700U
5675 #define DPX_CR_RT_PERF_MASKFULL 0x000000000000001FULL
5676 #define DPX_CR_RT_PERF_CLR_3_SHIFT 4U
5677 #define DPX_CR_RT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
5678 #define DPX_CR_RT_PERF_CLR_3_EN 0x00000010U
5679 #define DPX_CR_RT_PERF_CLR_2_SHIFT 3U
5680 #define DPX_CR_RT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
5681 #define DPX_CR_RT_PERF_CLR_2_EN 0x00000008U
5682 #define DPX_CR_RT_PERF_CLR_1_SHIFT 2U
5683 #define DPX_CR_RT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
5684 #define DPX_CR_RT_PERF_CLR_1_EN 0x00000004U
5685 #define DPX_CR_RT_PERF_CLR_0_SHIFT 1U
5686 #define DPX_CR_RT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
5687 #define DPX_CR_RT_PERF_CLR_0_EN 0x00000002U
5688 #define DPX_CR_RT_PERF_CTRL_ENABLE_SHIFT 0U
5689 #define DPX_CR_RT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
5690 #define DPX_CR_RT_PERF_CTRL_ENABLE_EN 0x00000001U
5691 
5692 /* Register DPX_CR_RT_PERF_SELECT0 */
5693 #define DPX_CR_RT_PERF_SELECT0 0xC708U
5694 #define DPX_CR_RT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
5695 #define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5696 #define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
5697 #define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5698 #define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
5699 #define DPX_CR_RT_PERF_SELECT0_MODE_SHIFT 21U
5700 #define DPX_CR_RT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5701 #define DPX_CR_RT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
5702 #define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5703 #define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
5704 #define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5705 #define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
5706 
5707 /* Register DPX_CR_RT_PERF_COUNTER_0 */
5708 #define DPX_CR_RT_PERF_COUNTER_0 0xC730U
5709 #define DPX_CR_RT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
5710 #define DPX_CR_RT_PERF_COUNTER_0_REG_SHIFT 0U
5711 #define DPX_CR_RT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
5712 
5713 /* Register DPX_CR_BX_TU_PERF */
5714 #define DPX_CR_BX_TU_PERF 0xC908U
5715 #define DPX_CR_BX_TU_PERF_MASKFULL 0x000000000000001FULL
5716 #define DPX_CR_BX_TU_PERF_CLR_3_SHIFT 4U
5717 #define DPX_CR_BX_TU_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
5718 #define DPX_CR_BX_TU_PERF_CLR_3_EN 0x00000010U
5719 #define DPX_CR_BX_TU_PERF_CLR_2_SHIFT 3U
5720 #define DPX_CR_BX_TU_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
5721 #define DPX_CR_BX_TU_PERF_CLR_2_EN 0x00000008U
5722 #define DPX_CR_BX_TU_PERF_CLR_1_SHIFT 2U
5723 #define DPX_CR_BX_TU_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
5724 #define DPX_CR_BX_TU_PERF_CLR_1_EN 0x00000004U
5725 #define DPX_CR_BX_TU_PERF_CLR_0_SHIFT 1U
5726 #define DPX_CR_BX_TU_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
5727 #define DPX_CR_BX_TU_PERF_CLR_0_EN 0x00000002U
5728 #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_SHIFT 0U
5729 #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
5730 #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_EN 0x00000001U
5731 
5732 /* Register DPX_CR_BX_TU_PERF_SELECT0 */
5733 #define DPX_CR_BX_TU_PERF_SELECT0 0xC910U
5734 #define DPX_CR_BX_TU_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
5735 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_SHIFT 48U
5736 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
5737 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_SHIFT 32U
5738 #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
5739 #define DPX_CR_BX_TU_PERF_SELECT0_MODE_SHIFT 21U
5740 #define DPX_CR_BX_TU_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
5741 #define DPX_CR_BX_TU_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
5742 #define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
5743 #define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
5744 #define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_SHIFT 0U
5745 #define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
5746 
5747 /* Register DPX_CR_BX_TU_PERF_COUNTER_0 */
5748 #define DPX_CR_BX_TU_PERF_COUNTER_0 0xC938U
5749 #define DPX_CR_BX_TU_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
5750 #define DPX_CR_BX_TU_PERF_COUNTER_0_REG_SHIFT 0U
5751 #define DPX_CR_BX_TU_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
5752 
5753 /* Register DPX_CR_RS_PDS_RR_CHECKSUM */
5754 #define DPX_CR_RS_PDS_RR_CHECKSUM 0xC0F0U
5755 #define DPX_CR_RS_PDS_RR_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
5756 #define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_SHIFT 0U
5757 #define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_CLRMSK 0xFFFFFFFF00000000ULL
5758 
5759 /* Register ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT */
5760 #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT 0xE140U
5761 #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_MASKFULL 0x00000000000000FFULL
5762 #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT 0U
5763 #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK 0xFFFFFF00U
5764 
5765 /* Register ROGUE_CR_MMU_CBASE_MAPPING */
5766 #define ROGUE_CR_MMU_CBASE_MAPPING 0xE148U
5767 #define ROGUE_CR_MMU_CBASE_MAPPING_MASKFULL 0x000000000FFFFFFFULL
5768 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT 0U
5769 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK 0xF0000000U
5770 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT 12U
5771 #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE 4096U
5772 
5773 /* Register ROGUE_CR_MMU_FAULT_STATUS */
5774 #define ROGUE_CR_MMU_FAULT_STATUS 0xE150U
5775 #define ROGUE_CR_MMU_FAULT_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5776 #define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_SHIFT 28U
5777 #define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_CLRMSK 0x000000000FFFFFFFULL
5778 #define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_SHIFT 20U
5779 #define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL
5780 #define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_SHIFT 12U
5781 #define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL
5782 #define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_SHIFT 6U
5783 #define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL
5784 #define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_SHIFT 4U
5785 #define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL
5786 #define ROGUE_CR_MMU_FAULT_STATUS_RNW_SHIFT 3U
5787 #define ROGUE_CR_MMU_FAULT_STATUS_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
5788 #define ROGUE_CR_MMU_FAULT_STATUS_RNW_EN 0x0000000000000008ULL
5789 #define ROGUE_CR_MMU_FAULT_STATUS_TYPE_SHIFT 1U
5790 #define ROGUE_CR_MMU_FAULT_STATUS_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL
5791 #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_SHIFT 0U
5792 #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL
5793 #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_EN 0x0000000000000001ULL
5794 
5795 /* Register ROGUE_CR_MMU_FAULT_STATUS_META */
5796 #define ROGUE_CR_MMU_FAULT_STATUS_META 0xE158U
5797 #define ROGUE_CR_MMU_FAULT_STATUS_META_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5798 #define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT 28U
5799 #define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK 0x000000000FFFFFFFULL
5800 #define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT 20U
5801 #define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL
5802 #define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_SHIFT 12U
5803 #define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL
5804 #define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT 6U
5805 #define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL
5806 #define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT 4U
5807 #define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL
5808 #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_SHIFT 3U
5809 #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
5810 #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_EN 0x0000000000000008ULL
5811 #define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT 1U
5812 #define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL
5813 #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT 0U
5814 #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL
5815 #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_EN 0x0000000000000001ULL
5816 
5817 /* Register ROGUE_CR_SLC3_CTRL_MISC */
5818 #define ROGUE_CR_SLC3_CTRL_MISC 0xE200U
5819 #define ROGUE_CR_SLC3_CTRL_MISC_MASKFULL 0x0000000000000107ULL
5820 #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_SHIFT 8U
5821 #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_CLRMSK 0xFFFFFEFFU
5822 #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_EN 0x00000100U
5823 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 0U
5824 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFF8U
5825 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_LINEAR 0x00000000U
5826 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_IN_PAGE_HASH 0x00000001U
5827 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_FIXED_PVR_HASH 0x00000002U
5828 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SCRAMBLE_PVR_HASH 0x00000003U
5829 #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_WEAVED_HASH 0x00000004U
5830 
5831 /* Register ROGUE_CR_SLC3_SCRAMBLE */
5832 #define ROGUE_CR_SLC3_SCRAMBLE 0xE208U
5833 #define ROGUE_CR_SLC3_SCRAMBLE_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5834 #define ROGUE_CR_SLC3_SCRAMBLE_BITS_SHIFT 0U
5835 #define ROGUE_CR_SLC3_SCRAMBLE_BITS_CLRMSK 0x0000000000000000ULL
5836 
5837 /* Register ROGUE_CR_SLC3_SCRAMBLE2 */
5838 #define ROGUE_CR_SLC3_SCRAMBLE2 0xE210U
5839 #define ROGUE_CR_SLC3_SCRAMBLE2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5840 #define ROGUE_CR_SLC3_SCRAMBLE2_BITS_SHIFT 0U
5841 #define ROGUE_CR_SLC3_SCRAMBLE2_BITS_CLRMSK 0x0000000000000000ULL
5842 
5843 /* Register ROGUE_CR_SLC3_SCRAMBLE3 */
5844 #define ROGUE_CR_SLC3_SCRAMBLE3 0xE218U
5845 #define ROGUE_CR_SLC3_SCRAMBLE3_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5846 #define ROGUE_CR_SLC3_SCRAMBLE3_BITS_SHIFT 0U
5847 #define ROGUE_CR_SLC3_SCRAMBLE3_BITS_CLRMSK 0x0000000000000000ULL
5848 
5849 /* Register ROGUE_CR_SLC3_SCRAMBLE4 */
5850 #define ROGUE_CR_SLC3_SCRAMBLE4 0xE260U
5851 #define ROGUE_CR_SLC3_SCRAMBLE4_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5852 #define ROGUE_CR_SLC3_SCRAMBLE4_BITS_SHIFT 0U
5853 #define ROGUE_CR_SLC3_SCRAMBLE4_BITS_CLRMSK 0x0000000000000000ULL
5854 
5855 /* Register ROGUE_CR_SLC3_STATUS */
5856 #define ROGUE_CR_SLC3_STATUS 0xE220U
5857 #define ROGUE_CR_SLC3_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
5858 #define ROGUE_CR_SLC3_STATUS_WRITES1_SHIFT 48U
5859 #define ROGUE_CR_SLC3_STATUS_WRITES1_CLRMSK 0x0000FFFFFFFFFFFFULL
5860 #define ROGUE_CR_SLC3_STATUS_WRITES0_SHIFT 32U
5861 #define ROGUE_CR_SLC3_STATUS_WRITES0_CLRMSK 0xFFFF0000FFFFFFFFULL
5862 #define ROGUE_CR_SLC3_STATUS_READS1_SHIFT 16U
5863 #define ROGUE_CR_SLC3_STATUS_READS1_CLRMSK 0xFFFFFFFF0000FFFFULL
5864 #define ROGUE_CR_SLC3_STATUS_READS0_SHIFT 0U
5865 #define ROGUE_CR_SLC3_STATUS_READS0_CLRMSK 0xFFFFFFFFFFFF0000ULL
5866 
5867 /* Register ROGUE_CR_SLC3_IDLE */
5868 #define ROGUE_CR_SLC3_IDLE 0xE228U
5869 #define ROGUE_CR_SLC3_IDLE_MASKFULL 0x00000000000FFFFFULL
5870 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_SHIFT 18U
5871 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_CLRMSK 0xFFF3FFFFU
5872 #define ROGUE_CR_SLC3_IDLE_MMU_SHIFT 17U
5873 #define ROGUE_CR_SLC3_IDLE_MMU_CLRMSK 0xFFFDFFFFU
5874 #define ROGUE_CR_SLC3_IDLE_MMU_EN 0x00020000U
5875 #define ROGUE_CR_SLC3_IDLE_RDI_SHIFT 16U
5876 #define ROGUE_CR_SLC3_IDLE_RDI_CLRMSK 0xFFFEFFFFU
5877 #define ROGUE_CR_SLC3_IDLE_RDI_EN 0x00010000U
5878 #define ROGUE_CR_SLC3_IDLE_IMGBV4_SHIFT 12U
5879 #define ROGUE_CR_SLC3_IDLE_IMGBV4_CLRMSK 0xFFFF0FFFU
5880 #define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_SHIFT 4U
5881 #define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_CLRMSK 0xFFFFF00FU
5882 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_SHIFT 2U
5883 #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_CLRMSK 0xFFFFFFF3U
5884 #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_SHIFT 1U
5885 #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_CLRMSK 0xFFFFFFFDU
5886 #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_EN 0x00000002U
5887 #define ROGUE_CR_SLC3_IDLE_XBAR_SHIFT 0U
5888 #define ROGUE_CR_SLC3_IDLE_XBAR_CLRMSK 0xFFFFFFFEU
5889 #define ROGUE_CR_SLC3_IDLE_XBAR_EN 0x00000001U
5890 
5891 /* Register ROGUE_CR_SLC3_FAULT_STOP_STATUS */
5892 #define ROGUE_CR_SLC3_FAULT_STOP_STATUS 0xE248U
5893 #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_MASKFULL 0x0000000000001FFFULL
5894 #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_SHIFT 0U
5895 #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_CLRMSK 0xFFFFE000U
5896 
5897 /* Register ROGUE_CR_VDM_CONTEXT_STORE_MODE */
5898 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE 0xF048U
5899 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MASKFULL 0x0000000000000003ULL
5900 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_SHIFT 0U
5901 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_CLRMSK 0xFFFFFFFCU
5902 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX 0x00000000U
5903 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE 0x00000001U
5904 #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST 0x00000002U
5905 
5906 /* Register ROGUE_CR_CONTEXT_MAPPING0 */
5907 #define ROGUE_CR_CONTEXT_MAPPING0 0xF078U
5908 #define ROGUE_CR_CONTEXT_MAPPING0_MASKFULL 0x00000000FFFFFFFFULL
5909 #define ROGUE_CR_CONTEXT_MAPPING0_2D_SHIFT 24U
5910 #define ROGUE_CR_CONTEXT_MAPPING0_2D_CLRMSK 0x00FFFFFFU
5911 #define ROGUE_CR_CONTEXT_MAPPING0_CDM_SHIFT 16U
5912 #define ROGUE_CR_CONTEXT_MAPPING0_CDM_CLRMSK 0xFF00FFFFU
5913 #define ROGUE_CR_CONTEXT_MAPPING0_3D_SHIFT 8U
5914 #define ROGUE_CR_CONTEXT_MAPPING0_3D_CLRMSK 0xFFFF00FFU
5915 #define ROGUE_CR_CONTEXT_MAPPING0_TA_SHIFT 0U
5916 #define ROGUE_CR_CONTEXT_MAPPING0_TA_CLRMSK 0xFFFFFF00U
5917 
5918 /* Register ROGUE_CR_CONTEXT_MAPPING1 */
5919 #define ROGUE_CR_CONTEXT_MAPPING1 0xF080U
5920 #define ROGUE_CR_CONTEXT_MAPPING1_MASKFULL 0x000000000000FFFFULL
5921 #define ROGUE_CR_CONTEXT_MAPPING1_HOST_SHIFT 8U
5922 #define ROGUE_CR_CONTEXT_MAPPING1_HOST_CLRMSK 0xFFFF00FFU
5923 #define ROGUE_CR_CONTEXT_MAPPING1_TLA_SHIFT 0U
5924 #define ROGUE_CR_CONTEXT_MAPPING1_TLA_CLRMSK 0xFFFFFF00U
5925 
5926 /* Register ROGUE_CR_CONTEXT_MAPPING2 */
5927 #define ROGUE_CR_CONTEXT_MAPPING2 0xF088U
5928 #define ROGUE_CR_CONTEXT_MAPPING2_MASKFULL 0x0000000000FFFFFFULL
5929 #define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_SHIFT 16U
5930 #define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK 0xFF00FFFFU
5931 #define ROGUE_CR_CONTEXT_MAPPING2_TE0_SHIFT 8U
5932 #define ROGUE_CR_CONTEXT_MAPPING2_TE0_CLRMSK 0xFFFF00FFU
5933 #define ROGUE_CR_CONTEXT_MAPPING2_VCE0_SHIFT 0U
5934 #define ROGUE_CR_CONTEXT_MAPPING2_VCE0_CLRMSK 0xFFFFFF00U
5935 
5936 /* Register ROGUE_CR_CONTEXT_MAPPING3 */
5937 #define ROGUE_CR_CONTEXT_MAPPING3 0xF090U
5938 #define ROGUE_CR_CONTEXT_MAPPING3_MASKFULL 0x0000000000FFFFFFULL
5939 #define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_SHIFT 16U
5940 #define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK 0xFF00FFFFU
5941 #define ROGUE_CR_CONTEXT_MAPPING3_TE1_SHIFT 8U
5942 #define ROGUE_CR_CONTEXT_MAPPING3_TE1_CLRMSK 0xFFFF00FFU
5943 #define ROGUE_CR_CONTEXT_MAPPING3_VCE1_SHIFT 0U
5944 #define ROGUE_CR_CONTEXT_MAPPING3_VCE1_CLRMSK 0xFFFFFF00U
5945 
5946 /* Register ROGUE_CR_BIF_JONES_OUTSTANDING_READ */
5947 #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ 0xF098U
5948 #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
5949 #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_SHIFT 0U
5950 #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
5951 
5952 /* Register ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ */
5953 #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ 0xF0A0U
5954 #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
5955 #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_SHIFT 0U
5956 #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
5957 
5958 /* Register ROGUE_CR_BIF_DUST_OUTSTANDING_READ */
5959 #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ 0xF0A8U
5960 #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
5961 #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_SHIFT 0U
5962 #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
5963 
5964 /* Register ROGUE_CR_CONTEXT_MAPPING4 */
5965 #define ROGUE_CR_CONTEXT_MAPPING4 0xF210U
5966 #define ROGUE_CR_CONTEXT_MAPPING4_MASKFULL 0x0000FFFFFFFFFFFFULL
5967 #define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT 40U
5968 #define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_CLRMSK 0xFFFF00FFFFFFFFFFULL
5969 #define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT 32U
5970 #define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_CLRMSK 0xFFFFFF00FFFFFFFFULL
5971 #define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT 24U
5972 #define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_CLRMSK 0xFFFFFFFF00FFFFFFULL
5973 #define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT 16U
5974 #define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_CLRMSK 0xFFFFFFFFFF00FFFFULL
5975 #define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT 8U
5976 #define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_CLRMSK 0xFFFFFFFFFFFF00FFULL
5977 #define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT 0U
5978 #define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_CLRMSK 0xFFFFFFFFFFFFFF00ULL
5979 
5980 /* Register ROGUE_CR_MULTICORE_GPU */
5981 #define ROGUE_CR_MULTICORE_GPU 0xF300U
5982 #define ROGUE_CR_MULTICORE_GPU_MASKFULL 0x000000000000007FULL
5983 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_SHIFT 6U
5984 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_CLRMSK 0xFFFFFFBFU
5985 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_EN 0x00000040U
5986 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_SHIFT 5U
5987 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_CLRMSK 0xFFFFFFDFU
5988 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_EN 0x00000020U
5989 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_SHIFT 4U
5990 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_CLRMSK 0xFFFFFFEFU
5991 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_EN 0x00000010U
5992 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_SHIFT 3U
5993 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_CLRMSK 0xFFFFFFF7U
5994 #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_EN 0x00000008U
5995 #define ROGUE_CR_MULTICORE_GPU_ID_SHIFT 0U
5996 #define ROGUE_CR_MULTICORE_GPU_ID_CLRMSK 0xFFFFFFF8U
5997 
5998 /* Register ROGUE_CR_MULTICORE_SYSTEM */
5999 #define ROGUE_CR_MULTICORE_SYSTEM 0xF308U
6000 #define ROGUE_CR_MULTICORE_SYSTEM_MASKFULL 0x000000000000000FULL
6001 #define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT 0U
6002 #define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_CLRMSK 0xFFFFFFF0U
6003 
6004 /* Register ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON */
6005 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON 0xF310U
6006 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
6007 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6008 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
6009 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6010 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
6011 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6012 #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
6013 
6014 /* Register ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON */
6015 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON 0xF320U
6016 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
6017 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6018 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
6019 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6020 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
6021 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6022 #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
6023 
6024 /* Register ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON */
6025 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON 0xF330U
6026 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
6027 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
6028 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
6029 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
6030 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
6031 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
6032 #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
6033 
6034 /* Register ROGUE_CR_ECC_RAM_ERR_INJ */
6035 #define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U
6036 #define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL
6037 #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U
6038 #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
6039 #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U
6040 #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U
6041 #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U
6042 #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U
6043 #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U
6044 #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
6045 #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U
6046 #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U
6047 #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU
6048 #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U
6049 #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U
6050 #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU
6051 #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U
6052 
6053 /* Register ROGUE_CR_ECC_RAM_INIT_KICK */
6054 #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U
6055 #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL
6056 #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_SHIFT 4U
6057 #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
6058 #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_EN 0x00000010U
6059 #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_SHIFT 3U
6060 #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_CLRMSK 0xFFFFFFF7U
6061 #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_EN 0x00000008U
6062 #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_SHIFT 2U
6063 #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
6064 #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_EN 0x00000004U
6065 #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_SHIFT 1U
6066 #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_CLRMSK 0xFFFFFFFDU
6067 #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_EN 0x00000002U
6068 #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_SHIFT 0U
6069 #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_CLRMSK 0xFFFFFFFEU
6070 #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_EN 0x00000001U
6071 
6072 /* Register ROGUE_CR_ECC_RAM_INIT_DONE */
6073 #define ROGUE_CR_ECC_RAM_INIT_DONE 0xF350U
6074 #define ROGUE_CR_ECC_RAM_INIT_DONE_MASKFULL 0x000000000000001FULL
6075 #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_SHIFT 4U
6076 #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
6077 #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_EN 0x00000010U
6078 #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_SHIFT 3U
6079 #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_CLRMSK 0xFFFFFFF7U
6080 #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_EN 0x00000008U
6081 #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_SHIFT 2U
6082 #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
6083 #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_EN 0x00000004U
6084 #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_SHIFT 1U
6085 #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_CLRMSK 0xFFFFFFFDU
6086 #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_EN 0x00000002U
6087 #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_SHIFT 0U
6088 #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_CLRMSK 0xFFFFFFFEU
6089 #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_EN 0x00000001U
6090 
6091 /* Register ROGUE_CR_SAFETY_EVENT_ENABLE */
6092 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE 0xF390U
6093 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
6094 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6095 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
6096 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
6097 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6098 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
6099 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
6100 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6101 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
6102 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
6103 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
6104 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
6105 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U
6106 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
6107 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
6108 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U
6109 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
6110 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
6111 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U
6112 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6113 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
6114 #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
6115 
6116 /* Register ROGUE_CR_SAFETY_EVENT_STATUS */
6117 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE 0xF398U
6118 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__MASKFULL 0x000000000000007FULL
6119 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6120 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
6121 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
6122 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6123 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
6124 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
6125 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6126 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
6127 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
6128 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_SHIFT 3U
6129 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
6130 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_EN 0x00000008U
6131 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_SHIFT 2U
6132 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
6133 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN 0x00000004U
6134 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_SHIFT 1U
6135 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
6136 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_EN 0x00000002U
6137 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6138 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
6139 #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
6140 
6141 /* Register ROGUE_CR_SAFETY_EVENT_CLEAR */
6142 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE 0xF3A0U
6143 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__MASKFULL 0x000000000000007FULL
6144 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6145 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
6146 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
6147 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6148 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
6149 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
6150 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6151 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
6152 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
6153 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_SHIFT 3U
6154 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
6155 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_EN 0x00000008U
6156 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_SHIFT 2U
6157 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
6158 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_EN 0x00000004U
6159 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_SHIFT 1U
6160 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
6161 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_EN 0x00000002U
6162 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6163 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
6164 #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
6165 
6166 /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */
6167 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U
6168 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
6169 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
6170 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
6171 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
6172 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
6173 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
6174 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
6175 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
6176 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
6177 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
6178 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
6179 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
6180 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U
6181 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
6182 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
6183 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U
6184 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
6185 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
6186 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U
6187 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
6188 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
6189 #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
6190 
6191 /* clang-format on */
6192 
6193 #endif /* PVR_ROGUE_CR_DEFS_H */
6194