1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #ifndef PVR_ROGUE_CR_DEFS_CLIENT_H 5 #define PVR_ROGUE_CR_DEFS_CLIENT_H 6 7 /* clang-format off */ 8 9 /* 10 * This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is 11 * provided in both X & Y axis. 12 * This register needs to be set based on the ISP Samples Per Pixel a core supports. 13 * 14 * When ISP Samples Per Pixel = 1: 15 * 2xmsaa is achieved by enabling Y - TE does AA on Y plane only 16 * 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane 17 * 8xmsaa not supported by XE cores 18 * 19 * When ISP Samples Per Pixel = 2: 20 * 2xmsaa is achieved by enabling X2 - does not affect TE 21 * 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only 22 * 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane 23 * 8xmsaa not supported by XE cores 24 * 25 * When ISP Samples Per Pixel = 4: 26 * 2xmsaa is achieved by enabling X2 - does not affect TE 27 * 4xmsaa is achieved by enabling Y2 and X2 - TE does AA on Y plane only 28 * 8xmsaa not supported by XE cores 29 */ 30 /* Register ROGUE_CR_TE_AA */ 31 #define ROGUE_CR_TE_AA 0x0C00U 32 #define ROGUE_CR_TE_AA_MASKFULL 0x000000000000000Full 33 /* Y2 34 * Indicates 4xmsaa when X2 and Y2 are set to 1. This does not affect TE and is only used within 35 * TPW. 36 */ 37 #define ROGUE_CR_TE_AA_Y2_SHIFT 3 38 #define ROGUE_CR_TE_AA_Y2_CLRMSK 0xFFFFFFF7 39 #define ROGUE_CR_TE_AA_Y2_EN 0x00000008 40 /* Y 41 * Anti-Aliasing in Y Plane Enabled 42 */ 43 #define ROGUE_CR_TE_AA_Y_SHIFT 2 44 #define ROGUE_CR_TE_AA_Y_CLRMSK 0xFFFFFFFB 45 #define ROGUE_CR_TE_AA_Y_EN 0x00000004 46 /* X 47 * Anti-Aliasing in X Plane Enabled 48 */ 49 #define ROGUE_CR_TE_AA_X_SHIFT 1 50 #define ROGUE_CR_TE_AA_X_CLRMSK 0xFFFFFFFD 51 #define ROGUE_CR_TE_AA_X_EN 0x00000002 52 /* X2 53 * 2x Anti-Aliasing Enabled, affects PPP only 54 */ 55 #define ROGUE_CR_TE_AA_X2_SHIFT (0U) 56 #define ROGUE_CR_TE_AA_X2_CLRMSK (0xFFFFFFFEU) 57 #define ROGUE_CR_TE_AA_X2_EN (0x00000001U) 58 59 /* MacroTile Boundaries X Plane */ 60 /* Register ROGUE_CR_TE_MTILE1 */ 61 #define ROGUE_CR_TE_MTILE1 0x0C08 62 #define ROGUE_CR_TE_MTILE1_MASKFULL 0x0000000007FFFFFFull 63 /* X1 default: 0x00000004 64 * X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across 65 * tile 66 */ 67 #define ROGUE_CR_TE_MTILE1_X1_SHIFT 18 68 #define ROGUE_CR_TE_MTILE1_X1_CLRMSK 0xF803FFFF 69 /* X2 default: 0x00000008 70 * X2 MacroTile boundary, left tile X for third(16MT) column of macrotiles - 32 pixels across tile 71 */ 72 #define ROGUE_CR_TE_MTILE1_X2_SHIFT 9U 73 #define ROGUE_CR_TE_MTILE1_X2_CLRMSK 0xFFFC01FF 74 /* X3 default: 0x0000000c 75 * X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile 76 */ 77 #define ROGUE_CR_TE_MTILE1_X3_SHIFT 0 78 #define ROGUE_CR_TE_MTILE1_X3_CLRMSK 0xFFFFFE00 79 80 /* MacroTile Boundaries Y Plane. */ 81 /* Register ROGUE_CR_TE_MTILE2 */ 82 #define ROGUE_CR_TE_MTILE2 0x0C10 83 #define ROGUE_CR_TE_MTILE2_MASKFULL 0x0000000007FFFFFFull 84 /* Y1 default: 0x00000004 85 * X1 MacroTile boundary, ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile 86 * height 87 */ 88 #define ROGUE_CR_TE_MTILE2_Y1_SHIFT 18 89 #define ROGUE_CR_TE_MTILE2_Y1_CLRMSK 0xF803FFFF 90 /* Y2 default: 0x00000008 91 * X2 MacroTile boundary, top tile Y for third(16MT) column of macrotiles - 32 pixels tile height 92 */ 93 #define ROGUE_CR_TE_MTILE2_Y2_SHIFT 9 94 #define ROGUE_CR_TE_MTILE2_Y2_CLRMSK 0xFFFC01FF 95 /* Y3 default: 0x0000000c 96 * X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height 97 */ 98 #define ROGUE_CR_TE_MTILE2_Y3_SHIFT 0 99 #define ROGUE_CR_TE_MTILE2_Y3_CLRMSK 0xFFFFFE00 100 101 /* 102 * In order to perform the tiling operation and generate the display list the maximum screen size 103 * must be configured in terms of the number of tiles in X & Y axis. 104 */ 105 106 /* Register ROGUE_CR_TE_SCREEN */ 107 #define ROGUE_CR_TE_SCREEN 0x0C18U 108 #define ROGUE_CR_TE_SCREEN_MASKFULL 0x00000000001FF1FFull 109 /* YMAX default: 0x00000010 110 * Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size 111 */ 112 #define ROGUE_CR_TE_SCREEN_YMAX_SHIFT 12 113 #define ROGUE_CR_TE_SCREEN_YMAX_CLRMSK 0xFFE00FFF 114 /* XMAX default: 0x00000010 115 * Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size 116 */ 117 #define ROGUE_CR_TE_SCREEN_XMAX_SHIFT 0 118 #define ROGUE_CR_TE_SCREEN_XMAX_CLRMSK 0xFFFFFE00 119 120 /* 121 * In order to perform the tiling operation and generate the display list the maximum screen size 122 * must be configured in terms of the number of pixels in X & Y axis since this may not be the same 123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register. 124 */ 125 /* Register ROGUE_CR_PPP_SCREEN */ 126 #define ROGUE_CR_PPP_SCREEN 0x0C98 127 #define ROGUE_CR_PPP_SCREEN_MASKFULL 0x000000007FFF7FFFull 128 /* PIXYMAX 129 * Screen height in pixels. (16K x 16K max screen size) 130 */ 131 #define ROGUE_CR_PPP_SCREEN_PIXYMAX_SHIFT 16 132 #define ROGUE_CR_PPP_SCREEN_PIXYMAX_CLRMSK 0x8000FFFF 133 /* PIXXMAX 134 * Screen width in pixels.(16K x 16K max screen size) 135 */ 136 #define ROGUE_CR_PPP_SCREEN_PIXXMAX_SHIFT 0 137 #define ROGUE_CR_PPP_SCREEN_PIXXMAX_CLRMSK 0xFFFF8000 138 139 /* Register ROGUE_CR_ISP_MTILE_SIZE */ 140 #define ROGUE_CR_ISP_MTILE_SIZE 0x0F18 141 #define ROGUE_CR_ISP_MTILE_SIZE_MASKFULL 0x0000000003FF03FFull 142 /* X 143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size 144 */ 145 #define ROGUE_CR_ISP_MTILE_SIZE_X_SHIFT 16 146 #define ROGUE_CR_ISP_MTILE_SIZE_X_CLRMSK 0xFC00FFFF 147 #define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSHIFT 0 148 #define ROGUE_CR_ISP_MTILE_SIZE_X_ALIGNSIZE 1 149 /* Y 150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size 151 */ 152 #define ROGUE_CR_ISP_MTILE_SIZE_Y_SHIFT 0 153 #define ROGUE_CR_ISP_MTILE_SIZE_Y_CLRMSK 0xFFFFFC00 154 #define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSHIFT 0 155 #define ROGUE_CR_ISP_MTILE_SIZE_Y_ALIGNSIZE 1 156 157 /* clang-format on */ 158 159 #endif /* PVR_ROGUE_CR_DEFS_CLIENT_H */ 160