1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces 4 * 5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, 6 * Pilo Chambert <pilo.c@wanadoo.fr> 7 * 8 * Thanks to : Anders Torger <torger@ludd.luth.se>, 9 * Henk Hesselink <henk@anda.nl> 10 * for writing the digi96-driver 11 * and RME for all informations. 12 * 13 * **************************************************************************** 14 * 15 * Note #1 "Sek'd models" ................................... martin 2002-12-07 16 * 17 * Identical soundcards by Sek'd were labeled: 18 * RME Digi 32 = Sek'd Prodif 32 19 * RME Digi 32 Pro = Sek'd Prodif 96 20 * RME Digi 32/8 = Sek'd Prodif Gold 21 * 22 * **************************************************************************** 23 * 24 * Note #2 "full duplex mode" ............................... martin 2002-12-07 25 * 26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical 27 * in this mode. Rec data and play data are using the same buffer therefore. At 28 * first you have got the playing bits in the buffer and then (after playing 29 * them) they were overwitten by the captured sound of the CS8412/14. Both 30 * modes (play/record) are running harmonically hand in hand in the same buffer 31 * and you have only one start bit plus one interrupt bit to control this 32 * paired action. 33 * This is opposite to the latter rme96 where playing and capturing is totally 34 * separated and so their full duplex mode is supported by alsa (using two 35 * start bits and two interrupts for two different buffers). 36 * But due to the wrong sequence of playing and capturing ALSA shows no solved 37 * full duplex support for the rme32 at the moment. That's bad, but I'm not 38 * able to solve it. Are you motivated enough to solve this problem now? Your 39 * patch would be welcome! 40 * 41 * **************************************************************************** 42 * 43 * "The story after the long seeking" -- tiwai 44 * 45 * Ok, the situation regarding the full duplex is now improved a bit. 46 * In the fullduplex mode (given by the module parameter), the hardware buffer 47 * is split to halves for read and write directions at the DMA pointer. 48 * That is, the half above the current DMA pointer is used for write, and 49 * the half below is used for read. To mangle this strange behavior, an 50 * software intermediate buffer is introduced. This is, of course, not good 51 * from the viewpoint of the data transfer efficiency. However, this allows 52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. 53 * 54 * **************************************************************************** 55 */ 56 57 58 #include <linux/delay.h> 59 #include <linux/gfp.h> 60 #include <linux/init.h> 61 #include <linux/interrupt.h> 62 #include <linux/pci.h> 63 #include <linux/module.h> 64 #include <linux/io.h> 65 66 #include <sound/core.h> 67 #include <sound/info.h> 68 #include <sound/control.h> 69 #include <sound/pcm.h> 70 #include <sound/pcm_params.h> 71 #include <sound/pcm-indirect.h> 72 #include <sound/asoundef.h> 73 #include <sound/initval.h> 74 75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 78 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; 79 80 module_param_array(index, int, NULL, 0444); 81 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); 82 module_param_array(id, charp, NULL, 0444); 83 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); 84 module_param_array(enable, bool, NULL, 0444); 85 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); 86 module_param_array(fullduplex, bool, NULL, 0444); 87 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); 88 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); 89 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); 90 MODULE_LICENSE("GPL"); 91 92 /* Defines for RME Digi32 series */ 93 #define RME32_SPDIF_NCHANNELS 2 94 95 /* Playback and capture buffer size */ 96 #define RME32_BUFFER_SIZE 0x20000 97 98 /* IO area size */ 99 #define RME32_IO_SIZE 0x30000 100 101 /* IO area offsets */ 102 #define RME32_IO_DATA_BUFFER 0x0 103 #define RME32_IO_CONTROL_REGISTER 0x20000 104 #define RME32_IO_GET_POS 0x20000 105 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 106 #define RME32_IO_RESET_POS 0x20100 107 108 /* Write control register bits */ 109 #define RME32_WCR_START (1 << 0) /* startbit */ 110 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono 111 Setting the whole card to mono 112 doesn't seem to be very useful. 113 A software-solution can handle 114 full-duplex with one direction in 115 stereo and the other way in mono. 116 So, the hardware should work all 117 the time in stereo! */ 118 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ 119 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ 120 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ 121 #define RME32_WCR_FREQ_1 (1 << 5) 122 #define RME32_WCR_INP_0 (1 << 6) /* input switch */ 123 #define RME32_WCR_INP_1 (1 << 7) 124 #define RME32_WCR_RESET (1 << 8) /* Reset address */ 125 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ 126 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ 127 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ 128 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ 129 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ 130 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ 131 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ 132 133 #define RME32_WCR_BITPOS_FREQ_0 4 134 #define RME32_WCR_BITPOS_FREQ_1 5 135 #define RME32_WCR_BITPOS_INP_0 6 136 #define RME32_WCR_BITPOS_INP_1 7 137 138 /* Read control register bits */ 139 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff 140 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ 141 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ 142 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ 143 #define RME32_RCR_FREQ_1 (1 << 28) 144 #define RME32_RCR_FREQ_2 (1 << 29) 145 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ 146 #define RME32_RCR_IRQ (1 << 31) /* interrupt */ 147 148 #define RME32_RCR_BITPOS_F0 27 149 #define RME32_RCR_BITPOS_F1 28 150 #define RME32_RCR_BITPOS_F2 29 151 152 /* Input types */ 153 #define RME32_INPUT_OPTICAL 0 154 #define RME32_INPUT_COAXIAL 1 155 #define RME32_INPUT_INTERNAL 2 156 #define RME32_INPUT_XLR 3 157 158 /* Clock modes */ 159 #define RME32_CLOCKMODE_SLAVE 0 160 #define RME32_CLOCKMODE_MASTER_32 1 161 #define RME32_CLOCKMODE_MASTER_44 2 162 #define RME32_CLOCKMODE_MASTER_48 3 163 164 /* Block sizes in bytes */ 165 #define RME32_BLOCK_SIZE 8192 166 167 /* Software intermediate buffer (max) size */ 168 #define RME32_MID_BUFFER_SIZE (1024*1024) 169 170 /* Hardware revisions */ 171 #define RME32_32_REVISION 192 172 #define RME32_328_REVISION_OLD 100 173 #define RME32_328_REVISION_NEW 101 174 #define RME32_PRO_REVISION_WITH_8412 192 175 #define RME32_PRO_REVISION_WITH_8414 150 176 177 178 struct rme32 { 179 spinlock_t lock; 180 int irq; 181 unsigned long port; 182 void __iomem *iobase; 183 184 u32 wcreg; /* cached write control register value */ 185 u32 wcreg_spdif; /* S/PDIF setup */ 186 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 187 u32 rcreg; /* cached read control register value */ 188 189 u8 rev; /* card revision number */ 190 191 struct snd_pcm_substream *playback_substream; 192 struct snd_pcm_substream *capture_substream; 193 194 int playback_frlog; /* log2 of framesize */ 195 int capture_frlog; 196 197 size_t playback_periodsize; /* in bytes, zero if not used */ 198 size_t capture_periodsize; /* in bytes, zero if not used */ 199 200 unsigned int fullduplex_mode; 201 int running; 202 203 struct snd_pcm_indirect playback_pcm; 204 struct snd_pcm_indirect capture_pcm; 205 206 struct snd_card *card; 207 struct snd_pcm *spdif_pcm; 208 struct snd_pcm *adat_pcm; 209 struct pci_dev *pci; 210 struct snd_kcontrol *spdif_ctl; 211 }; 212 213 static const struct pci_device_id snd_rme32_ids[] = { 214 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, 215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, 216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, 217 {0,} 218 }; 219 220 MODULE_DEVICE_TABLE(pci, snd_rme32_ids); 221 222 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) 223 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) 224 225 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); 226 227 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); 228 229 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); 230 231 static void snd_rme32_proc_init(struct rme32 * rme32); 232 233 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); 234 235 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) 236 { 237 return (readl(rme32->iobase + RME32_IO_GET_POS) 238 & RME32_RCR_AUDIO_ADDR_MASK); 239 } 240 241 /* silence callback for halfduplex mode */ 242 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, 243 int channel, unsigned long pos, 244 unsigned long count) 245 { 246 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 247 248 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); 249 return 0; 250 } 251 252 /* copy callback for halfduplex mode */ 253 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, 254 int channel, unsigned long pos, 255 struct iov_iter *src, unsigned long count) 256 { 257 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 258 259 if (copy_from_iter_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 260 count, src) != count) 261 return -EFAULT; 262 return 0; 263 } 264 265 /* copy callback for halfduplex mode */ 266 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, 267 int channel, unsigned long pos, 268 struct iov_iter *dst, unsigned long count) 269 { 270 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 271 272 if (copy_to_iter_fromio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 273 count, dst) != count) 274 return -EFAULT; 275 return 0; 276 } 277 278 /* 279 * SPDIF I/O capabilities (half-duplex mode) 280 */ 281 static const struct snd_pcm_hardware snd_rme32_spdif_info = { 282 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 283 SNDRV_PCM_INFO_MMAP_VALID | 284 SNDRV_PCM_INFO_INTERLEAVED | 285 SNDRV_PCM_INFO_PAUSE | 286 SNDRV_PCM_INFO_SYNC_START | 287 SNDRV_PCM_INFO_SYNC_APPLPTR), 288 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 289 SNDRV_PCM_FMTBIT_S32_LE), 290 .rates = (SNDRV_PCM_RATE_32000 | 291 SNDRV_PCM_RATE_44100 | 292 SNDRV_PCM_RATE_48000), 293 .rate_min = 32000, 294 .rate_max = 48000, 295 .channels_min = 2, 296 .channels_max = 2, 297 .buffer_bytes_max = RME32_BUFFER_SIZE, 298 .period_bytes_min = RME32_BLOCK_SIZE, 299 .period_bytes_max = RME32_BLOCK_SIZE, 300 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 301 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 302 .fifo_size = 0, 303 }; 304 305 /* 306 * ADAT I/O capabilities (half-duplex mode) 307 */ 308 static const struct snd_pcm_hardware snd_rme32_adat_info = 309 { 310 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 311 SNDRV_PCM_INFO_MMAP_VALID | 312 SNDRV_PCM_INFO_INTERLEAVED | 313 SNDRV_PCM_INFO_PAUSE | 314 SNDRV_PCM_INFO_SYNC_START | 315 SNDRV_PCM_INFO_SYNC_APPLPTR), 316 .formats= SNDRV_PCM_FMTBIT_S16_LE, 317 .rates = (SNDRV_PCM_RATE_44100 | 318 SNDRV_PCM_RATE_48000), 319 .rate_min = 44100, 320 .rate_max = 48000, 321 .channels_min = 8, 322 .channels_max = 8, 323 .buffer_bytes_max = RME32_BUFFER_SIZE, 324 .period_bytes_min = RME32_BLOCK_SIZE, 325 .period_bytes_max = RME32_BLOCK_SIZE, 326 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 327 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 328 .fifo_size = 0, 329 }; 330 331 /* 332 * SPDIF I/O capabilities (full-duplex mode) 333 */ 334 static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { 335 .info = (SNDRV_PCM_INFO_MMAP | 336 SNDRV_PCM_INFO_MMAP_VALID | 337 SNDRV_PCM_INFO_INTERLEAVED | 338 SNDRV_PCM_INFO_PAUSE | 339 SNDRV_PCM_INFO_SYNC_START | 340 SNDRV_PCM_INFO_SYNC_APPLPTR), 341 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 342 SNDRV_PCM_FMTBIT_S32_LE), 343 .rates = (SNDRV_PCM_RATE_32000 | 344 SNDRV_PCM_RATE_44100 | 345 SNDRV_PCM_RATE_48000), 346 .rate_min = 32000, 347 .rate_max = 48000, 348 .channels_min = 2, 349 .channels_max = 2, 350 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 351 .period_bytes_min = RME32_BLOCK_SIZE, 352 .period_bytes_max = RME32_BLOCK_SIZE, 353 .periods_min = 2, 354 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 355 .fifo_size = 0, 356 }; 357 358 /* 359 * ADAT I/O capabilities (full-duplex mode) 360 */ 361 static const struct snd_pcm_hardware snd_rme32_adat_fd_info = 362 { 363 .info = (SNDRV_PCM_INFO_MMAP | 364 SNDRV_PCM_INFO_MMAP_VALID | 365 SNDRV_PCM_INFO_INTERLEAVED | 366 SNDRV_PCM_INFO_PAUSE | 367 SNDRV_PCM_INFO_SYNC_START | 368 SNDRV_PCM_INFO_SYNC_APPLPTR), 369 .formats= SNDRV_PCM_FMTBIT_S16_LE, 370 .rates = (SNDRV_PCM_RATE_44100 | 371 SNDRV_PCM_RATE_48000), 372 .rate_min = 44100, 373 .rate_max = 48000, 374 .channels_min = 8, 375 .channels_max = 8, 376 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 377 .period_bytes_min = RME32_BLOCK_SIZE, 378 .period_bytes_max = RME32_BLOCK_SIZE, 379 .periods_min = 2, 380 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 381 .fifo_size = 0, 382 }; 383 384 static void snd_rme32_reset_dac(struct rme32 *rme32) 385 { 386 writel(rme32->wcreg | RME32_WCR_PD, 387 rme32->iobase + RME32_IO_CONTROL_REGISTER); 388 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 389 } 390 391 static int snd_rme32_playback_getrate(struct rme32 * rme32) 392 { 393 int rate; 394 395 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 396 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 397 switch (rate) { 398 case 1: 399 rate = 32000; 400 break; 401 case 2: 402 rate = 44100; 403 break; 404 case 3: 405 rate = 48000; 406 break; 407 default: 408 return -1; 409 } 410 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; 411 } 412 413 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) 414 { 415 int n; 416 417 *is_adat = 0; 418 if (rme32->rcreg & RME32_RCR_LOCK) { 419 /* ADAT rate */ 420 *is_adat = 1; 421 } 422 if (rme32->rcreg & RME32_RCR_ERF) { 423 return -1; 424 } 425 426 /* S/PDIF rate */ 427 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + 428 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + 429 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); 430 431 if (RME32_PRO_WITH_8414(rme32)) 432 switch (n) { /* supporting the CS8414 */ 433 case 0: 434 case 1: 435 case 2: 436 return -1; 437 case 3: 438 return 96000; 439 case 4: 440 return 88200; 441 case 5: 442 return 48000; 443 case 6: 444 return 44100; 445 case 7: 446 return 32000; 447 default: 448 return -1; 449 } 450 else 451 switch (n) { /* supporting the CS8412 */ 452 case 0: 453 return -1; 454 case 1: 455 return 48000; 456 case 2: 457 return 44100; 458 case 3: 459 return 32000; 460 case 4: 461 return 48000; 462 case 5: 463 return 44100; 464 case 6: 465 return 44056; 466 case 7: 467 return 32000; 468 default: 469 break; 470 } 471 return -1; 472 } 473 474 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) 475 { 476 int ds; 477 478 ds = rme32->wcreg & RME32_WCR_DS_BM; 479 switch (rate) { 480 case 32000: 481 rme32->wcreg &= ~RME32_WCR_DS_BM; 482 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 483 ~RME32_WCR_FREQ_1; 484 break; 485 case 44100: 486 rme32->wcreg &= ~RME32_WCR_DS_BM; 487 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 488 ~RME32_WCR_FREQ_0; 489 break; 490 case 48000: 491 rme32->wcreg &= ~RME32_WCR_DS_BM; 492 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 493 RME32_WCR_FREQ_1; 494 break; 495 case 64000: 496 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 497 return -EINVAL; 498 rme32->wcreg |= RME32_WCR_DS_BM; 499 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 500 ~RME32_WCR_FREQ_1; 501 break; 502 case 88200: 503 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 504 return -EINVAL; 505 rme32->wcreg |= RME32_WCR_DS_BM; 506 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 507 ~RME32_WCR_FREQ_0; 508 break; 509 case 96000: 510 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 511 return -EINVAL; 512 rme32->wcreg |= RME32_WCR_DS_BM; 513 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 514 RME32_WCR_FREQ_1; 515 break; 516 default: 517 return -EINVAL; 518 } 519 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || 520 (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) 521 { 522 /* change to/from double-speed: reset the DAC (if available) */ 523 snd_rme32_reset_dac(rme32); 524 } else { 525 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 526 } 527 return 0; 528 } 529 530 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) 531 { 532 switch (mode) { 533 case RME32_CLOCKMODE_SLAVE: 534 /* AutoSync */ 535 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 536 ~RME32_WCR_FREQ_1; 537 break; 538 case RME32_CLOCKMODE_MASTER_32: 539 /* Internal 32.0kHz */ 540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 541 ~RME32_WCR_FREQ_1; 542 break; 543 case RME32_CLOCKMODE_MASTER_44: 544 /* Internal 44.1kHz */ 545 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 546 RME32_WCR_FREQ_1; 547 break; 548 case RME32_CLOCKMODE_MASTER_48: 549 /* Internal 48.0kHz */ 550 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 551 RME32_WCR_FREQ_1; 552 break; 553 default: 554 return -EINVAL; 555 } 556 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 557 return 0; 558 } 559 560 static int snd_rme32_getclockmode(struct rme32 * rme32) 561 { 562 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 563 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 564 } 565 566 static int snd_rme32_setinputtype(struct rme32 * rme32, int type) 567 { 568 switch (type) { 569 case RME32_INPUT_OPTICAL: 570 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 571 ~RME32_WCR_INP_1; 572 break; 573 case RME32_INPUT_COAXIAL: 574 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 575 ~RME32_WCR_INP_1; 576 break; 577 case RME32_INPUT_INTERNAL: 578 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 579 RME32_WCR_INP_1; 580 break; 581 case RME32_INPUT_XLR: 582 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 583 RME32_WCR_INP_1; 584 break; 585 default: 586 return -EINVAL; 587 } 588 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 589 return 0; 590 } 591 592 static int snd_rme32_getinputtype(struct rme32 * rme32) 593 { 594 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + 595 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); 596 } 597 598 static void 599 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) 600 { 601 int frlog; 602 603 if (n_channels == 2) { 604 frlog = 1; 605 } else { 606 /* assume 8 channels */ 607 frlog = 3; 608 } 609 if (is_playback) { 610 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 611 rme32->playback_frlog = frlog; 612 } else { 613 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 614 rme32->capture_frlog = frlog; 615 } 616 } 617 618 static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) 619 { 620 switch (format) { 621 case SNDRV_PCM_FORMAT_S16_LE: 622 rme32->wcreg &= ~RME32_WCR_MODE24; 623 break; 624 case SNDRV_PCM_FORMAT_S32_LE: 625 rme32->wcreg |= RME32_WCR_MODE24; 626 break; 627 default: 628 return -EINVAL; 629 } 630 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 631 return 0; 632 } 633 634 static int 635 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, 636 struct snd_pcm_hw_params *params) 637 { 638 int err, rate, dummy; 639 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 640 struct snd_pcm_runtime *runtime = substream->runtime; 641 642 if (!rme32->fullduplex_mode) { 643 runtime->dma_area = (void __force *)(rme32->iobase + 644 RME32_IO_DATA_BUFFER); 645 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 646 runtime->dma_bytes = RME32_BUFFER_SIZE; 647 } 648 649 guard(spinlock_irq)(&rme32->lock); 650 rate = 0; 651 if (rme32->rcreg & RME32_RCR_KMODE) 652 rate = snd_rme32_capture_getrate(rme32, &dummy); 653 if (rate > 0) { 654 /* AutoSync */ 655 if ((int)params_rate(params) != rate) 656 return -EIO; 657 } else { 658 err = snd_rme32_playback_setrate(rme32, params_rate(params)); 659 if (err < 0) 660 return err; 661 } 662 err = snd_rme32_setformat(rme32, params_format(params)); 663 if (err < 0) 664 return err; 665 666 snd_rme32_setframelog(rme32, params_channels(params), 1); 667 if (rme32->capture_periodsize != 0) { 668 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) 669 return -EBUSY; 670 } 671 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; 672 /* S/PDIF setup */ 673 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { 674 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 675 rme32->wcreg |= rme32->wcreg_spdif_stream; 676 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 677 } 678 679 return 0; 680 } 681 682 static int 683 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, 684 struct snd_pcm_hw_params *params) 685 { 686 int err, isadat, rate; 687 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 688 struct snd_pcm_runtime *runtime = substream->runtime; 689 690 if (!rme32->fullduplex_mode) { 691 runtime->dma_area = (void __force *)rme32->iobase + 692 RME32_IO_DATA_BUFFER; 693 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 694 runtime->dma_bytes = RME32_BUFFER_SIZE; 695 } 696 697 guard(spinlock_irq)(&rme32->lock); 698 /* enable AutoSync for record-preparing */ 699 rme32->wcreg |= RME32_WCR_AUTOSYNC; 700 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 701 702 err = snd_rme32_setformat(rme32, params_format(params)); 703 if (err < 0) 704 return err; 705 err = snd_rme32_playback_setrate(rme32, params_rate(params)); 706 if (err < 0) 707 return err; 708 rate = snd_rme32_capture_getrate(rme32, &isadat); 709 if (rate > 0) { 710 if ((int)params_rate(params) != rate) 711 return -EIO; 712 if ((isadat && runtime->hw.channels_min == 2) || 713 (!isadat && runtime->hw.channels_min == 8)) 714 return -EIO; 715 } 716 /* AutoSync off for recording */ 717 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; 718 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 719 720 snd_rme32_setframelog(rme32, params_channels(params), 0); 721 if (rme32->playback_periodsize != 0) { 722 if (params_period_size(params) << rme32->capture_frlog != 723 rme32->playback_periodsize) 724 return -EBUSY; 725 } 726 rme32->capture_periodsize = 727 params_period_size(params) << rme32->capture_frlog; 728 729 return 0; 730 } 731 732 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) 733 { 734 if (!from_pause) { 735 writel(0, rme32->iobase + RME32_IO_RESET_POS); 736 } 737 738 rme32->wcreg |= RME32_WCR_START; 739 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 740 } 741 742 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) 743 { 744 /* 745 * Check if there is an unconfirmed IRQ, if so confirm it, or else 746 * the hardware will not stop generating interrupts 747 */ 748 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 749 if (rme32->rcreg & RME32_RCR_IRQ) { 750 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 751 } 752 rme32->wcreg &= ~RME32_WCR_START; 753 if (rme32->wcreg & RME32_WCR_SEL) 754 rme32->wcreg |= RME32_WCR_MUTE; 755 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 756 if (! to_pause) 757 writel(0, rme32->iobase + RME32_IO_RESET_POS); 758 } 759 760 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) 761 { 762 struct rme32 *rme32 = (struct rme32 *) dev_id; 763 764 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 765 if (!(rme32->rcreg & RME32_RCR_IRQ)) { 766 return IRQ_NONE; 767 } else { 768 if (rme32->capture_substream) { 769 snd_pcm_period_elapsed(rme32->capture_substream); 770 } 771 if (rme32->playback_substream) { 772 snd_pcm_period_elapsed(rme32->playback_substream); 773 } 774 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 775 } 776 return IRQ_HANDLED; 777 } 778 779 static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; 780 781 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 782 .count = ARRAY_SIZE(period_bytes), 783 .list = period_bytes, 784 .mask = 0 785 }; 786 787 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) 788 { 789 if (! rme32->fullduplex_mode) { 790 snd_pcm_hw_constraint_single(runtime, 791 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 792 RME32_BUFFER_SIZE); 793 snd_pcm_hw_constraint_list(runtime, 0, 794 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 795 &hw_constraints_period_bytes); 796 } 797 } 798 799 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) 800 { 801 int rate, dummy; 802 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 803 struct snd_pcm_runtime *runtime = substream->runtime; 804 805 snd_pcm_set_sync(substream); 806 807 scoped_guard(spinlock_irq, &rme32->lock) { 808 if (rme32->playback_substream != NULL) 809 return -EBUSY; 810 rme32->wcreg &= ~RME32_WCR_ADAT; 811 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 812 rme32->playback_substream = substream; 813 } 814 815 if (rme32->fullduplex_mode) 816 runtime->hw = snd_rme32_spdif_fd_info; 817 else 818 runtime->hw = snd_rme32_spdif_info; 819 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { 820 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 821 runtime->hw.rate_max = 96000; 822 } 823 rate = 0; 824 if (rme32->rcreg & RME32_RCR_KMODE) 825 rate = snd_rme32_capture_getrate(rme32, &dummy); 826 if (rate > 0) { 827 /* AutoSync */ 828 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 829 runtime->hw.rate_min = rate; 830 runtime->hw.rate_max = rate; 831 } 832 833 snd_rme32_set_buffer_constraint(rme32, runtime); 834 835 rme32->wcreg_spdif_stream = rme32->wcreg_spdif; 836 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 837 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 838 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); 839 return 0; 840 } 841 842 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) 843 { 844 int isadat, rate; 845 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 846 struct snd_pcm_runtime *runtime = substream->runtime; 847 848 snd_pcm_set_sync(substream); 849 850 scoped_guard(spinlock_irq, &rme32->lock) { 851 if (rme32->capture_substream != NULL) 852 return -EBUSY; 853 rme32->capture_substream = substream; 854 } 855 856 if (rme32->fullduplex_mode) 857 runtime->hw = snd_rme32_spdif_fd_info; 858 else 859 runtime->hw = snd_rme32_spdif_info; 860 if (RME32_PRO_WITH_8414(rme32)) { 861 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 862 runtime->hw.rate_max = 96000; 863 } 864 rate = snd_rme32_capture_getrate(rme32, &isadat); 865 if (rate > 0) { 866 if (isadat) { 867 return -EIO; 868 } 869 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 870 runtime->hw.rate_min = rate; 871 runtime->hw.rate_max = rate; 872 } 873 874 snd_rme32_set_buffer_constraint(rme32, runtime); 875 876 return 0; 877 } 878 879 static int 880 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) 881 { 882 int rate, dummy; 883 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 884 struct snd_pcm_runtime *runtime = substream->runtime; 885 886 snd_pcm_set_sync(substream); 887 888 scoped_guard(spinlock_irq, &rme32->lock) { 889 if (rme32->playback_substream != NULL) 890 return -EBUSY; 891 rme32->wcreg |= RME32_WCR_ADAT; 892 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 893 rme32->playback_substream = substream; 894 } 895 896 if (rme32->fullduplex_mode) 897 runtime->hw = snd_rme32_adat_fd_info; 898 else 899 runtime->hw = snd_rme32_adat_info; 900 rate = 0; 901 if (rme32->rcreg & RME32_RCR_KMODE) 902 rate = snd_rme32_capture_getrate(rme32, &dummy); 903 if (rate > 0) { 904 /* AutoSync */ 905 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 906 runtime->hw.rate_min = rate; 907 runtime->hw.rate_max = rate; 908 } 909 910 snd_rme32_set_buffer_constraint(rme32, runtime); 911 return 0; 912 } 913 914 static int 915 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) 916 { 917 int isadat, rate; 918 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 919 struct snd_pcm_runtime *runtime = substream->runtime; 920 921 if (rme32->fullduplex_mode) 922 runtime->hw = snd_rme32_adat_fd_info; 923 else 924 runtime->hw = snd_rme32_adat_info; 925 rate = snd_rme32_capture_getrate(rme32, &isadat); 926 if (rate > 0) { 927 if (!isadat) { 928 return -EIO; 929 } 930 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 931 runtime->hw.rate_min = rate; 932 runtime->hw.rate_max = rate; 933 } 934 935 snd_pcm_set_sync(substream); 936 937 scoped_guard(spinlock_irq, &rme32->lock) { 938 if (rme32->capture_substream != NULL) 939 return -EBUSY; 940 rme32->capture_substream = substream; 941 } 942 943 snd_rme32_set_buffer_constraint(rme32, runtime); 944 return 0; 945 } 946 947 static int snd_rme32_playback_close(struct snd_pcm_substream *substream) 948 { 949 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 950 int spdif = 0; 951 952 scoped_guard(spinlock_irq, &rme32->lock) { 953 rme32->playback_substream = NULL; 954 rme32->playback_periodsize = 0; 955 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; 956 } 957 if (spdif) { 958 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 959 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 960 SNDRV_CTL_EVENT_MASK_INFO, 961 &rme32->spdif_ctl->id); 962 } 963 return 0; 964 } 965 966 static int snd_rme32_capture_close(struct snd_pcm_substream *substream) 967 { 968 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 969 970 guard(spinlock_irq)(&rme32->lock); 971 rme32->capture_substream = NULL; 972 rme32->capture_periodsize = 0; 973 return 0; 974 } 975 976 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) 977 { 978 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 979 980 guard(spinlock_irq)(&rme32->lock); 981 if (rme32->fullduplex_mode) { 982 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); 983 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 984 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 985 } else { 986 writel(0, rme32->iobase + RME32_IO_RESET_POS); 987 } 988 if (rme32->wcreg & RME32_WCR_SEL) 989 rme32->wcreg &= ~RME32_WCR_MUTE; 990 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 991 return 0; 992 } 993 994 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) 995 { 996 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 997 998 guard(spinlock_irq)(&rme32->lock); 999 if (rme32->fullduplex_mode) { 1000 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); 1001 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1002 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; 1003 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1004 } else { 1005 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1006 } 1007 return 0; 1008 } 1009 1010 static int 1011 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1012 { 1013 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1014 struct snd_pcm_substream *s; 1015 1016 guard(spinlock)(&rme32->lock); 1017 snd_pcm_group_for_each_entry(s, substream) { 1018 if (s != rme32->playback_substream && 1019 s != rme32->capture_substream) 1020 continue; 1021 switch (cmd) { 1022 case SNDRV_PCM_TRIGGER_START: 1023 rme32->running |= (1 << s->stream); 1024 if (rme32->fullduplex_mode) { 1025 /* remember the current DMA position */ 1026 if (s == rme32->playback_substream) { 1027 rme32->playback_pcm.hw_io = 1028 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1029 } else { 1030 rme32->capture_pcm.hw_io = 1031 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1032 } 1033 } 1034 break; 1035 case SNDRV_PCM_TRIGGER_STOP: 1036 rme32->running &= ~(1 << s->stream); 1037 break; 1038 } 1039 snd_pcm_trigger_done(s, substream); 1040 } 1041 1042 switch (cmd) { 1043 case SNDRV_PCM_TRIGGER_START: 1044 if (rme32->running && ! RME32_ISWORKING(rme32)) 1045 snd_rme32_pcm_start(rme32, 0); 1046 break; 1047 case SNDRV_PCM_TRIGGER_STOP: 1048 if (! rme32->running && RME32_ISWORKING(rme32)) 1049 snd_rme32_pcm_stop(rme32, 0); 1050 break; 1051 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1052 if (rme32->running && RME32_ISWORKING(rme32)) 1053 snd_rme32_pcm_stop(rme32, 1); 1054 break; 1055 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1056 if (rme32->running && ! RME32_ISWORKING(rme32)) 1057 snd_rme32_pcm_start(rme32, 1); 1058 break; 1059 } 1060 return 0; 1061 } 1062 1063 /* pointer callback for halfduplex mode */ 1064 static snd_pcm_uframes_t 1065 snd_rme32_playback_pointer(struct snd_pcm_substream *substream) 1066 { 1067 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1068 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; 1069 } 1070 1071 static snd_pcm_uframes_t 1072 snd_rme32_capture_pointer(struct snd_pcm_substream *substream) 1073 { 1074 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1075 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; 1076 } 1077 1078 1079 /* ack and pointer callbacks for fullduplex mode */ 1080 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, 1081 struct snd_pcm_indirect *rec, size_t bytes) 1082 { 1083 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1084 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1085 substream->runtime->dma_area + rec->sw_data, bytes); 1086 } 1087 1088 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) 1089 { 1090 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1091 struct snd_pcm_indirect *rec, *cprec; 1092 1093 rec = &rme32->playback_pcm; 1094 cprec = &rme32->capture_pcm; 1095 scoped_guard(spinlock, &rme32->lock) { 1096 rec->hw_queue_size = RME32_BUFFER_SIZE; 1097 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) 1098 rec->hw_queue_size -= cprec->hw_ready; 1099 } 1100 return snd_pcm_indirect_playback_transfer(substream, rec, 1101 snd_rme32_pb_trans_copy); 1102 } 1103 1104 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, 1105 struct snd_pcm_indirect *rec, size_t bytes) 1106 { 1107 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1108 memcpy_fromio(substream->runtime->dma_area + rec->sw_data, 1109 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1110 bytes); 1111 } 1112 1113 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) 1114 { 1115 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1116 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, 1117 snd_rme32_cp_trans_copy); 1118 } 1119 1120 static snd_pcm_uframes_t 1121 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) 1122 { 1123 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1124 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, 1125 snd_rme32_pcm_byteptr(rme32)); 1126 } 1127 1128 static snd_pcm_uframes_t 1129 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) 1130 { 1131 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1132 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, 1133 snd_rme32_pcm_byteptr(rme32)); 1134 } 1135 1136 /* for halfduplex mode */ 1137 static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { 1138 .open = snd_rme32_playback_spdif_open, 1139 .close = snd_rme32_playback_close, 1140 .hw_params = snd_rme32_playback_hw_params, 1141 .prepare = snd_rme32_playback_prepare, 1142 .trigger = snd_rme32_pcm_trigger, 1143 .pointer = snd_rme32_playback_pointer, 1144 .copy = snd_rme32_playback_copy, 1145 .fill_silence = snd_rme32_playback_silence, 1146 .mmap = snd_pcm_lib_mmap_iomem, 1147 }; 1148 1149 static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { 1150 .open = snd_rme32_capture_spdif_open, 1151 .close = snd_rme32_capture_close, 1152 .hw_params = snd_rme32_capture_hw_params, 1153 .prepare = snd_rme32_capture_prepare, 1154 .trigger = snd_rme32_pcm_trigger, 1155 .pointer = snd_rme32_capture_pointer, 1156 .copy = snd_rme32_capture_copy, 1157 .mmap = snd_pcm_lib_mmap_iomem, 1158 }; 1159 1160 static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { 1161 .open = snd_rme32_playback_adat_open, 1162 .close = snd_rme32_playback_close, 1163 .hw_params = snd_rme32_playback_hw_params, 1164 .prepare = snd_rme32_playback_prepare, 1165 .trigger = snd_rme32_pcm_trigger, 1166 .pointer = snd_rme32_playback_pointer, 1167 .copy = snd_rme32_playback_copy, 1168 .fill_silence = snd_rme32_playback_silence, 1169 .mmap = snd_pcm_lib_mmap_iomem, 1170 }; 1171 1172 static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { 1173 .open = snd_rme32_capture_adat_open, 1174 .close = snd_rme32_capture_close, 1175 .hw_params = snd_rme32_capture_hw_params, 1176 .prepare = snd_rme32_capture_prepare, 1177 .trigger = snd_rme32_pcm_trigger, 1178 .pointer = snd_rme32_capture_pointer, 1179 .copy = snd_rme32_capture_copy, 1180 .mmap = snd_pcm_lib_mmap_iomem, 1181 }; 1182 1183 /* for fullduplex mode */ 1184 static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { 1185 .open = snd_rme32_playback_spdif_open, 1186 .close = snd_rme32_playback_close, 1187 .hw_params = snd_rme32_playback_hw_params, 1188 .prepare = snd_rme32_playback_prepare, 1189 .trigger = snd_rme32_pcm_trigger, 1190 .pointer = snd_rme32_playback_fd_pointer, 1191 .ack = snd_rme32_playback_fd_ack, 1192 }; 1193 1194 static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { 1195 .open = snd_rme32_capture_spdif_open, 1196 .close = snd_rme32_capture_close, 1197 .hw_params = snd_rme32_capture_hw_params, 1198 .prepare = snd_rme32_capture_prepare, 1199 .trigger = snd_rme32_pcm_trigger, 1200 .pointer = snd_rme32_capture_fd_pointer, 1201 .ack = snd_rme32_capture_fd_ack, 1202 }; 1203 1204 static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { 1205 .open = snd_rme32_playback_adat_open, 1206 .close = snd_rme32_playback_close, 1207 .hw_params = snd_rme32_playback_hw_params, 1208 .prepare = snd_rme32_playback_prepare, 1209 .trigger = snd_rme32_pcm_trigger, 1210 .pointer = snd_rme32_playback_fd_pointer, 1211 .ack = snd_rme32_playback_fd_ack, 1212 }; 1213 1214 static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { 1215 .open = snd_rme32_capture_adat_open, 1216 .close = snd_rme32_capture_close, 1217 .hw_params = snd_rme32_capture_hw_params, 1218 .prepare = snd_rme32_capture_prepare, 1219 .trigger = snd_rme32_pcm_trigger, 1220 .pointer = snd_rme32_capture_fd_pointer, 1221 .ack = snd_rme32_capture_fd_ack, 1222 }; 1223 1224 static void snd_rme32_free(struct rme32 *rme32) 1225 { 1226 if (rme32->irq >= 0) 1227 snd_rme32_pcm_stop(rme32, 0); 1228 } 1229 1230 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) 1231 { 1232 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1233 rme32->spdif_pcm = NULL; 1234 } 1235 1236 static void 1237 snd_rme32_free_adat_pcm(struct snd_pcm *pcm) 1238 { 1239 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1240 rme32->adat_pcm = NULL; 1241 } 1242 1243 static int snd_rme32_create(struct rme32 *rme32) 1244 { 1245 struct pci_dev *pci = rme32->pci; 1246 int err; 1247 1248 rme32->irq = -1; 1249 spin_lock_init(&rme32->lock); 1250 1251 err = pcim_enable_device(pci); 1252 if (err < 0) 1253 return err; 1254 1255 err = pcim_request_all_regions(pci, "RME32"); 1256 if (err < 0) 1257 return err; 1258 rme32->port = pci_resource_start(rme32->pci, 0); 1259 1260 rme32->iobase = devm_ioremap(&pci->dev, rme32->port, RME32_IO_SIZE); 1261 if (!rme32->iobase) { 1262 dev_err(rme32->card->dev, 1263 "unable to remap memory region 0x%lx-0x%lx\n", 1264 rme32->port, rme32->port + RME32_IO_SIZE - 1); 1265 return -ENOMEM; 1266 } 1267 1268 if (devm_request_irq(&pci->dev, pci->irq, snd_rme32_interrupt, 1269 IRQF_SHARED, KBUILD_MODNAME, rme32)) { 1270 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); 1271 return -EBUSY; 1272 } 1273 rme32->irq = pci->irq; 1274 rme32->card->sync_irq = rme32->irq; 1275 1276 /* read the card's revision number */ 1277 pci_read_config_byte(pci, 8, &rme32->rev); 1278 1279 /* set up ALSA pcm device for S/PDIF */ 1280 err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm); 1281 if (err < 0) 1282 return err; 1283 rme32->spdif_pcm->private_data = rme32; 1284 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; 1285 strscpy(rme32->spdif_pcm->name, "Digi32 IEC958"); 1286 if (rme32->fullduplex_mode) { 1287 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1288 &snd_rme32_playback_spdif_fd_ops); 1289 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1290 &snd_rme32_capture_spdif_fd_ops); 1291 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1292 NULL, 0, RME32_MID_BUFFER_SIZE); 1293 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1294 } else { 1295 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1296 &snd_rme32_playback_spdif_ops); 1297 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1298 &snd_rme32_capture_spdif_ops); 1299 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1300 } 1301 1302 /* set up ALSA pcm device for ADAT */ 1303 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || 1304 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { 1305 /* ADAT is not available on DIGI32 and DIGI32 Pro */ 1306 rme32->adat_pcm = NULL; 1307 } 1308 else { 1309 err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, 1310 1, 1, &rme32->adat_pcm); 1311 if (err < 0) 1312 return err; 1313 rme32->adat_pcm->private_data = rme32; 1314 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; 1315 strscpy(rme32->adat_pcm->name, "Digi32 ADAT"); 1316 if (rme32->fullduplex_mode) { 1317 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1318 &snd_rme32_playback_adat_fd_ops); 1319 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1320 &snd_rme32_capture_adat_fd_ops); 1321 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1322 NULL, 1323 0, RME32_MID_BUFFER_SIZE); 1324 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1325 } else { 1326 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1327 &snd_rme32_playback_adat_ops); 1328 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1329 &snd_rme32_capture_adat_ops); 1330 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1331 } 1332 } 1333 1334 1335 rme32->playback_periodsize = 0; 1336 rme32->capture_periodsize = 0; 1337 1338 /* make sure playback/capture is stopped, if by some reason active */ 1339 snd_rme32_pcm_stop(rme32, 0); 1340 1341 /* reset DAC */ 1342 snd_rme32_reset_dac(rme32); 1343 1344 /* reset buffer pointer */ 1345 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1346 1347 /* set default values in registers */ 1348 rme32->wcreg = RME32_WCR_SEL | /* normal playback */ 1349 RME32_WCR_INP_0 | /* input select */ 1350 RME32_WCR_MUTE; /* muting on */ 1351 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1352 1353 1354 /* init switch interface */ 1355 err = snd_rme32_create_switches(rme32->card, rme32); 1356 if (err < 0) 1357 return err; 1358 1359 /* init proc interface */ 1360 snd_rme32_proc_init(rme32); 1361 1362 rme32->capture_substream = NULL; 1363 rme32->playback_substream = NULL; 1364 1365 return 0; 1366 } 1367 1368 /* 1369 * proc interface 1370 */ 1371 1372 static void 1373 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) 1374 { 1375 int n; 1376 struct rme32 *rme32 = (struct rme32 *) entry->private_data; 1377 1378 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 1379 1380 snd_iprintf(buffer, rme32->card->longname); 1381 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); 1382 1383 snd_iprintf(buffer, "\nGeneral settings\n"); 1384 if (rme32->fullduplex_mode) 1385 snd_iprintf(buffer, " Full-duplex mode\n"); 1386 else 1387 snd_iprintf(buffer, " Half-duplex mode\n"); 1388 if (RME32_PRO_WITH_8414(rme32)) { 1389 snd_iprintf(buffer, " receiver: CS8414\n"); 1390 } else { 1391 snd_iprintf(buffer, " receiver: CS8412\n"); 1392 } 1393 if (rme32->wcreg & RME32_WCR_MODE24) { 1394 snd_iprintf(buffer, " format: 24 bit"); 1395 } else { 1396 snd_iprintf(buffer, " format: 16 bit"); 1397 } 1398 if (rme32->wcreg & RME32_WCR_MONO) { 1399 snd_iprintf(buffer, ", Mono\n"); 1400 } else { 1401 snd_iprintf(buffer, ", Stereo\n"); 1402 } 1403 1404 snd_iprintf(buffer, "\nInput settings\n"); 1405 switch (snd_rme32_getinputtype(rme32)) { 1406 case RME32_INPUT_OPTICAL: 1407 snd_iprintf(buffer, " input: optical"); 1408 break; 1409 case RME32_INPUT_COAXIAL: 1410 snd_iprintf(buffer, " input: coaxial"); 1411 break; 1412 case RME32_INPUT_INTERNAL: 1413 snd_iprintf(buffer, " input: internal"); 1414 break; 1415 case RME32_INPUT_XLR: 1416 snd_iprintf(buffer, " input: XLR"); 1417 break; 1418 } 1419 if (snd_rme32_capture_getrate(rme32, &n) < 0) { 1420 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1421 } else { 1422 if (n) { 1423 snd_iprintf(buffer, " (8 channels)\n"); 1424 } else { 1425 snd_iprintf(buffer, " (2 channels)\n"); 1426 } 1427 snd_iprintf(buffer, " sample rate: %d Hz\n", 1428 snd_rme32_capture_getrate(rme32, &n)); 1429 } 1430 1431 snd_iprintf(buffer, "\nOutput settings\n"); 1432 if (rme32->wcreg & RME32_WCR_SEL) { 1433 snd_iprintf(buffer, " output signal: normal playback"); 1434 } else { 1435 snd_iprintf(buffer, " output signal: same as input"); 1436 } 1437 if (rme32->wcreg & RME32_WCR_MUTE) { 1438 snd_iprintf(buffer, " (muted)\n"); 1439 } else { 1440 snd_iprintf(buffer, "\n"); 1441 } 1442 1443 /* master output frequency */ 1444 if (! 1445 ((!(rme32->wcreg & RME32_WCR_FREQ_0)) 1446 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { 1447 snd_iprintf(buffer, " sample rate: %d Hz\n", 1448 snd_rme32_playback_getrate(rme32)); 1449 } 1450 if (rme32->rcreg & RME32_RCR_KMODE) { 1451 snd_iprintf(buffer, " sample clock source: AutoSync\n"); 1452 } else { 1453 snd_iprintf(buffer, " sample clock source: Internal\n"); 1454 } 1455 if (rme32->wcreg & RME32_WCR_PRO) { 1456 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1457 } else { 1458 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1459 } 1460 if (rme32->wcreg & RME32_WCR_EMP) { 1461 snd_iprintf(buffer, " emphasis: on\n"); 1462 } else { 1463 snd_iprintf(buffer, " emphasis: off\n"); 1464 } 1465 } 1466 1467 static void snd_rme32_proc_init(struct rme32 *rme32) 1468 { 1469 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); 1470 } 1471 1472 /* 1473 * control interface 1474 */ 1475 1476 #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info 1477 1478 static int 1479 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, 1480 struct snd_ctl_elem_value *ucontrol) 1481 { 1482 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1483 1484 guard(spinlock_irq)(&rme32->lock); 1485 ucontrol->value.integer.value[0] = 1486 rme32->wcreg & RME32_WCR_SEL ? 0 : 1; 1487 return 0; 1488 } 1489 static int 1490 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, 1491 struct snd_ctl_elem_value *ucontrol) 1492 { 1493 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1494 unsigned int val; 1495 int change; 1496 1497 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; 1498 guard(spinlock_irq)(&rme32->lock); 1499 val = (rme32->wcreg & ~RME32_WCR_SEL) | val; 1500 change = val != rme32->wcreg; 1501 if (ucontrol->value.integer.value[0]) 1502 val &= ~RME32_WCR_MUTE; 1503 else 1504 val |= RME32_WCR_MUTE; 1505 rme32->wcreg = val; 1506 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1507 return change; 1508 } 1509 1510 static int 1511 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, 1512 struct snd_ctl_elem_info *uinfo) 1513 { 1514 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1515 static const char * const texts[4] = { 1516 "Optical", "Coaxial", "Internal", "XLR" 1517 }; 1518 int num_items; 1519 1520 switch (rme32->pci->device) { 1521 case PCI_DEVICE_ID_RME_DIGI32: 1522 case PCI_DEVICE_ID_RME_DIGI32_8: 1523 num_items = 3; 1524 break; 1525 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1526 num_items = 4; 1527 break; 1528 default: 1529 snd_BUG(); 1530 return -EINVAL; 1531 } 1532 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1533 } 1534 static int 1535 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, 1536 struct snd_ctl_elem_value *ucontrol) 1537 { 1538 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1539 unsigned int items = 3; 1540 1541 guard(spinlock_irq)(&rme32->lock); 1542 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); 1543 1544 switch (rme32->pci->device) { 1545 case PCI_DEVICE_ID_RME_DIGI32: 1546 case PCI_DEVICE_ID_RME_DIGI32_8: 1547 items = 3; 1548 break; 1549 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1550 items = 4; 1551 break; 1552 default: 1553 snd_BUG(); 1554 break; 1555 } 1556 if (ucontrol->value.enumerated.item[0] >= items) { 1557 ucontrol->value.enumerated.item[0] = items - 1; 1558 } 1559 1560 return 0; 1561 } 1562 static int 1563 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, 1564 struct snd_ctl_elem_value *ucontrol) 1565 { 1566 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1567 unsigned int val; 1568 int change, items = 3; 1569 1570 switch (rme32->pci->device) { 1571 case PCI_DEVICE_ID_RME_DIGI32: 1572 case PCI_DEVICE_ID_RME_DIGI32_8: 1573 items = 3; 1574 break; 1575 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1576 items = 4; 1577 break; 1578 default: 1579 snd_BUG(); 1580 break; 1581 } 1582 val = ucontrol->value.enumerated.item[0] % items; 1583 1584 guard(spinlock_irq)(&rme32->lock); 1585 change = val != (unsigned int)snd_rme32_getinputtype(rme32); 1586 snd_rme32_setinputtype(rme32, val); 1587 return change; 1588 } 1589 1590 static int 1591 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, 1592 struct snd_ctl_elem_info *uinfo) 1593 { 1594 static const char * const texts[4] = { "AutoSync", 1595 "Internal 32.0kHz", 1596 "Internal 44.1kHz", 1597 "Internal 48.0kHz" }; 1598 1599 return snd_ctl_enum_info(uinfo, 1, 4, texts); 1600 } 1601 static int 1602 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, 1603 struct snd_ctl_elem_value *ucontrol) 1604 { 1605 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1606 1607 guard(spinlock_irq)(&rme32->lock); 1608 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); 1609 return 0; 1610 } 1611 static int 1612 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, 1613 struct snd_ctl_elem_value *ucontrol) 1614 { 1615 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1616 unsigned int val; 1617 int change; 1618 1619 val = ucontrol->value.enumerated.item[0] % 3; 1620 guard(spinlock_irq)(&rme32->lock); 1621 change = val != (unsigned int)snd_rme32_getclockmode(rme32); 1622 snd_rme32_setclockmode(rme32, val); 1623 return change; 1624 } 1625 1626 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) 1627 { 1628 u32 val = 0; 1629 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; 1630 if (val & RME32_WCR_PRO) 1631 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1632 else 1633 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1634 return val; 1635 } 1636 1637 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) 1638 { 1639 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); 1640 if (val & RME32_WCR_PRO) 1641 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1642 else 1643 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1644 } 1645 1646 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, 1647 struct snd_ctl_elem_info *uinfo) 1648 { 1649 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1650 uinfo->count = 1; 1651 return 0; 1652 } 1653 1654 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, 1655 struct snd_ctl_elem_value *ucontrol) 1656 { 1657 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1658 1659 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1660 rme32->wcreg_spdif); 1661 return 0; 1662 } 1663 1664 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, 1665 struct snd_ctl_elem_value *ucontrol) 1666 { 1667 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1668 int change; 1669 u32 val; 1670 1671 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1672 guard(spinlock_irq)(&rme32->lock); 1673 change = val != rme32->wcreg_spdif; 1674 rme32->wcreg_spdif = val; 1675 return change; 1676 } 1677 1678 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, 1679 struct snd_ctl_elem_info *uinfo) 1680 { 1681 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1682 uinfo->count = 1; 1683 return 0; 1684 } 1685 1686 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, 1687 struct snd_ctl_elem_value * 1688 ucontrol) 1689 { 1690 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1691 1692 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1693 rme32->wcreg_spdif_stream); 1694 return 0; 1695 } 1696 1697 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, 1698 struct snd_ctl_elem_value * 1699 ucontrol) 1700 { 1701 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1702 int change; 1703 u32 val; 1704 1705 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1706 guard(spinlock_irq)(&rme32->lock); 1707 change = val != rme32->wcreg_spdif_stream; 1708 rme32->wcreg_spdif_stream = val; 1709 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 1710 rme32->wcreg |= val; 1711 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1712 return change; 1713 } 1714 1715 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, 1716 struct snd_ctl_elem_info *uinfo) 1717 { 1718 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1719 uinfo->count = 1; 1720 return 0; 1721 } 1722 1723 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, 1724 struct snd_ctl_elem_value * 1725 ucontrol) 1726 { 1727 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1728 return 0; 1729 } 1730 1731 static const struct snd_kcontrol_new snd_rme32_controls[] = { 1732 { 1733 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1734 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1735 .info = snd_rme32_control_spdif_info, 1736 .get = snd_rme32_control_spdif_get, 1737 .put = snd_rme32_control_spdif_put 1738 }, 1739 { 1740 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1741 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1742 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), 1743 .info = snd_rme32_control_spdif_stream_info, 1744 .get = snd_rme32_control_spdif_stream_get, 1745 .put = snd_rme32_control_spdif_stream_put 1746 }, 1747 { 1748 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1749 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1750 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1751 .info = snd_rme32_control_spdif_mask_info, 1752 .get = snd_rme32_control_spdif_mask_get, 1753 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS 1754 }, 1755 { 1756 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1757 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1758 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), 1759 .info = snd_rme32_control_spdif_mask_info, 1760 .get = snd_rme32_control_spdif_mask_get, 1761 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS 1762 }, 1763 { 1764 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1765 .name = "Input Connector", 1766 .info = snd_rme32_info_inputtype_control, 1767 .get = snd_rme32_get_inputtype_control, 1768 .put = snd_rme32_put_inputtype_control 1769 }, 1770 { 1771 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1772 .name = "Loopback Input", 1773 .info = snd_rme32_info_loopback_control, 1774 .get = snd_rme32_get_loopback_control, 1775 .put = snd_rme32_put_loopback_control 1776 }, 1777 { 1778 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1779 .name = "Sample Clock Source", 1780 .info = snd_rme32_info_clockmode_control, 1781 .get = snd_rme32_get_clockmode_control, 1782 .put = snd_rme32_put_clockmode_control 1783 } 1784 }; 1785 1786 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) 1787 { 1788 int idx, err; 1789 struct snd_kcontrol *kctl; 1790 1791 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { 1792 kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32); 1793 err = snd_ctl_add(card, kctl); 1794 if (err < 0) 1795 return err; 1796 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 1797 rme32->spdif_ctl = kctl; 1798 } 1799 1800 return 0; 1801 } 1802 1803 /* 1804 * Card initialisation 1805 */ 1806 1807 static void snd_rme32_card_free(struct snd_card *card) 1808 { 1809 snd_rme32_free(card->private_data); 1810 } 1811 1812 static int 1813 __snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1814 { 1815 static int dev; 1816 struct rme32 *rme32; 1817 struct snd_card *card; 1818 int err; 1819 1820 if (dev >= SNDRV_CARDS) { 1821 return -ENODEV; 1822 } 1823 if (!enable[dev]) { 1824 dev++; 1825 return -ENOENT; 1826 } 1827 1828 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1829 sizeof(*rme32), &card); 1830 if (err < 0) 1831 return err; 1832 card->private_free = snd_rme32_card_free; 1833 rme32 = (struct rme32 *) card->private_data; 1834 rme32->card = card; 1835 rme32->pci = pci; 1836 if (fullduplex[dev]) 1837 rme32->fullduplex_mode = 1; 1838 err = snd_rme32_create(rme32); 1839 if (err < 0) 1840 return err; 1841 1842 strscpy(card->driver, "Digi32"); 1843 switch (rme32->pci->device) { 1844 case PCI_DEVICE_ID_RME_DIGI32: 1845 strscpy(card->shortname, "RME Digi32"); 1846 break; 1847 case PCI_DEVICE_ID_RME_DIGI32_8: 1848 strscpy(card->shortname, "RME Digi32/8"); 1849 break; 1850 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1851 strscpy(card->shortname, "RME Digi32 PRO"); 1852 break; 1853 } 1854 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", 1855 card->shortname, rme32->rev, rme32->port, rme32->irq); 1856 1857 err = snd_card_register(card); 1858 if (err < 0) 1859 return err; 1860 pci_set_drvdata(pci, card); 1861 dev++; 1862 return 0; 1863 } 1864 1865 static int 1866 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1867 { 1868 return snd_card_free_on_error(&pci->dev, __snd_rme32_probe(pci, pci_id)); 1869 } 1870 1871 static struct pci_driver rme32_driver = { 1872 .name = KBUILD_MODNAME, 1873 .id_table = snd_rme32_ids, 1874 .probe = snd_rme32_probe, 1875 }; 1876 1877 module_pci_driver(rme32_driver); 1878