1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/of_net.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/delay.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <linux/pm_runtime.h>
23
24 #include "stmmac_platform.h"
25
26 struct rk_priv_data;
27 struct rk_gmac_ops {
28 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
29 int tx_delay, int rx_delay);
30 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
31 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
32 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
33 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
34 bool enable);
35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
37 bool php_grf_required;
38 bool regs_valid;
39 u32 regs[];
40 };
41
42 static const char * const rk_clocks[] = {
43 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
44 };
45
46 static const char * const rk_rmii_clocks[] = {
47 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
48 };
49
50 enum rk_clocks_index {
51 RK_ACLK_MAC = 0,
52 RK_PCLK_MAC,
53 RK_MAC_CLK_TX,
54 RK_CLK_MAC_SPEED,
55 RK_MAC_CLK_RX,
56 RK_CLK_MAC_REF,
57 RK_CLK_MAC_REFOUT,
58 };
59
60 struct rk_priv_data {
61 struct platform_device *pdev;
62 phy_interface_t phy_iface;
63 int id;
64 struct regulator *regulator;
65 bool suspended;
66 const struct rk_gmac_ops *ops;
67
68 bool clk_enabled;
69 bool clock_input;
70 bool integrated_phy;
71
72 struct clk_bulk_data *clks;
73 int num_clks;
74 struct clk *clk_mac;
75 struct clk *clk_phy;
76
77 struct reset_control *phy_reset;
78
79 int tx_delay;
80 int rx_delay;
81
82 struct regmap *grf;
83 struct regmap *php_grf;
84 };
85
86 #define HIWORD_UPDATE(val, mask, shift) \
87 ((val) << (shift) | (mask) << ((shift) + 16))
88
89 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
90 #define GRF_CLR_BIT(nr) (BIT(nr+16))
91
92 #define DELAY_ENABLE(soc, tx, rx) \
93 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
94 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
95
96 #define RK_GRF_MACPHY_CON0 0xb00
97 #define RK_GRF_MACPHY_CON1 0xb04
98 #define RK_GRF_MACPHY_CON2 0xb08
99 #define RK_GRF_MACPHY_CON3 0xb0c
100
101 #define RK_MACPHY_ENABLE GRF_BIT(0)
102 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
103 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
104 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
105 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
106 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
107
rk_gmac_integrated_ephy_powerup(struct rk_priv_data * priv)108 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
109 {
110 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
111 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
112
113 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
114 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
115
116 if (priv->phy_reset) {
117 /* PHY needs to be disabled before trying to reset it */
118 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
119 if (priv->phy_reset)
120 reset_control_assert(priv->phy_reset);
121 usleep_range(10, 20);
122 if (priv->phy_reset)
123 reset_control_deassert(priv->phy_reset);
124 usleep_range(10, 20);
125 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
126 msleep(30);
127 }
128 }
129
rk_gmac_integrated_ephy_powerdown(struct rk_priv_data * priv)130 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
131 {
132 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
133 if (priv->phy_reset)
134 reset_control_assert(priv->phy_reset);
135 }
136
137 #define RK_FEPHY_SHUTDOWN GRF_BIT(1)
138 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
139 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
140 #define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
141 #define RK_FEPHY_PHY_ID GRF_BIT(11)
142
rk_gmac_integrated_fephy_powerup(struct rk_priv_data * priv,unsigned int reg)143 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
144 unsigned int reg)
145 {
146 reset_control_assert(priv->phy_reset);
147 usleep_range(20, 30);
148
149 regmap_write(priv->grf, reg,
150 RK_FEPHY_POWERUP |
151 RK_FEPHY_INTERNAL_RMII_SEL |
152 RK_FEPHY_24M_CLK_SEL |
153 RK_FEPHY_PHY_ID);
154 usleep_range(10000, 12000);
155
156 reset_control_deassert(priv->phy_reset);
157 usleep_range(50000, 60000);
158 }
159
rk_gmac_integrated_fephy_powerdown(struct rk_priv_data * priv,unsigned int reg)160 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
161 unsigned int reg)
162 {
163 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
164 }
165
166 #define PX30_GRF_GMAC_CON1 0x0904
167
168 /* PX30_GRF_GMAC_CON1 */
169 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
170 GRF_BIT(6))
171 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
172 #define PX30_GMAC_SPEED_100M GRF_BIT(2)
173
px30_set_to_rmii(struct rk_priv_data * bsp_priv)174 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
175 {
176 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
177 PX30_GMAC_PHY_INTF_SEL_RMII);
178 }
179
px30_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)180 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
181 {
182 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
183 struct device *dev = &bsp_priv->pdev->dev;
184 int ret;
185
186 if (!clk_mac_speed) {
187 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
188 return;
189 }
190
191 if (speed == 10) {
192 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
193 PX30_GMAC_SPEED_10M);
194
195 ret = clk_set_rate(clk_mac_speed, 2500000);
196 if (ret)
197 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
198 __func__, ret);
199 } else if (speed == 100) {
200 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
201 PX30_GMAC_SPEED_100M);
202
203 ret = clk_set_rate(clk_mac_speed, 25000000);
204 if (ret)
205 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
206 __func__, ret);
207
208 } else {
209 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
210 }
211 }
212
213 static const struct rk_gmac_ops px30_ops = {
214 .set_to_rmii = px30_set_to_rmii,
215 .set_rmii_speed = px30_set_rmii_speed,
216 };
217
218 #define RK3128_GRF_MAC_CON0 0x0168
219 #define RK3128_GRF_MAC_CON1 0x016c
220
221 /* RK3128_GRF_MAC_CON0 */
222 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
223 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
224 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
225 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
226 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
227 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
228
229 /* RK3128_GRF_MAC_CON1 */
230 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \
231 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
232 #define RK3128_GMAC_PHY_INTF_SEL_RMII \
233 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
234 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
235 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
236 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
237 #define RK3128_GMAC_SPEED_100M GRF_BIT(10)
238 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
239 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
240 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
241 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
242 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
243 #define RK3128_GMAC_RMII_MODE GRF_BIT(14)
244 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
245
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)246 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
247 int tx_delay, int rx_delay)
248 {
249 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
250 RK3128_GMAC_PHY_INTF_SEL_RGMII |
251 RK3128_GMAC_RMII_MODE_CLR);
252 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
253 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
254 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
255 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
256 }
257
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)258 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
259 {
260 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
261 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
262 }
263
rk3128_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)264 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
265 {
266 struct device *dev = &bsp_priv->pdev->dev;
267
268 if (speed == 10)
269 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
270 RK3128_GMAC_CLK_2_5M);
271 else if (speed == 100)
272 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
273 RK3128_GMAC_CLK_25M);
274 else if (speed == 1000)
275 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
276 RK3128_GMAC_CLK_125M);
277 else
278 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
279 }
280
rk3128_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)281 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
282 {
283 struct device *dev = &bsp_priv->pdev->dev;
284
285 if (speed == 10) {
286 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
287 RK3128_GMAC_RMII_CLK_2_5M |
288 RK3128_GMAC_SPEED_10M);
289 } else if (speed == 100) {
290 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
291 RK3128_GMAC_RMII_CLK_25M |
292 RK3128_GMAC_SPEED_100M);
293 } else {
294 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
295 }
296 }
297
298 static const struct rk_gmac_ops rk3128_ops = {
299 .set_to_rgmii = rk3128_set_to_rgmii,
300 .set_to_rmii = rk3128_set_to_rmii,
301 .set_rgmii_speed = rk3128_set_rgmii_speed,
302 .set_rmii_speed = rk3128_set_rmii_speed,
303 };
304
305 #define RK3228_GRF_MAC_CON0 0x0900
306 #define RK3228_GRF_MAC_CON1 0x0904
307
308 #define RK3228_GRF_CON_MUX 0x50
309
310 /* RK3228_GRF_MAC_CON0 */
311 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
312 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
313
314 /* RK3228_GRF_MAC_CON1 */
315 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
316 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
317 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
318 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
319 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
320 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
321 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
322 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
323 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
324 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
325 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
326 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
327 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
328 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
329 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
330 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
331 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
332 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
333 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
334
335 /* RK3228_GRF_COM_MUX */
336 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
337
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)338 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
339 int tx_delay, int rx_delay)
340 {
341 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
342 RK3228_GMAC_PHY_INTF_SEL_RGMII |
343 RK3228_GMAC_RMII_MODE_CLR |
344 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
345
346 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
347 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
348 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
349 }
350
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)351 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
352 {
353 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
354 RK3228_GMAC_PHY_INTF_SEL_RMII |
355 RK3228_GMAC_RMII_MODE);
356
357 /* set MAC to RMII mode */
358 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
359 }
360
rk3228_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)361 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
362 {
363 struct device *dev = &bsp_priv->pdev->dev;
364
365 if (speed == 10)
366 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
367 RK3228_GMAC_CLK_2_5M);
368 else if (speed == 100)
369 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
370 RK3228_GMAC_CLK_25M);
371 else if (speed == 1000)
372 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
373 RK3228_GMAC_CLK_125M);
374 else
375 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
376 }
377
rk3228_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)378 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
379 {
380 struct device *dev = &bsp_priv->pdev->dev;
381
382 if (speed == 10)
383 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
384 RK3228_GMAC_RMII_CLK_2_5M |
385 RK3228_GMAC_SPEED_10M);
386 else if (speed == 100)
387 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
388 RK3228_GMAC_RMII_CLK_25M |
389 RK3228_GMAC_SPEED_100M);
390 else
391 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
392 }
393
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)394 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
395 {
396 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
397 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
398
399 rk_gmac_integrated_ephy_powerup(priv);
400 }
401
402 static const struct rk_gmac_ops rk3228_ops = {
403 .set_to_rgmii = rk3228_set_to_rgmii,
404 .set_to_rmii = rk3228_set_to_rmii,
405 .set_rgmii_speed = rk3228_set_rgmii_speed,
406 .set_rmii_speed = rk3228_set_rmii_speed,
407 .integrated_phy_powerup = rk3228_integrated_phy_powerup,
408 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
409 };
410
411 #define RK3288_GRF_SOC_CON1 0x0248
412 #define RK3288_GRF_SOC_CON3 0x0250
413
414 /*RK3288_GRF_SOC_CON1*/
415 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
416 GRF_CLR_BIT(8))
417 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
418 GRF_BIT(8))
419 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
420 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
421 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
422 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
423 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
424 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
425 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
426 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
427 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
428 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
429 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
430
431 /*RK3288_GRF_SOC_CON3*/
432 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
433 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
434 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
435 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
436 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
437 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
438
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)439 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
440 int tx_delay, int rx_delay)
441 {
442 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
443 RK3288_GMAC_PHY_INTF_SEL_RGMII |
444 RK3288_GMAC_RMII_MODE_CLR);
445 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
446 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
447 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
448 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
449 }
450
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)451 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
452 {
453 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
454 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
455 }
456
rk3288_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)457 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
458 {
459 struct device *dev = &bsp_priv->pdev->dev;
460
461 if (speed == 10)
462 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
463 RK3288_GMAC_CLK_2_5M);
464 else if (speed == 100)
465 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
466 RK3288_GMAC_CLK_25M);
467 else if (speed == 1000)
468 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
469 RK3288_GMAC_CLK_125M);
470 else
471 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
472 }
473
rk3288_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)474 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
475 {
476 struct device *dev = &bsp_priv->pdev->dev;
477
478 if (speed == 10) {
479 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
480 RK3288_GMAC_RMII_CLK_2_5M |
481 RK3288_GMAC_SPEED_10M);
482 } else if (speed == 100) {
483 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
484 RK3288_GMAC_RMII_CLK_25M |
485 RK3288_GMAC_SPEED_100M);
486 } else {
487 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
488 }
489 }
490
491 static const struct rk_gmac_ops rk3288_ops = {
492 .set_to_rgmii = rk3288_set_to_rgmii,
493 .set_to_rmii = rk3288_set_to_rmii,
494 .set_rgmii_speed = rk3288_set_rgmii_speed,
495 .set_rmii_speed = rk3288_set_rmii_speed,
496 };
497
498 #define RK3308_GRF_MAC_CON0 0x04a0
499
500 /* RK3308_GRF_MAC_CON0 */
501 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
502 GRF_BIT(4))
503 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
504 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
505 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
506 #define RK3308_GMAC_SPEED_100M GRF_BIT(0)
507
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)508 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
509 {
510 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
511 RK3308_GMAC_PHY_INTF_SEL_RMII);
512 }
513
rk3308_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)514 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
515 {
516 struct device *dev = &bsp_priv->pdev->dev;
517
518 if (speed == 10) {
519 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
520 RK3308_GMAC_SPEED_10M);
521 } else if (speed == 100) {
522 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
523 RK3308_GMAC_SPEED_100M);
524 } else {
525 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
526 }
527 }
528
529 static const struct rk_gmac_ops rk3308_ops = {
530 .set_to_rmii = rk3308_set_to_rmii,
531 .set_rmii_speed = rk3308_set_rmii_speed,
532 };
533
534 #define RK3328_GRF_MAC_CON0 0x0900
535 #define RK3328_GRF_MAC_CON1 0x0904
536 #define RK3328_GRF_MAC_CON2 0x0908
537 #define RK3328_GRF_MACPHY_CON1 0xb04
538
539 /* RK3328_GRF_MAC_CON0 */
540 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
541 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
542
543 /* RK3328_GRF_MAC_CON1 */
544 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \
545 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
546 #define RK3328_GMAC_PHY_INTF_SEL_RMII \
547 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
548 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
549 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
550 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
551 #define RK3328_GMAC_SPEED_100M GRF_BIT(2)
552 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
553 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
554 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
555 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
556 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
557 #define RK3328_GMAC_RMII_MODE GRF_BIT(9)
558 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
559 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
560 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
561 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
562 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
563
564 /* RK3328_GRF_MACPHY_CON1 */
565 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
566
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)567 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
568 int tx_delay, int rx_delay)
569 {
570 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
571 RK3328_GMAC_PHY_INTF_SEL_RGMII |
572 RK3328_GMAC_RMII_MODE_CLR |
573 RK3328_GMAC_RXCLK_DLY_ENABLE |
574 RK3328_GMAC_TXCLK_DLY_ENABLE);
575
576 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
577 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
578 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
579 }
580
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)581 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
582 {
583 unsigned int reg;
584
585 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
586 RK3328_GRF_MAC_CON1;
587
588 regmap_write(bsp_priv->grf, reg,
589 RK3328_GMAC_PHY_INTF_SEL_RMII |
590 RK3328_GMAC_RMII_MODE);
591 }
592
rk3328_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)593 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
594 {
595 struct device *dev = &bsp_priv->pdev->dev;
596
597 if (speed == 10)
598 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
599 RK3328_GMAC_CLK_2_5M);
600 else if (speed == 100)
601 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
602 RK3328_GMAC_CLK_25M);
603 else if (speed == 1000)
604 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
605 RK3328_GMAC_CLK_125M);
606 else
607 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
608 }
609
rk3328_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)610 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
611 {
612 struct device *dev = &bsp_priv->pdev->dev;
613 unsigned int reg;
614
615 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
616 RK3328_GRF_MAC_CON1;
617
618 if (speed == 10)
619 regmap_write(bsp_priv->grf, reg,
620 RK3328_GMAC_RMII_CLK_2_5M |
621 RK3328_GMAC_SPEED_10M);
622 else if (speed == 100)
623 regmap_write(bsp_priv->grf, reg,
624 RK3328_GMAC_RMII_CLK_25M |
625 RK3328_GMAC_SPEED_100M);
626 else
627 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
628 }
629
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)630 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
631 {
632 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
633 RK3328_MACPHY_RMII_MODE);
634
635 rk_gmac_integrated_ephy_powerup(priv);
636 }
637
638 static const struct rk_gmac_ops rk3328_ops = {
639 .set_to_rgmii = rk3328_set_to_rgmii,
640 .set_to_rmii = rk3328_set_to_rmii,
641 .set_rgmii_speed = rk3328_set_rgmii_speed,
642 .set_rmii_speed = rk3328_set_rmii_speed,
643 .integrated_phy_powerup = rk3328_integrated_phy_powerup,
644 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
645 };
646
647 #define RK3366_GRF_SOC_CON6 0x0418
648 #define RK3366_GRF_SOC_CON7 0x041c
649
650 /* RK3366_GRF_SOC_CON6 */
651 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
652 GRF_CLR_BIT(11))
653 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
654 GRF_BIT(11))
655 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
656 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
657 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
658 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
659 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
660 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
661 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
662 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
663 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
664 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
665 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
666
667 /* RK3366_GRF_SOC_CON7 */
668 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
669 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
670 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
671 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
672 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
673 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
674
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)675 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
676 int tx_delay, int rx_delay)
677 {
678 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
679 RK3366_GMAC_PHY_INTF_SEL_RGMII |
680 RK3366_GMAC_RMII_MODE_CLR);
681 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
682 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
683 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
684 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
685 }
686
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)687 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
688 {
689 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
690 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
691 }
692
rk3366_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)693 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
694 {
695 struct device *dev = &bsp_priv->pdev->dev;
696
697 if (speed == 10)
698 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
699 RK3366_GMAC_CLK_2_5M);
700 else if (speed == 100)
701 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
702 RK3366_GMAC_CLK_25M);
703 else if (speed == 1000)
704 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
705 RK3366_GMAC_CLK_125M);
706 else
707 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
708 }
709
rk3366_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)710 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
711 {
712 struct device *dev = &bsp_priv->pdev->dev;
713
714 if (speed == 10) {
715 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
716 RK3366_GMAC_RMII_CLK_2_5M |
717 RK3366_GMAC_SPEED_10M);
718 } else if (speed == 100) {
719 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
720 RK3366_GMAC_RMII_CLK_25M |
721 RK3366_GMAC_SPEED_100M);
722 } else {
723 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
724 }
725 }
726
727 static const struct rk_gmac_ops rk3366_ops = {
728 .set_to_rgmii = rk3366_set_to_rgmii,
729 .set_to_rmii = rk3366_set_to_rmii,
730 .set_rgmii_speed = rk3366_set_rgmii_speed,
731 .set_rmii_speed = rk3366_set_rmii_speed,
732 };
733
734 #define RK3368_GRF_SOC_CON15 0x043c
735 #define RK3368_GRF_SOC_CON16 0x0440
736
737 /* RK3368_GRF_SOC_CON15 */
738 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
739 GRF_CLR_BIT(11))
740 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
741 GRF_BIT(11))
742 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
743 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
744 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
745 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
746 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
747 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
748 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
749 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
750 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
751 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
752 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
753
754 /* RK3368_GRF_SOC_CON16 */
755 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
756 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
757 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
758 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
759 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
760 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
761
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)762 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
763 int tx_delay, int rx_delay)
764 {
765 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
766 RK3368_GMAC_PHY_INTF_SEL_RGMII |
767 RK3368_GMAC_RMII_MODE_CLR);
768 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
769 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
770 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
771 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
772 }
773
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)774 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
775 {
776 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
777 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
778 }
779
rk3368_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)780 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
781 {
782 struct device *dev = &bsp_priv->pdev->dev;
783
784 if (speed == 10)
785 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
786 RK3368_GMAC_CLK_2_5M);
787 else if (speed == 100)
788 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
789 RK3368_GMAC_CLK_25M);
790 else if (speed == 1000)
791 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
792 RK3368_GMAC_CLK_125M);
793 else
794 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
795 }
796
rk3368_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)797 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
798 {
799 struct device *dev = &bsp_priv->pdev->dev;
800
801 if (speed == 10) {
802 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
803 RK3368_GMAC_RMII_CLK_2_5M |
804 RK3368_GMAC_SPEED_10M);
805 } else if (speed == 100) {
806 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
807 RK3368_GMAC_RMII_CLK_25M |
808 RK3368_GMAC_SPEED_100M);
809 } else {
810 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
811 }
812 }
813
814 static const struct rk_gmac_ops rk3368_ops = {
815 .set_to_rgmii = rk3368_set_to_rgmii,
816 .set_to_rmii = rk3368_set_to_rmii,
817 .set_rgmii_speed = rk3368_set_rgmii_speed,
818 .set_rmii_speed = rk3368_set_rmii_speed,
819 };
820
821 #define RK3399_GRF_SOC_CON5 0xc214
822 #define RK3399_GRF_SOC_CON6 0xc218
823
824 /* RK3399_GRF_SOC_CON5 */
825 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
826 GRF_CLR_BIT(11))
827 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
828 GRF_BIT(11))
829 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
830 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
831 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
832 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
833 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
834 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
835 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
836 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
837 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
838 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
839 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
840
841 /* RK3399_GRF_SOC_CON6 */
842 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
843 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
844 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
845 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
846 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
847 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
848
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)849 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
850 int tx_delay, int rx_delay)
851 {
852 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
853 RK3399_GMAC_PHY_INTF_SEL_RGMII |
854 RK3399_GMAC_RMII_MODE_CLR);
855 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
856 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
857 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
858 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
859 }
860
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)861 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
862 {
863 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
864 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
865 }
866
rk3399_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)867 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
868 {
869 struct device *dev = &bsp_priv->pdev->dev;
870
871 if (speed == 10)
872 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
873 RK3399_GMAC_CLK_2_5M);
874 else if (speed == 100)
875 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
876 RK3399_GMAC_CLK_25M);
877 else if (speed == 1000)
878 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
879 RK3399_GMAC_CLK_125M);
880 else
881 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
882 }
883
rk3399_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)884 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
885 {
886 struct device *dev = &bsp_priv->pdev->dev;
887
888 if (speed == 10) {
889 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
890 RK3399_GMAC_RMII_CLK_2_5M |
891 RK3399_GMAC_SPEED_10M);
892 } else if (speed == 100) {
893 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
894 RK3399_GMAC_RMII_CLK_25M |
895 RK3399_GMAC_SPEED_100M);
896 } else {
897 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
898 }
899 }
900
901 static const struct rk_gmac_ops rk3399_ops = {
902 .set_to_rgmii = rk3399_set_to_rgmii,
903 .set_to_rmii = rk3399_set_to_rmii,
904 .set_rgmii_speed = rk3399_set_rgmii_speed,
905 .set_rmii_speed = rk3399_set_rmii_speed,
906 };
907
908 #define RK3528_VO_GRF_GMAC_CON 0x0018
909 #define RK3528_VO_GRF_MACPHY_CON0 0x001c
910 #define RK3528_VO_GRF_MACPHY_CON1 0x0020
911 #define RK3528_VPU_GRF_GMAC_CON5 0x0018
912 #define RK3528_VPU_GRF_GMAC_CON6 0x001c
913
914 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
915 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
916 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
917 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
918
919 #define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
920 #define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
921
922 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
923 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
924 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
925
926 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
927 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
928
929 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
930 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
931 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
932 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
933
934 #define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
935 #define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
936 #define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
937
938 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
939 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
940 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
941 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
942
rk3528_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)943 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
944 int tx_delay, int rx_delay)
945 {
946 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
947 RK3528_GMAC1_PHY_INTF_SEL_RGMII);
948
949 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
950 DELAY_ENABLE(RK3528, tx_delay, rx_delay));
951
952 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
953 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
954 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
955 }
956
rk3528_set_to_rmii(struct rk_priv_data * bsp_priv)957 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
958 {
959 if (bsp_priv->id == 1)
960 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
961 RK3528_GMAC1_PHY_INTF_SEL_RMII);
962 else
963 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
964 RK3528_GMAC0_PHY_INTF_SEL_RMII |
965 RK3528_GMAC0_CLK_RMII_DIV2);
966 }
967
rk3528_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)968 static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
969 {
970 struct device *dev = &bsp_priv->pdev->dev;
971
972 if (speed == 10)
973 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
974 RK3528_GMAC1_CLK_RGMII_DIV50);
975 else if (speed == 100)
976 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
977 RK3528_GMAC1_CLK_RGMII_DIV5);
978 else if (speed == 1000)
979 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
980 RK3528_GMAC1_CLK_RGMII_DIV1);
981 else
982 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
983 }
984
rk3528_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)985 static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
986 {
987 struct device *dev = &bsp_priv->pdev->dev;
988 unsigned int reg, val;
989
990 if (speed == 10)
991 val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
992 RK3528_GMAC0_CLK_RMII_DIV20;
993 else if (speed == 100)
994 val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
995 RK3528_GMAC0_CLK_RMII_DIV2;
996 else {
997 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
998 return;
999 }
1000
1001 reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
1002 RK3528_VO_GRF_GMAC_CON;
1003
1004 regmap_write(bsp_priv->grf, reg, val);
1005 }
1006
rk3528_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1007 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1008 bool input, bool enable)
1009 {
1010 unsigned int val;
1011
1012 if (bsp_priv->id == 1) {
1013 val = input ? RK3528_GMAC1_CLK_SELECT_IO :
1014 RK3528_GMAC1_CLK_SELECT_CRU;
1015 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1016 RK3528_GMAC1_CLK_RMII_GATE;
1017 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1018 } else {
1019 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1020 RK3528_GMAC0_CLK_RMII_GATE;
1021 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
1022 }
1023 }
1024
rk3528_integrated_phy_powerup(struct rk_priv_data * bsp_priv)1025 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
1026 {
1027 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
1028 }
1029
rk3528_integrated_phy_powerdown(struct rk_priv_data * bsp_priv)1030 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
1031 {
1032 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
1033 }
1034
1035 static const struct rk_gmac_ops rk3528_ops = {
1036 .set_to_rgmii = rk3528_set_to_rgmii,
1037 .set_to_rmii = rk3528_set_to_rmii,
1038 .set_rgmii_speed = rk3528_set_rgmii_speed,
1039 .set_rmii_speed = rk3528_set_rmii_speed,
1040 .set_clock_selection = rk3528_set_clock_selection,
1041 .integrated_phy_powerup = rk3528_integrated_phy_powerup,
1042 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
1043 .regs_valid = true,
1044 .regs = {
1045 0xffbd0000, /* gmac0 */
1046 0xffbe0000, /* gmac1 */
1047 0x0, /* sentinel */
1048 },
1049 };
1050
1051 #define RK3568_GRF_GMAC0_CON0 0x0380
1052 #define RK3568_GRF_GMAC0_CON1 0x0384
1053 #define RK3568_GRF_GMAC1_CON0 0x0388
1054 #define RK3568_GRF_GMAC1_CON1 0x038c
1055
1056 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1057 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \
1058 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1059 #define RK3568_GMAC_PHY_INTF_SEL_RMII \
1060 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1061 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
1062 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1063 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1064 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1065 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1066 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1067
1068 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1069 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1070 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1071
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1072 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1073 int tx_delay, int rx_delay)
1074 {
1075 u32 con0, con1;
1076
1077 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1078 RK3568_GRF_GMAC0_CON0;
1079 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1080 RK3568_GRF_GMAC0_CON1;
1081
1082 regmap_write(bsp_priv->grf, con0,
1083 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1084 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1085
1086 regmap_write(bsp_priv->grf, con1,
1087 RK3568_GMAC_PHY_INTF_SEL_RGMII |
1088 RK3568_GMAC_RXCLK_DLY_ENABLE |
1089 RK3568_GMAC_TXCLK_DLY_ENABLE);
1090 }
1091
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1092 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1093 {
1094 u32 con1;
1095
1096 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1097 RK3568_GRF_GMAC0_CON1;
1098 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1099 }
1100
rk3568_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1101 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1102 {
1103 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1104 struct device *dev = &bsp_priv->pdev->dev;
1105 long rate;
1106 int ret;
1107
1108 rate = rgmii_clock(speed);
1109 if (rate < 0) {
1110 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1111 return;
1112 }
1113
1114 ret = clk_set_rate(clk_mac_speed, rate);
1115 if (ret)
1116 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1117 __func__, rate, ret);
1118 }
1119
1120 static const struct rk_gmac_ops rk3568_ops = {
1121 .set_to_rgmii = rk3568_set_to_rgmii,
1122 .set_to_rmii = rk3568_set_to_rmii,
1123 .set_rgmii_speed = rk3568_set_gmac_speed,
1124 .set_rmii_speed = rk3568_set_gmac_speed,
1125 .regs_valid = true,
1126 .regs = {
1127 0xfe2a0000, /* gmac0 */
1128 0xfe010000, /* gmac1 */
1129 0x0, /* sentinel */
1130 },
1131 };
1132
1133 /* VCCIO0_1_3_IOC */
1134 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
1135 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
1136 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410
1137 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414
1138
1139 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1140 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1141 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1142 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1143
1144 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1145 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1146
1147 /* SDGMAC_GRF */
1148 #define RK3576_GRF_GMAC_CON0 0X0020
1149 #define RK3576_GRF_GMAC_CON1 0X0024
1150
1151 #define RK3576_GMAC_RMII_MODE GRF_BIT(3)
1152 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
1153
1154 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
1155 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
1156
1157 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
1158 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
1159
1160 #define RK3576_GMAC_CLK_RGMII_DIV1 \
1161 (GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
1162 #define RK3576_GMAC_CLK_RGMII_DIV5 \
1163 (GRF_BIT(6) | GRF_BIT(5))
1164 #define RK3576_GMAC_CLK_RGMII_DIV50 \
1165 (GRF_BIT(6) | GRF_CLR_BIT(5))
1166
1167 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
1168 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
1169
rk3576_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1170 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
1171 int tx_delay, int rx_delay)
1172 {
1173 unsigned int offset_con;
1174
1175 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1176 RK3576_GRF_GMAC_CON0;
1177
1178 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
1179
1180 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
1181 RK3576_VCCIO0_1_3_IOC_CON2;
1182
1183 /* m0 && m1 delay enabled */
1184 regmap_write(bsp_priv->php_grf, offset_con,
1185 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1186 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1187 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1188
1189 /* m0 && m1 delay value */
1190 regmap_write(bsp_priv->php_grf, offset_con,
1191 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1192 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1193 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1194 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1195 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1196 }
1197
rk3576_set_to_rmii(struct rk_priv_data * bsp_priv)1198 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
1199 {
1200 unsigned int offset_con;
1201
1202 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1203 RK3576_GRF_GMAC_CON0;
1204
1205 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
1206 }
1207
rk3576_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1208 static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1209 {
1210 struct device *dev = &bsp_priv->pdev->dev;
1211 unsigned int val = 0, offset_con;
1212
1213 switch (speed) {
1214 case 10:
1215 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1216 val = RK3576_GMAC_CLK_RMII_DIV20;
1217 else
1218 val = RK3576_GMAC_CLK_RGMII_DIV50;
1219 break;
1220 case 100:
1221 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1222 val = RK3576_GMAC_CLK_RMII_DIV2;
1223 else
1224 val = RK3576_GMAC_CLK_RGMII_DIV5;
1225 break;
1226 case 1000:
1227 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1228 val = RK3576_GMAC_CLK_RGMII_DIV1;
1229 else
1230 goto err;
1231 break;
1232 default:
1233 goto err;
1234 }
1235
1236 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1237 RK3576_GRF_GMAC_CON0;
1238
1239 regmap_write(bsp_priv->grf, offset_con, val);
1240
1241 return;
1242 err:
1243 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1244 }
1245
rk3576_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1246 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1247 bool enable)
1248 {
1249 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
1250 RK3576_GMAC_CLK_SELECT_CRU;
1251 unsigned int offset_con;
1252
1253 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
1254 RK3576_GMAC_CLK_RMII_GATE;
1255
1256 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1257 RK3576_GRF_GMAC_CON0;
1258
1259 regmap_write(bsp_priv->grf, offset_con, val);
1260 }
1261
1262 static const struct rk_gmac_ops rk3576_ops = {
1263 .set_to_rgmii = rk3576_set_to_rgmii,
1264 .set_to_rmii = rk3576_set_to_rmii,
1265 .set_rgmii_speed = rk3576_set_gmac_speed,
1266 .set_rmii_speed = rk3576_set_gmac_speed,
1267 .set_clock_selection = rk3576_set_clock_selection,
1268 .php_grf_required = true,
1269 .regs_valid = true,
1270 .regs = {
1271 0x2a220000, /* gmac0 */
1272 0x2a230000, /* gmac1 */
1273 0x0, /* sentinel */
1274 },
1275 };
1276
1277 /* sys_grf */
1278 #define RK3588_GRF_GMAC_CON7 0X031c
1279 #define RK3588_GRF_GMAC_CON8 0X0320
1280 #define RK3588_GRF_GMAC_CON9 0X0324
1281
1282 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
1283 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
1284 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
1285 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
1286
1287 #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
1288 #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
1289
1290 /* php_grf */
1291 #define RK3588_GRF_GMAC_CON0 0X0008
1292 #define RK3588_GRF_CLK_CON1 0X0070
1293
1294 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
1295 (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1296 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
1297 (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1298
1299 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
1300 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
1301
1302 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
1303 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
1304
1305 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
1306 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
1307
1308 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \
1309 (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1310 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \
1311 (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1312 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \
1313 (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1314
1315 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
1316 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
1317
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1318 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1319 int tx_delay, int rx_delay)
1320 {
1321 u32 offset_con, id = bsp_priv->id;
1322
1323 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1324 RK3588_GRF_GMAC_CON8;
1325
1326 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1327 RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1328
1329 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1330 RK3588_GMAC_CLK_RGMII_MODE(id));
1331
1332 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1333 RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1334 RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1335
1336 regmap_write(bsp_priv->grf, offset_con,
1337 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1338 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1339 }
1340
rk3588_set_to_rmii(struct rk_priv_data * bsp_priv)1341 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1342 {
1343 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1344 RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
1345
1346 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1347 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1348 }
1349
rk3588_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1350 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1351 {
1352 struct device *dev = &bsp_priv->pdev->dev;
1353 unsigned int val = 0, id = bsp_priv->id;
1354
1355 switch (speed) {
1356 case 10:
1357 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1358 val = RK3588_GMA_CLK_RMII_DIV20(id);
1359 else
1360 val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1361 break;
1362 case 100:
1363 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1364 val = RK3588_GMA_CLK_RMII_DIV2(id);
1365 else
1366 val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1367 break;
1368 case 1000:
1369 if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1370 val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1371 else
1372 goto err;
1373 break;
1374 default:
1375 goto err;
1376 }
1377
1378 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1379
1380 return;
1381 err:
1382 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1383 }
1384
rk3588_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1385 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1386 bool enable)
1387 {
1388 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) :
1389 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id);
1390
1391 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
1392 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
1393
1394 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1395 }
1396
1397 static const struct rk_gmac_ops rk3588_ops = {
1398 .set_to_rgmii = rk3588_set_to_rgmii,
1399 .set_to_rmii = rk3588_set_to_rmii,
1400 .set_rgmii_speed = rk3588_set_gmac_speed,
1401 .set_rmii_speed = rk3588_set_gmac_speed,
1402 .set_clock_selection = rk3588_set_clock_selection,
1403 .php_grf_required = true,
1404 .regs_valid = true,
1405 .regs = {
1406 0xfe1b0000, /* gmac0 */
1407 0xfe1c0000, /* gmac1 */
1408 0x0, /* sentinel */
1409 },
1410 };
1411
1412 #define RV1108_GRF_GMAC_CON0 0X0900
1413
1414 /* RV1108_GRF_GMAC_CON0 */
1415 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1416 GRF_BIT(6))
1417 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
1418 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1419 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
1420 #define RV1108_GMAC_SPEED_100M GRF_BIT(2)
1421 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
1422 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
1423
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)1424 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1425 {
1426 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1427 RV1108_GMAC_PHY_INTF_SEL_RMII);
1428 }
1429
rv1108_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1430 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1431 {
1432 struct device *dev = &bsp_priv->pdev->dev;
1433
1434 if (speed == 10) {
1435 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1436 RV1108_GMAC_RMII_CLK_2_5M |
1437 RV1108_GMAC_SPEED_10M);
1438 } else if (speed == 100) {
1439 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1440 RV1108_GMAC_RMII_CLK_25M |
1441 RV1108_GMAC_SPEED_100M);
1442 } else {
1443 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1444 }
1445 }
1446
1447 static const struct rk_gmac_ops rv1108_ops = {
1448 .set_to_rmii = rv1108_set_to_rmii,
1449 .set_rmii_speed = rv1108_set_rmii_speed,
1450 };
1451
1452 #define RV1126_GRF_GMAC_CON0 0X0070
1453 #define RV1126_GRF_GMAC_CON1 0X0074
1454 #define RV1126_GRF_GMAC_CON2 0X0078
1455
1456 /* RV1126_GRF_GMAC_CON0 */
1457 #define RV1126_GMAC_PHY_INTF_SEL_RGMII \
1458 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1459 #define RV1126_GMAC_PHY_INTF_SEL_RMII \
1460 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1461 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
1462 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
1463 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
1464 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1465 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
1466 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1467 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
1468 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
1469 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
1470 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
1471
1472 /* RV1126_GRF_GMAC_CON1 */
1473 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1474 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1475 /* RV1126_GRF_GMAC_CON2 */
1476 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1477 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1478
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1479 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1480 int tx_delay, int rx_delay)
1481 {
1482 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1483 RV1126_GMAC_PHY_INTF_SEL_RGMII |
1484 RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1485 RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1486 RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1487 RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1488
1489 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1490 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1491 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1492
1493 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1494 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1495 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1496 }
1497
rv1126_set_to_rmii(struct rk_priv_data * bsp_priv)1498 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1499 {
1500 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1501 RV1126_GMAC_PHY_INTF_SEL_RMII);
1502 }
1503
rv1126_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1504 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1505 {
1506 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1507 struct device *dev = &bsp_priv->pdev->dev;
1508 long rate;
1509 int ret;
1510
1511 rate = rgmii_clock(speed);
1512 if (rate < 0) {
1513 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1514 return;
1515 }
1516
1517 ret = clk_set_rate(clk_mac_speed, rate);
1518 if (ret)
1519 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1520 __func__, rate, ret);
1521 }
1522
rv1126_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1523 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1524 {
1525 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1526 struct device *dev = &bsp_priv->pdev->dev;
1527 unsigned long rate;
1528 int ret;
1529
1530 switch (speed) {
1531 case 10:
1532 rate = 2500000;
1533 break;
1534 case 100:
1535 rate = 25000000;
1536 break;
1537 default:
1538 dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1539 return;
1540 }
1541
1542 ret = clk_set_rate(clk_mac_speed, rate);
1543 if (ret)
1544 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1545 __func__, rate, ret);
1546 }
1547
1548 static const struct rk_gmac_ops rv1126_ops = {
1549 .set_to_rgmii = rv1126_set_to_rgmii,
1550 .set_to_rmii = rv1126_set_to_rmii,
1551 .set_rgmii_speed = rv1126_set_rgmii_speed,
1552 .set_rmii_speed = rv1126_set_rmii_speed,
1553 };
1554
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1555 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1556 {
1557 struct rk_priv_data *bsp_priv = plat->bsp_priv;
1558 struct device *dev = &bsp_priv->pdev->dev;
1559 int phy_iface = bsp_priv->phy_iface;
1560 int i, j, ret;
1561
1562 bsp_priv->clk_enabled = false;
1563
1564 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
1565 if (phy_iface == PHY_INTERFACE_MODE_RMII)
1566 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
1567
1568 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
1569 sizeof(*bsp_priv->clks), GFP_KERNEL);
1570 if (!bsp_priv->clks)
1571 return -ENOMEM;
1572
1573 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
1574 bsp_priv->clks[i].id = rk_clocks[i];
1575
1576 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1577 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
1578 bsp_priv->clks[i++].id = rk_rmii_clocks[j];
1579 }
1580
1581 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
1582 bsp_priv->clks);
1583 if (ret)
1584 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1585
1586 /* "stmmaceth" will be enabled by the core */
1587 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1588 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac);
1589 if (ret)
1590 return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n");
1591
1592 if (bsp_priv->clock_input) {
1593 dev_info(dev, "clock input from PHY\n");
1594 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1595 clk_set_rate(bsp_priv->clk_mac, 50000000);
1596 }
1597
1598 if (plat->phy_node && bsp_priv->integrated_phy) {
1599 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1600 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
1601 if (ret)
1602 return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
1603 clk_set_rate(bsp_priv->clk_phy, 50000000);
1604 }
1605
1606 return 0;
1607 }
1608
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1609 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1610 {
1611 int ret;
1612
1613 if (enable) {
1614 if (!bsp_priv->clk_enabled) {
1615 ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
1616 bsp_priv->clks);
1617 if (ret)
1618 return ret;
1619
1620 ret = clk_prepare_enable(bsp_priv->clk_phy);
1621 if (ret)
1622 return ret;
1623
1624 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1625 bsp_priv->ops->set_clock_selection(bsp_priv,
1626 bsp_priv->clock_input, true);
1627
1628 mdelay(5);
1629 bsp_priv->clk_enabled = true;
1630 }
1631 } else {
1632 if (bsp_priv->clk_enabled) {
1633 clk_bulk_disable_unprepare(bsp_priv->num_clks,
1634 bsp_priv->clks);
1635 clk_disable_unprepare(bsp_priv->clk_phy);
1636
1637 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1638 bsp_priv->ops->set_clock_selection(bsp_priv,
1639 bsp_priv->clock_input, false);
1640
1641 bsp_priv->clk_enabled = false;
1642 }
1643 }
1644
1645 return 0;
1646 }
1647
phy_power_on(struct rk_priv_data * bsp_priv,bool enable)1648 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1649 {
1650 struct regulator *ldo = bsp_priv->regulator;
1651 int ret;
1652 struct device *dev = &bsp_priv->pdev->dev;
1653
1654 if (enable) {
1655 ret = regulator_enable(ldo);
1656 if (ret)
1657 dev_err(dev, "fail to enable phy-supply\n");
1658 } else {
1659 ret = regulator_disable(ldo);
1660 if (ret)
1661 dev_err(dev, "fail to disable phy-supply\n");
1662 }
1663
1664 return 0;
1665 }
1666
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1667 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1668 struct plat_stmmacenet_data *plat,
1669 const struct rk_gmac_ops *ops)
1670 {
1671 struct rk_priv_data *bsp_priv;
1672 struct device *dev = &pdev->dev;
1673 struct resource *res;
1674 int ret;
1675 const char *strings = NULL;
1676 int value;
1677
1678 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1679 if (!bsp_priv)
1680 return ERR_PTR(-ENOMEM);
1681
1682 bsp_priv->phy_iface = plat->phy_interface;
1683 bsp_priv->ops = ops;
1684
1685 /* Some SoCs have multiple MAC controllers, which need
1686 * to be distinguished.
1687 */
1688 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1689 if (res && ops->regs_valid) {
1690 int i = 0;
1691
1692 while (ops->regs[i]) {
1693 if (ops->regs[i] == res->start) {
1694 bsp_priv->id = i;
1695 break;
1696 }
1697 i++;
1698 }
1699 }
1700
1701 bsp_priv->regulator = devm_regulator_get(dev, "phy");
1702 if (IS_ERR(bsp_priv->regulator)) {
1703 ret = PTR_ERR(bsp_priv->regulator);
1704 dev_err_probe(dev, ret, "failed to get phy regulator\n");
1705 return ERR_PTR(ret);
1706 }
1707
1708 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1709 if (ret) {
1710 dev_err(dev, "Can not read property: clock_in_out.\n");
1711 bsp_priv->clock_input = true;
1712 } else {
1713 dev_info(dev, "clock input or output? (%s).\n",
1714 strings);
1715 if (!strcmp(strings, "input"))
1716 bsp_priv->clock_input = true;
1717 else
1718 bsp_priv->clock_input = false;
1719 }
1720
1721 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1722 if (ret) {
1723 bsp_priv->tx_delay = 0x30;
1724 dev_err(dev, "Can not read property: tx_delay.");
1725 dev_err(dev, "set tx_delay to 0x%x\n",
1726 bsp_priv->tx_delay);
1727 } else {
1728 dev_info(dev, "TX delay(0x%x).\n", value);
1729 bsp_priv->tx_delay = value;
1730 }
1731
1732 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1733 if (ret) {
1734 bsp_priv->rx_delay = 0x10;
1735 dev_err(dev, "Can not read property: rx_delay.");
1736 dev_err(dev, "set rx_delay to 0x%x\n",
1737 bsp_priv->rx_delay);
1738 } else {
1739 dev_info(dev, "RX delay(0x%x).\n", value);
1740 bsp_priv->rx_delay = value;
1741 }
1742
1743 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1744 "rockchip,grf");
1745 if (IS_ERR(bsp_priv->grf)) {
1746 dev_err_probe(dev, PTR_ERR(bsp_priv->grf),
1747 "failed to lookup rockchip,grf\n");
1748 return ERR_CAST(bsp_priv->grf);
1749 }
1750
1751 if (ops->php_grf_required) {
1752 bsp_priv->php_grf =
1753 syscon_regmap_lookup_by_phandle(dev->of_node,
1754 "rockchip,php-grf");
1755 if (IS_ERR(bsp_priv->php_grf)) {
1756 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf),
1757 "failed to lookup rockchip,php-grf\n");
1758 return ERR_CAST(bsp_priv->php_grf);
1759 }
1760 }
1761
1762 if (plat->phy_node) {
1763 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1764 "phy-is-integrated");
1765 if (bsp_priv->integrated_phy) {
1766 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1767 if (IS_ERR(bsp_priv->phy_reset)) {
1768 dev_err(&pdev->dev, "No PHY reset control found.\n");
1769 bsp_priv->phy_reset = NULL;
1770 }
1771 }
1772 }
1773 dev_info(dev, "integrated PHY? (%s).\n",
1774 bsp_priv->integrated_phy ? "yes" : "no");
1775
1776 bsp_priv->pdev = pdev;
1777
1778 return bsp_priv;
1779 }
1780
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1781 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1782 {
1783 switch (bsp_priv->phy_iface) {
1784 case PHY_INTERFACE_MODE_RGMII:
1785 case PHY_INTERFACE_MODE_RGMII_ID:
1786 case PHY_INTERFACE_MODE_RGMII_RXID:
1787 case PHY_INTERFACE_MODE_RGMII_TXID:
1788 if (!bsp_priv->ops->set_to_rgmii)
1789 return -EINVAL;
1790 break;
1791 case PHY_INTERFACE_MODE_RMII:
1792 if (!bsp_priv->ops->set_to_rmii)
1793 return -EINVAL;
1794 break;
1795 default:
1796 dev_err(&bsp_priv->pdev->dev,
1797 "unsupported interface %d", bsp_priv->phy_iface);
1798 }
1799 return 0;
1800 }
1801
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1802 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1803 {
1804 int ret;
1805 struct device *dev = &bsp_priv->pdev->dev;
1806
1807 ret = rk_gmac_check_ops(bsp_priv);
1808 if (ret)
1809 return ret;
1810
1811 ret = gmac_clk_enable(bsp_priv, true);
1812 if (ret)
1813 return ret;
1814
1815 /*rmii or rgmii*/
1816 switch (bsp_priv->phy_iface) {
1817 case PHY_INTERFACE_MODE_RGMII:
1818 dev_info(dev, "init for RGMII\n");
1819 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1820 bsp_priv->rx_delay);
1821 break;
1822 case PHY_INTERFACE_MODE_RGMII_ID:
1823 dev_info(dev, "init for RGMII_ID\n");
1824 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1825 break;
1826 case PHY_INTERFACE_MODE_RGMII_RXID:
1827 dev_info(dev, "init for RGMII_RXID\n");
1828 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1829 break;
1830 case PHY_INTERFACE_MODE_RGMII_TXID:
1831 dev_info(dev, "init for RGMII_TXID\n");
1832 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1833 break;
1834 case PHY_INTERFACE_MODE_RMII:
1835 dev_info(dev, "init for RMII\n");
1836 bsp_priv->ops->set_to_rmii(bsp_priv);
1837 break;
1838 default:
1839 dev_err(dev, "NO interface defined!\n");
1840 }
1841
1842 ret = phy_power_on(bsp_priv, true);
1843 if (ret) {
1844 gmac_clk_enable(bsp_priv, false);
1845 return ret;
1846 }
1847
1848 pm_runtime_get_sync(dev);
1849
1850 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
1851 bsp_priv->ops->integrated_phy_powerup(bsp_priv);
1852
1853 return 0;
1854 }
1855
rk_gmac_powerdown(struct rk_priv_data * gmac)1856 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1857 {
1858 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
1859 gmac->ops->integrated_phy_powerdown(gmac);
1860
1861 pm_runtime_put_sync(&gmac->pdev->dev);
1862
1863 phy_power_on(gmac, false);
1864 gmac_clk_enable(gmac, false);
1865 }
1866
rk_set_clk_tx_rate(void * bsp_priv_,struct clk * clk_tx_i,phy_interface_t interface,int speed)1867 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i,
1868 phy_interface_t interface, int speed)
1869 {
1870 struct rk_priv_data *bsp_priv = bsp_priv_;
1871 struct device *dev = &bsp_priv->pdev->dev;
1872
1873 switch (bsp_priv->phy_iface) {
1874 case PHY_INTERFACE_MODE_RGMII:
1875 case PHY_INTERFACE_MODE_RGMII_ID:
1876 case PHY_INTERFACE_MODE_RGMII_RXID:
1877 case PHY_INTERFACE_MODE_RGMII_TXID:
1878 if (bsp_priv->ops->set_rgmii_speed)
1879 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1880 break;
1881 case PHY_INTERFACE_MODE_RMII:
1882 if (bsp_priv->ops->set_rmii_speed)
1883 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1884 break;
1885 default:
1886 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1887 }
1888
1889 return 0;
1890 }
1891
rk_gmac_probe(struct platform_device * pdev)1892 static int rk_gmac_probe(struct platform_device *pdev)
1893 {
1894 struct plat_stmmacenet_data *plat_dat;
1895 struct stmmac_resources stmmac_res;
1896 const struct rk_gmac_ops *data;
1897 int ret;
1898
1899 data = of_device_get_match_data(&pdev->dev);
1900 if (!data) {
1901 dev_err(&pdev->dev, "no of match data provided\n");
1902 return -EINVAL;
1903 }
1904
1905 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1906 if (ret)
1907 return ret;
1908
1909 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1910 if (IS_ERR(plat_dat))
1911 return PTR_ERR(plat_dat);
1912
1913 /* If the stmmac is not already selected as gmac4,
1914 * then make sure we fallback to gmac.
1915 */
1916 if (!plat_dat->has_gmac4) {
1917 plat_dat->has_gmac = true;
1918 plat_dat->rx_fifo_size = 4096;
1919 plat_dat->tx_fifo_size = 2048;
1920 }
1921
1922 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate;
1923
1924 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1925 if (IS_ERR(plat_dat->bsp_priv))
1926 return PTR_ERR(plat_dat->bsp_priv);
1927
1928 ret = rk_gmac_clk_init(plat_dat);
1929 if (ret)
1930 return ret;
1931
1932 ret = rk_gmac_powerup(plat_dat->bsp_priv);
1933 if (ret)
1934 return ret;
1935
1936 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1937 if (ret)
1938 goto err_gmac_powerdown;
1939
1940 return 0;
1941
1942 err_gmac_powerdown:
1943 rk_gmac_powerdown(plat_dat->bsp_priv);
1944
1945 return ret;
1946 }
1947
rk_gmac_remove(struct platform_device * pdev)1948 static void rk_gmac_remove(struct platform_device *pdev)
1949 {
1950 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1951
1952 stmmac_dvr_remove(&pdev->dev);
1953
1954 rk_gmac_powerdown(bsp_priv);
1955 }
1956
1957 #ifdef CONFIG_PM_SLEEP
rk_gmac_suspend(struct device * dev)1958 static int rk_gmac_suspend(struct device *dev)
1959 {
1960 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1961 int ret = stmmac_suspend(dev);
1962
1963 /* Keep the PHY up if we use Wake-on-Lan. */
1964 if (!device_may_wakeup(dev)) {
1965 rk_gmac_powerdown(bsp_priv);
1966 bsp_priv->suspended = true;
1967 }
1968
1969 return ret;
1970 }
1971
rk_gmac_resume(struct device * dev)1972 static int rk_gmac_resume(struct device *dev)
1973 {
1974 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1975
1976 /* The PHY was up for Wake-on-Lan. */
1977 if (bsp_priv->suspended) {
1978 rk_gmac_powerup(bsp_priv);
1979 bsp_priv->suspended = false;
1980 }
1981
1982 return stmmac_resume(dev);
1983 }
1984 #endif /* CONFIG_PM_SLEEP */
1985
1986 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1987
1988 static const struct of_device_id rk_gmac_dwmac_match[] = {
1989 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1990 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1991 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1992 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1993 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1994 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1995 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1996 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1997 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1998 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
1999 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2000 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
2001 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2002 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2003 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2004 { }
2005 };
2006 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
2007
2008 static struct platform_driver rk_gmac_dwmac_driver = {
2009 .probe = rk_gmac_probe,
2010 .remove = rk_gmac_remove,
2011 .driver = {
2012 .name = "rk_gmac-dwmac",
2013 .pm = &rk_gmac_pm_ops,
2014 .of_match_table = rk_gmac_dwmac_match,
2015 },
2016 };
2017 module_platform_driver(rk_gmac_dwmac_driver);
2018
2019 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
2020 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
2021 MODULE_LICENSE("GPL");
2022