1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <linux/module.h> 7 #include <linux/platform_device.h> 8 #include <linux/clk.h> 9 #include <linux/hw_bitfield.h> 10 #include <linux/mmc/host.h> 11 #include <linux/of_address.h> 12 #include <linux/mmc/slot-gpio.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/slab.h> 15 16 #include "dw_mmc.h" 17 #include "dw_mmc-pltfm.h" 18 19 #define RK3288_CLKGEN_DIV 2 20 #define SDMMC_TIMING_CON0 0x130 21 #define SDMMC_TIMING_CON1 0x134 22 #define SDMMC_MISC_CON 0x138 23 #define MEM_CLK_AUTOGATE_ENABLE BIT(5) 24 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 25 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 26 #define ROCKCHIP_MMC_DEGREE_OFFSET 1 27 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 28 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 29 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 30 31 static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; 32 33 struct dw_mci_rockchip_priv_data { 34 struct clk *drv_clk; 35 struct clk *sample_clk; 36 int default_sample_phase; 37 int num_phases; 38 bool internal_phase; 39 int sample_phase; 40 int drv_phase; 41 }; 42 43 /* 44 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 45 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 46 */ 47 static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample) 48 { 49 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; 50 u32 raw_value; 51 u16 degrees; 52 u32 delay_num = 0; 53 54 /* Constant signal, no measurable phase shift */ 55 if (!rate) 56 return 0; 57 58 if (sample) 59 raw_value = mci_readl(host, TIMING_CON1); 60 else 61 raw_value = mci_readl(host, TIMING_CON0); 62 63 raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET; 64 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 65 66 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 67 /* degrees/delaynum * 1000000 */ 68 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 69 36 * (rate / 10000); 70 71 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 72 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 73 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000); 74 } 75 76 return degrees % 360; 77 } 78 79 static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample) 80 { 81 struct dw_mci_rockchip_priv_data *priv = host->priv; 82 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; 83 84 if (priv->internal_phase) 85 return rockchip_mmc_get_internal_phase(host, sample); 86 else 87 return clk_get_phase(clock); 88 } 89 90 static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees) 91 { 92 unsigned long rate = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; 93 u8 nineties, remainder; 94 u8 delay_num; 95 u32 raw_value; 96 u32 delay; 97 98 /* 99 * The below calculation is based on the output clock from 100 * MMC host to the card, which expects the phase clock inherits 101 * the clock rate from its parent, namely the output clock 102 * provider of MMC host. However, things may go wrong if 103 * (1) It is orphan. 104 * (2) It is assigned to the wrong parent. 105 * 106 * This check help debug the case (1), which seems to be the 107 * most likely problem we often face and which makes it difficult 108 * for people to debug unstable mmc tuning results. 109 */ 110 if (!rate) { 111 dev_err(host->dev, "%s: invalid clk rate\n", __func__); 112 return -EINVAL; 113 } 114 115 nineties = degrees / 90; 116 remainder = (degrees % 90); 117 118 /* 119 * Due to the inexact nature of the "fine" delay, we might 120 * actually go non-monotonic. We don't go _too_ monotonic 121 * though, so we should be OK. Here are options of how we may 122 * work: 123 * 124 * Ideally we end up with: 125 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 126 * 127 * On one extreme (if delay is actually 44ps): 128 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 129 * The other (if delay is actually 77ps): 130 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 131 * 132 * It's possible we might make a delay that is up to 25 133 * degrees off from what we think we're making. That's OK 134 * though because we should be REALLY far from any bad range. 135 */ 136 137 /* 138 * Convert to delay; do a little extra work to make sure we 139 * don't overflow 32-bit / 64-bit numbers. 140 */ 141 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 142 delay *= remainder; 143 delay = DIV_ROUND_CLOSEST(delay, 144 (rate / 1000) * 36 * 145 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 146 147 delay_num = (u8) min_t(u32, delay, 255); 148 149 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 150 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 151 raw_value |= nineties; 152 153 if (sample) 154 mci_writel(host, TIMING_CON1, 155 FIELD_PREP_WM16(GENMASK(11, 1), raw_value)); 156 else 157 mci_writel(host, TIMING_CON0, 158 FIELD_PREP_WM16(GENMASK(11, 1), raw_value)); 159 160 dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n", 161 sample ? "sample" : "drv", degrees, delay_num, 162 rockchip_mmc_get_phase(host, sample) 163 ); 164 165 return 0; 166 } 167 168 static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees) 169 { 170 struct dw_mci_rockchip_priv_data *priv = host->priv; 171 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; 172 173 if (priv->internal_phase) 174 return rockchip_mmc_set_internal_phase(host, sample, degrees); 175 else 176 return clk_set_phase(clock, degrees); 177 } 178 179 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) 180 { 181 struct dw_mci_rockchip_priv_data *priv = host->priv; 182 struct mmc_clk_phase phase = host->phase_map.phase[ios->timing]; 183 int ret, sample_phase, drv_phase; 184 unsigned int cclkin; 185 u32 bus_hz; 186 187 if (ios->clock == 0) 188 return; 189 190 /* 191 * cclkin: source clock of mmc controller 192 * bus_hz: card interface clock generated by CLKGEN 193 * bus_hz = cclkin / RK3288_CLKGEN_DIV 194 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) 195 * 196 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC 197 * DDR52 8-bit mode. 198 */ 199 if (ios->bus_width == MMC_BUS_WIDTH_8 && 200 ios->timing == MMC_TIMING_MMC_DDR52) 201 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; 202 else 203 cclkin = ios->clock * RK3288_CLKGEN_DIV; 204 205 ret = clk_set_rate(host->ciu_clk, cclkin); 206 if (ret) 207 dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret); 208 209 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; 210 if (bus_hz != host->bus_hz) { 211 host->bus_hz = bus_hz; 212 /* force dw_mci_setup_bus() */ 213 host->current_speed = 0; 214 } 215 216 /* Make sure we use phases which we can enumerate with */ 217 if (!IS_ERR(priv->sample_clk)) { 218 /* Keep backward compatibility */ 219 if (ios->timing <= MMC_TIMING_SD_HS) { 220 sample_phase = phase.valid ? phase.in_deg : priv->default_sample_phase; 221 rockchip_mmc_set_phase(host, true, sample_phase); 222 } else if (phase.valid) { 223 rockchip_mmc_set_phase(host, true, phase.in_deg); 224 } 225 } 226 227 /* 228 * Set the drive phase offset based on speed mode to achieve hold times. 229 * 230 * NOTE: this is _not_ a value that is dynamically tuned and is also 231 * _not_ a value that will vary from board to board. It is a value 232 * that could vary between different SoC models if they had massively 233 * different output clock delays inside their dw_mmc IP block (delay_o), 234 * but since it's OK to overshoot a little we don't need to do complex 235 * calculations and can pick values that will just work for everyone. 236 * 237 * When picking values we'll stick with picking 0/90/180/270 since 238 * those can be made very accurately on all known Rockchip SoCs. 239 * 240 * Note that these values match values from the DesignWare Databook 241 * tables for the most part except for SDR12 and "ID mode". For those 242 * two modes the databook calculations assume a clock in of 50MHz. As 243 * seen above, we always use a clock in rate that is exactly the 244 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided 245 * back out before the controller sees it). 246 * 247 * From measurement of a single device, it appears that delay_o is 248 * about .5 ns. Since we try to leave a bit of margin, it's expected 249 * that numbers here will be fine even with much larger delay_o 250 * (the 1.4 ns assumed by the DesignWare Databook would result in the 251 * same results, for instance). 252 */ 253 if (!IS_ERR(priv->drv_clk)) { 254 /* 255 * In almost all cases a 90 degree phase offset will provide 256 * sufficient hold times across all valid input clock rates 257 * assuming delay_o is not absurd for a given SoC. We'll use 258 * that as a default. 259 */ 260 drv_phase = 90; 261 262 switch (ios->timing) { 263 case MMC_TIMING_MMC_DDR52: 264 /* 265 * Since clock in rate with MMC_DDR52 is doubled when 266 * bus width is 8 we need to double the phase offset 267 * to get the same timings. 268 */ 269 if (ios->bus_width == MMC_BUS_WIDTH_8) 270 drv_phase = 180; 271 break; 272 case MMC_TIMING_UHS_SDR104: 273 case MMC_TIMING_MMC_HS200: 274 /* 275 * In the case of 150 MHz clock (typical max for 276 * Rockchip SoCs), 90 degree offset will add a delay 277 * of 1.67 ns. That will meet min hold time of .8 ns 278 * as long as clock output delay is < .87 ns. On 279 * SoCs measured this seems to be OK, but it doesn't 280 * hurt to give margin here, so we use 180. 281 */ 282 drv_phase = 180; 283 break; 284 } 285 286 /* Use out phase from phase map first */ 287 if (phase.valid) 288 drv_phase = phase.out_deg; 289 rockchip_mmc_set_phase(host, false, drv_phase); 290 } 291 } 292 293 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \ 294 (DIV_ROUND_UP((i) * 360, num_phases)) 295 296 static int dw_mci_rk3288_execute_tuning(struct dw_mci *host, u32 opcode) 297 { 298 struct dw_mci_rockchip_priv_data *priv = host->priv; 299 struct mmc_host *mmc = host->mmc; 300 int ret = 0; 301 int i; 302 bool v, prev_v = 0, first_v; 303 struct range_t { 304 int start; 305 int end; /* inclusive */ 306 }; 307 struct range_t *ranges; 308 unsigned int range_count = 0; 309 int longest_range_len = -1; 310 int longest_range = -1; 311 int middle_phase; 312 int phase; 313 314 if (IS_ERR(priv->sample_clk)) { 315 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); 316 return -EIO; 317 } 318 319 ranges = kmalloc_objs(*ranges, priv->num_phases / 2 + 1); 320 if (!ranges) 321 return -ENOMEM; 322 323 /* Try each phase and extract good ranges */ 324 for (i = 0; i < priv->num_phases; ) { 325 rockchip_mmc_set_phase(host, true, 326 TUNING_ITERATION_TO_PHASE( 327 i, 328 priv->num_phases)); 329 330 v = !mmc_send_tuning(mmc, opcode, NULL); 331 332 if (i == 0) 333 first_v = v; 334 335 if ((!prev_v) && v) { 336 range_count++; 337 ranges[range_count-1].start = i; 338 } 339 if (v) { 340 ranges[range_count-1].end = i; 341 i++; 342 } else if (i == priv->num_phases - 1) { 343 /* No extra skipping rules if we're at the end */ 344 i++; 345 } else { 346 /* 347 * No need to check too close to an invalid 348 * one since testing bad phases is slow. Skip 349 * 20 degrees. 350 */ 351 i += DIV_ROUND_UP(20 * priv->num_phases, 360); 352 353 /* Always test the last one */ 354 if (i >= priv->num_phases) 355 i = priv->num_phases - 1; 356 } 357 358 prev_v = v; 359 } 360 361 if (range_count == 0) { 362 dev_warn(host->dev, "All phases bad!"); 363 ret = -EIO; 364 goto free; 365 } 366 367 /* wrap around case, merge the end points */ 368 if ((range_count > 1) && first_v && v) { 369 ranges[0].start = ranges[range_count-1].start; 370 range_count--; 371 } 372 373 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) { 374 rockchip_mmc_set_phase(host, true, priv->default_sample_phase); 375 376 dev_info(host->dev, "All phases work, using default phase %d.", 377 priv->default_sample_phase); 378 goto free; 379 } 380 381 /* Find the longest range */ 382 for (i = 0; i < range_count; i++) { 383 int len = (ranges[i].end - ranges[i].start + 1); 384 385 if (len < 0) 386 len += priv->num_phases; 387 388 if (longest_range_len < len) { 389 longest_range_len = len; 390 longest_range = i; 391 } 392 393 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", 394 TUNING_ITERATION_TO_PHASE(ranges[i].start, 395 priv->num_phases), 396 TUNING_ITERATION_TO_PHASE(ranges[i].end, 397 priv->num_phases), 398 len 399 ); 400 } 401 402 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", 403 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start, 404 priv->num_phases), 405 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end, 406 priv->num_phases), 407 longest_range_len 408 ); 409 410 middle_phase = ranges[longest_range].start + longest_range_len / 2; 411 middle_phase %= priv->num_phases; 412 phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases); 413 dev_info(host->dev, "Successfully tuned phase to %d\n", phase); 414 415 rockchip_mmc_set_phase(host, true, phase); 416 417 free: 418 kfree(ranges); 419 return ret; 420 } 421 422 static int dw_mci_common_parse_dt(struct dw_mci *host) 423 { 424 struct device_node *np = host->dev->of_node; 425 struct dw_mci_rockchip_priv_data *priv; 426 427 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); 428 if (!priv) 429 return -ENOMEM; 430 431 if (of_property_read_u32(np, "rockchip,desired-num-phases", 432 &priv->num_phases)) 433 priv->num_phases = 360; 434 435 if (of_property_read_u32(np, "rockchip,default-sample-phase", 436 &priv->default_sample_phase)) 437 priv->default_sample_phase = 0; 438 439 host->priv = priv; 440 441 return 0; 442 } 443 444 static int dw_mci_rk2928_parse_dt(struct dw_mci *host) 445 { 446 struct dw_mci_rockchip_priv_data *priv; 447 int err; 448 449 err = dw_mci_common_parse_dt(host); 450 if (err) 451 return err; 452 453 priv = host->priv; 454 455 priv->internal_phase = false; 456 457 return 0; 458 } 459 460 static int dw_mci_rk3288_parse_dt(struct dw_mci *host) 461 { 462 struct dw_mci_rockchip_priv_data *priv; 463 int err; 464 465 err = dw_mci_common_parse_dt(host); 466 if (err) 467 return err; 468 469 priv = host->priv; 470 471 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); 472 if (IS_ERR(priv->drv_clk)) 473 dev_dbg(host->dev, "ciu-drive not available\n"); 474 475 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); 476 if (IS_ERR(priv->sample_clk)) 477 dev_dbg(host->dev, "ciu-sample not available\n"); 478 479 priv->internal_phase = false; 480 481 return 0; 482 } 483 484 static int dw_mci_rk3576_parse_dt(struct dw_mci *host) 485 { 486 struct dw_mci_rockchip_priv_data *priv; 487 int err = dw_mci_common_parse_dt(host); 488 if (err) 489 return err; 490 491 priv = host->priv; 492 493 priv->internal_phase = true; 494 495 return 0; 496 } 497 498 static int dw_mci_rockchip_init(struct dw_mci *host) 499 { 500 struct dw_mci_rockchip_priv_data *priv = host->priv; 501 int ret, i; 502 503 /* SDIO irq is the 8th on Rockchip SoCs */ 504 host->sdio_irq = 8; 505 506 if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) { 507 host->bus_hz /= RK3288_CLKGEN_DIV; 508 509 /* clock driver will fail if the clock is less than the lowest source clock 510 * divided by the internal clock divider. Test for the lowest available 511 * clock and set the minimum freq to clock / clock divider. 512 */ 513 514 for (i = 0; i < ARRAY_SIZE(freqs); i++) { 515 ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV); 516 if (ret > 0) { 517 host->minimum_speed = ret / RK3288_CLKGEN_DIV; 518 break; 519 } 520 } 521 if (ret < 0) 522 dev_warn(host->dev, "no valid minimum freq: %d\n", ret); 523 } 524 525 if (priv->internal_phase) 526 mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); 527 528 return 0; 529 } 530 531 static const struct dw_mci_drv_data rk2928_drv_data = { 532 .init = dw_mci_rockchip_init, 533 .parse_dt = dw_mci_rk2928_parse_dt, 534 }; 535 536 static const struct dw_mci_drv_data rk3288_drv_data = { 537 .common_caps = MMC_CAP_CMD23, 538 .set_ios = dw_mci_rk3288_set_ios, 539 .execute_tuning = dw_mci_rk3288_execute_tuning, 540 .parse_dt = dw_mci_rk3288_parse_dt, 541 .init = dw_mci_rockchip_init, 542 }; 543 544 static const struct dw_mci_drv_data rk3576_drv_data = { 545 .common_caps = MMC_CAP_CMD23, 546 .set_ios = dw_mci_rk3288_set_ios, 547 .execute_tuning = dw_mci_rk3288_execute_tuning, 548 .parse_dt = dw_mci_rk3576_parse_dt, 549 .init = dw_mci_rockchip_init, 550 }; 551 552 static const struct of_device_id dw_mci_rockchip_match[] = { 553 { .compatible = "rockchip,rk2928-dw-mshc", 554 .data = &rk2928_drv_data }, 555 { .compatible = "rockchip,rk3288-dw-mshc", 556 .data = &rk3288_drv_data }, 557 { .compatible = "rockchip,rk3576-dw-mshc", 558 .data = &rk3576_drv_data }, 559 {}, 560 }; 561 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); 562 563 static int dw_mci_rockchip_probe(struct platform_device *pdev) 564 { 565 const struct dw_mci_drv_data *drv_data; 566 const struct of_device_id *match; 567 int ret; 568 569 if (!pdev->dev.of_node) 570 return -ENODEV; 571 572 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); 573 drv_data = match->data; 574 575 pm_runtime_get_noresume(&pdev->dev); 576 pm_runtime_set_active(&pdev->dev); 577 pm_runtime_enable(&pdev->dev); 578 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 579 pm_runtime_use_autosuspend(&pdev->dev); 580 581 ret = dw_mci_pltfm_register(pdev, drv_data); 582 if (ret) { 583 pm_runtime_disable(&pdev->dev); 584 pm_runtime_set_suspended(&pdev->dev); 585 pm_runtime_put_noidle(&pdev->dev); 586 return ret; 587 } 588 589 pm_runtime_put_autosuspend(&pdev->dev); 590 591 return 0; 592 } 593 594 static void dw_mci_rockchip_remove(struct platform_device *pdev) 595 { 596 pm_runtime_get_sync(&pdev->dev); 597 pm_runtime_disable(&pdev->dev); 598 pm_runtime_put_noidle(&pdev->dev); 599 600 dw_mci_pltfm_remove(pdev); 601 } 602 603 static int dw_mci_rockchip_runtime_suspend(struct device *dev) 604 { 605 struct platform_device *pdev = to_platform_device(dev); 606 struct dw_mci *host = platform_get_drvdata(pdev); 607 struct dw_mci_rockchip_priv_data *priv = host->priv; 608 609 if (priv->internal_phase) { 610 priv->sample_phase = rockchip_mmc_get_phase(host, true); 611 priv->drv_phase = rockchip_mmc_get_phase(host, false); 612 } 613 614 return dw_mci_runtime_suspend(dev); 615 } 616 617 static int dw_mci_rockchip_runtime_resume(struct device *dev) 618 { 619 struct platform_device *pdev = to_platform_device(dev); 620 struct dw_mci *host = platform_get_drvdata(pdev); 621 struct dw_mci_rockchip_priv_data *priv = host->priv; 622 int ret; 623 624 ret = dw_mci_runtime_resume(dev); 625 if (ret) 626 return ret; 627 628 if (priv->internal_phase) { 629 rockchip_mmc_set_phase(host, true, priv->sample_phase); 630 rockchip_mmc_set_phase(host, false, priv->drv_phase); 631 mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE); 632 } 633 634 return ret; 635 } 636 637 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = { 638 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 639 RUNTIME_PM_OPS(dw_mci_rockchip_runtime_suspend, dw_mci_rockchip_runtime_resume, NULL) 640 }; 641 642 static struct platform_driver dw_mci_rockchip_pltfm_driver = { 643 .probe = dw_mci_rockchip_probe, 644 .remove = dw_mci_rockchip_remove, 645 .driver = { 646 .name = "dwmmc_rockchip", 647 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 648 .of_match_table = dw_mci_rockchip_match, 649 .pm = pm_ptr(&dw_mci_rockchip_dev_pm_ops), 650 }, 651 }; 652 653 module_platform_driver(dw_mci_rockchip_pltfm_driver); 654 655 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 656 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); 657 MODULE_ALIAS("platform:dwmmc_rockchip"); 658 MODULE_LICENSE("GPL v2"); 659