1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/bus/stm32_firewall.h> 9 #include <linux/debugfs.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/string.h> 20 #include <linux/types.h> 21 22 /* 23 * RIFSC offset register 24 */ 25 #define RIFSC_RISC_SECCFGR0 0x10 26 #define RIFSC_RISC_PRIVCFGR0 0x30 27 #define RIFSC_RISC_PER0_CIDCFGR 0x100 28 #define RIFSC_RISC_PER0_SEMCR 0x104 29 #define RIFSC_RISC_REG0_ACFGR 0x900 30 #define RIFSC_RISC_REG3_AADDR 0x924 31 #define RIFSC_RISC_HWCFGR2 0xFEC 32 33 /* 34 * SEMCR register 35 */ 36 #define SEMCR_MUTEX BIT(0) 37 38 /* 39 * HWCFGR2 register 40 */ 41 #define HWCFGR2_CONF1_MASK GENMASK(15, 0) 42 #define HWCFGR2_CONF2_MASK GENMASK(23, 16) 43 #define HWCFGR2_CONF3_MASK GENMASK(31, 24) 44 45 /* 46 * RIFSC miscellaneous 47 */ 48 #define RIFSC_RISC_CFEN_MASK BIT(0) 49 #define RIFSC_RISC_SEM_EN_MASK BIT(1) 50 #define RIFSC_RISC_SCID_MASK GENMASK(6, 4) 51 #define RIFSC_RISC_SEML_SHIFT 16 52 #define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) 53 #define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24) 54 55 #define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ 56 RIFSC_RISC_SEM_EN_MASK | \ 57 RIFSC_RISC_SCID_MASK | \ 58 RIFSC_RISC_SEMWL_MASK) 59 60 #define IDS_PER_RISC_SEC_PRIV_REGS 32 61 62 /* RIF miscellaneous */ 63 /* 64 * CIDCFGR register fields 65 */ 66 #define CIDCFGR_CFEN BIT(0) 67 #define CIDCFGR_SEMEN BIT(1) 68 #define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x)) 69 70 #define SEMWL_SHIFT 16 71 72 /* Compartiment IDs */ 73 #define RIF_CID0 0x0 74 #define RIF_CID1 0x1 75 76 #if defined(CONFIG_DEBUG_FS) 77 #define RIFSC_RISUP_ENTRIES 128 78 #define RIFSC_RIMU_ENTRIES 16 79 #define RIFSC_RISAL_SUBREGIONS 2 80 #define RIFSC_RISAL_GRANULARITY 8 81 82 #define RIFSC_RIMC_ATTR0 0xC10 83 84 #define RIFSC_RIMC_CIDSEL BIT(2) 85 #define RIFSC_RIMC_MCID_MASK GENMASK(6, 4) 86 #define RIFSC_RIMC_MSEC BIT(8) 87 #define RIFSC_RIMC_MPRIV BIT(9) 88 89 #define RIFSC_RISC_SRCID_MASK GENMASK(6, 4) 90 #define RIFSC_RISC_SRPRIV BIT(9) 91 #define RIFSC_RISC_SRSEC BIT(8) 92 #define RIFSC_RISC_SRRLOCK BIT(1) 93 #define RIFSC_RISC_SREN BIT(0) 94 #define RIFSC_RISC_SRLENGTH_MASK GENMASK(27, 16) 95 #define RIFSC_RISC_SRSTART_MASK GENMASK(10, 0) 96 97 static const char *stm32mp21_rifsc_rimu_names[RIFSC_RIMU_ENTRIES] = { 98 "ETR", 99 "SDMMC1", 100 "SDMMC2", 101 "SDMMC3", 102 "OTG_HS", 103 "USBH", 104 "ETH1", 105 "ETH2", 106 "RESERVED", 107 "RESERVED", 108 "DCMIPP", 109 "LTDC_L1/L2", 110 "LTDC_L3", 111 "RESERVED", 112 "RESERVED", 113 "RESERVED", 114 }; 115 116 static const char *stm32mp25_rifsc_rimu_names[RIFSC_RIMU_ENTRIES] = { 117 "ETR", 118 "SDMMC1", 119 "SDMMC2", 120 "SDMMC3", 121 "USB3DR", 122 "USBH", 123 "ETH1", 124 "ETH2", 125 "PCIE", 126 "GPU", 127 "DMCIPP", 128 "LTDC_L0/L1", 129 "LTDC_L2", 130 "LTDC_ROT", 131 "VDEC", 132 "VENC" 133 }; 134 135 static const char *stm32mp21_rifsc_risup_names[RIFSC_RISUP_ENTRIES] = { 136 "TIM1", 137 "TIM2", 138 "TIM3", 139 "TIM4", 140 "TIM5", 141 "TIM6", 142 "TIM7", 143 "TIM8", 144 "TIM10", 145 "TIM11", 146 "TIM12", 147 "TIM13", 148 "TIM14", 149 "TIM15", 150 "TIM16", 151 "TIM17", 152 "RESERVED", 153 "LPTIM1", 154 "LPTIM2", 155 "LPTIM3", 156 "LPTIM4", 157 "LPTIM5", 158 "SPI1", 159 "SPI2", 160 "SPI3", 161 "SPI4", 162 "SPI5", 163 "SPI6", 164 "RESERVED", 165 "RESERVED", 166 "SPDIFRX", 167 "USART1", 168 "USART2", 169 "USART3", 170 "UART4", 171 "UART5", 172 "USART6", 173 "UART7", 174 "RESERVED", 175 "RESERVED", 176 "LPUART1", 177 "I2C1", 178 "I2C2", 179 "I2C3", 180 "RESERVED", 181 "RESERVED", 182 "RESERVED", 183 "RESERVED", 184 "RESERVED", 185 "SAI1", 186 "SAI2", 187 "SAI3", 188 "SAI4", 189 "RESERVED", 190 "MDF1", 191 "RESERVED", 192 "FDCAN", 193 "HDP", 194 "ADC1", 195 "ADC2", 196 "ETH1", 197 "ETH2", 198 "RESERVED", 199 "USBH", 200 "RESERVED", 201 "RESERVED", 202 "OTG_HS", 203 "DDRPERFM", 204 "RESERVED", 205 "RESERVED", 206 "RESERVED", 207 "RESERVED", 208 "RESERVED", 209 "STGEN", 210 "OCTOSPI1", 211 "RESERVED", 212 "SDMMC1", 213 "SDMMC2", 214 "SDMMC3", 215 "RESERVED", 216 "LTDC_CMN", 217 "RESERVED", 218 "RESERVED", 219 "RESERVED", 220 "RESERVED", 221 "RESERVED", 222 "CSI", 223 "DCMIPP", 224 "DCMI_PSSI", 225 "RESERVED", 226 "RESERVED", 227 "RESERVED", 228 "RNG1", 229 "RNG2", 230 "PKA", 231 "SAES", 232 "HASH1", 233 "HASH2", 234 "CRYP1", 235 "CRYP2", 236 "IWDG1", 237 "IWDG2", 238 "IWDG3", 239 "IWDG4", 240 "WWDG1", 241 "RESERVED", 242 "VREFBUF", 243 "DTS", 244 "RAMCFG", 245 "CRC", 246 "SERC", 247 "RESERVED", 248 "RESERVED", 249 "RESERVED", 250 "I3C1", 251 "I3C2", 252 "I3C3", 253 "RESERVED", 254 "ICACHE_DCACHE", 255 "LTDC_L1L2", 256 "LTDC_L3", 257 "RESERVED", 258 "RESERVED", 259 "RESERVED", 260 "RESERVED", 261 "OTFDEC1", 262 "RESERVED", 263 "IAC", 264 }; 265 266 static const char *stm32mp25_rifsc_risup_names[RIFSC_RISUP_ENTRIES] = { 267 "TIM1", 268 "TIM2", 269 "TIM3", 270 "TIM4", 271 "TIM5", 272 "TIM6", 273 "TIM7", 274 "TIM8", 275 "TIM10", 276 "TIM11", 277 "TIM12", 278 "TIM13", 279 "TIM14", 280 "TIM15", 281 "TIM16", 282 "TIM17", 283 "TIM20", 284 "LPTIM1", 285 "LPTIM2", 286 "LPTIM3", 287 "LPTIM4", 288 "LPTIM5", 289 "SPI1", 290 "SPI2", 291 "SPI3", 292 "SPI4", 293 "SPI5", 294 "SPI6", 295 "SPI7", 296 "SPI8", 297 "SPDIFRX", 298 "USART1", 299 "USART2", 300 "USART3", 301 "UART4", 302 "UART5", 303 "USART6", 304 "UART7", 305 "UART8", 306 "UART9", 307 "LPUART1", 308 "I2C1", 309 "I2C2", 310 "I2C3", 311 "I2C4", 312 "I2C5", 313 "I2C6", 314 "I2C7", 315 "I2C8", 316 "SAI1", 317 "SAI2", 318 "SAI3", 319 "SAI4", 320 "RESERVED", 321 "MDF1", 322 "ADF1", 323 "FDCAN", 324 "HDP", 325 "ADC12", 326 "ADC3", 327 "ETH1", 328 "ETH2", 329 "RESERVED", 330 "USBH", 331 "RESERVED", 332 "RESERVED", 333 "USB3DR", 334 "COMBOPHY", 335 "PCIE", 336 "UCPD1", 337 "ETHSW_DEIP", 338 "ETHSW_ACM_CF", 339 "ETHSW_ACM_MSGBU", 340 "STGEN", 341 "OCTOSPI1", 342 "OCTOSPI2", 343 "SDMMC1", 344 "SDMMC2", 345 "SDMMC3", 346 "GPU", 347 "LTDC_CMN", 348 "DSI_CMN", 349 "RESERVED", 350 "RESERVED", 351 "LVDS", 352 "RESERVED", 353 "CSI", 354 "DCMIPP", 355 "DCMI_PSSI", 356 "VDEC", 357 "VENC", 358 "RESERVED", 359 "RNG", 360 "PKA", 361 "SAES", 362 "HASH", 363 "CRYP1", 364 "CRYP2", 365 "IWDG1", 366 "IWDG2", 367 "IWDG3", 368 "IWDG4", 369 "IWDG5", 370 "WWDG1", 371 "WWDG2", 372 "RESERVED", 373 "VREFBUF", 374 "DTS", 375 "RAMCFG", 376 "CRC", 377 "SERC", 378 "OCTOSPIM", 379 "GICV2M", 380 "RESERVED", 381 "I3C1", 382 "I3C2", 383 "I3C3", 384 "I3C4", 385 "ICACHE_DCACHE", 386 "LTDC_L0L1", 387 "LTDC_L2", 388 "LTDC_ROT", 389 "DSI_TRIG", 390 "DSI_RDFIFO", 391 "RESERVED", 392 "OTFDEC1", 393 "OTFDEC2", 394 "IAC", 395 }; 396 struct rifsc_risup_debug_data { 397 char dev_name[15]; 398 u8 dev_cid; 399 u8 dev_sem_cids; 400 u8 dev_id; 401 bool dev_cid_filt_en; 402 bool dev_sem_en; 403 bool dev_priv; 404 bool dev_sec; 405 }; 406 407 struct rifsc_rimu_debug_data { 408 char m_name[11]; 409 u8 m_cid; 410 bool cidsel; 411 bool m_sec; 412 bool m_priv; 413 }; 414 415 struct rifsc_subreg_debug_data { 416 bool sr_sec; 417 bool sr_priv; 418 u8 sr_cid; 419 bool sr_rlock; 420 bool sr_enable; 421 u16 sr_start; 422 u16 sr_length; 423 }; 424 425 struct stm32_rifsc_resources_names { 426 const char **device_names; 427 const char **initiator_names; 428 }; 429 struct rifsc_dbg_private { 430 const struct stm32_rifsc_resources_names *res_names; 431 void __iomem *mmio; 432 unsigned int nb_risup; 433 unsigned int nb_rimu; 434 unsigned int nb_risal; 435 }; 436 437 static const struct stm32_rifsc_resources_names rifsc_mp21_res_names = { 438 .device_names = stm32mp21_rifsc_risup_names, 439 .initiator_names = stm32mp21_rifsc_rimu_names, 440 }; 441 442 static const struct stm32_rifsc_resources_names rifsc_mp25_res_names = { 443 .device_names = stm32mp25_rifsc_risup_names, 444 .initiator_names = stm32mp25_rifsc_rimu_names, 445 }; 446 447 static void stm32_rifsc_fill_rimu_dbg_entry(struct rifsc_dbg_private *rifsc, 448 struct rifsc_rimu_debug_data *dbg_entry, int i) 449 { 450 const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names; 451 u32 rimc_attr = readl_relaxed(rifsc->mmio + RIFSC_RIMC_ATTR0 + 0x4 * i); 452 453 strscpy(dbg_entry->m_name, dbg_names->initiator_names[i]); 454 dbg_entry->m_cid = FIELD_GET(RIFSC_RIMC_MCID_MASK, rimc_attr); 455 dbg_entry->cidsel = rimc_attr & RIFSC_RIMC_CIDSEL; 456 dbg_entry->m_sec = rimc_attr & RIFSC_RIMC_MSEC; 457 dbg_entry->m_priv = rimc_attr & RIFSC_RIMC_MPRIV; 458 } 459 460 static void stm32_rifsc_fill_dev_dbg_entry(struct rifsc_dbg_private *rifsc, 461 struct rifsc_risup_debug_data *dbg_entry, int i) 462 { 463 const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names; 464 u32 cid_cfgr, sec_cfgr, priv_cfgr; 465 u8 reg_id = i / IDS_PER_RISC_SEC_PRIV_REGS; 466 u8 reg_offset = i % IDS_PER_RISC_SEC_PRIV_REGS; 467 468 cid_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * i); 469 sec_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 470 priv_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PRIVCFGR0 + 0x4 * reg_id); 471 472 strscpy(dbg_entry->dev_name, dbg_names->device_names[i]); 473 dbg_entry->dev_id = i; 474 dbg_entry->dev_cid_filt_en = cid_cfgr & CIDCFGR_CFEN; 475 dbg_entry->dev_sem_en = cid_cfgr & CIDCFGR_SEMEN; 476 dbg_entry->dev_cid = FIELD_GET(RIFSC_RISC_SCID_MASK, cid_cfgr); 477 dbg_entry->dev_sem_cids = FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_cfgr); 478 dbg_entry->dev_sec = sec_cfgr & BIT(reg_offset) ? true : false; 479 dbg_entry->dev_priv = priv_cfgr & BIT(reg_offset) ? true : false; 480 } 481 482 483 static void stm32_rifsc_fill_subreg_dbg_entry(struct rifsc_dbg_private *rifsc, 484 struct rifsc_subreg_debug_data *dbg_entry, int i, 485 int j) 486 { 487 u32 risc_xcfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG0_ACFGR + 0x10 * i + 0x8 * j); 488 u32 risc_xaddr; 489 490 dbg_entry->sr_sec = risc_xcfgr & RIFSC_RISC_SRSEC; 491 dbg_entry->sr_priv = risc_xcfgr & RIFSC_RISC_SRPRIV; 492 dbg_entry->sr_cid = FIELD_GET(RIFSC_RISC_SRCID_MASK, risc_xcfgr); 493 dbg_entry->sr_rlock = risc_xcfgr & RIFSC_RISC_SRRLOCK; 494 dbg_entry->sr_enable = risc_xcfgr & RIFSC_RISC_SREN; 495 if (i == 2) { 496 risc_xaddr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG3_AADDR + 0x8 * j); 497 dbg_entry->sr_length = FIELD_GET(RIFSC_RISC_SRLENGTH_MASK, risc_xaddr); 498 dbg_entry->sr_start = FIELD_GET(RIFSC_RISC_SRSTART_MASK, risc_xaddr); 499 } else { 500 dbg_entry->sr_start = 0; 501 dbg_entry->sr_length = U16_MAX; 502 } 503 } 504 505 static int stm32_rifsc_conf_dump_show(struct seq_file *s, void *data) 506 { 507 struct rifsc_dbg_private *rifsc = (struct rifsc_dbg_private *)s->private; 508 int i, j; 509 510 seq_puts(s, "\n=============================================\n"); 511 seq_puts(s, " RIFSC dump\n"); 512 seq_puts(s, "=============================================\n\n"); 513 514 seq_puts(s, "\n=============================================\n"); 515 seq_puts(s, " RISUP dump\n"); 516 seq_puts(s, "=============================================\n"); 517 518 seq_printf(s, "\n| %-15s |", "Peripheral name"); 519 seq_puts(s, "| Firewall ID |"); 520 seq_puts(s, "| N/SECURE |"); 521 seq_puts(s, "| N/PRIVILEGED |"); 522 seq_puts(s, "| CID filtering |"); 523 seq_puts(s, "| Semaphore mode |"); 524 seq_puts(s, "| SCID |"); 525 seq_printf(s, "| %7s |\n", "SEMWL"); 526 527 for (i = 0; i < RIFSC_RISUP_ENTRIES && i < rifsc->nb_risup; i++) { 528 struct rifsc_risup_debug_data d_dbg_entry; 529 530 stm32_rifsc_fill_dev_dbg_entry(rifsc, &d_dbg_entry, i); 531 532 seq_printf(s, "| %-15s |", d_dbg_entry.dev_name); 533 seq_printf(s, "| %-11d |", d_dbg_entry.dev_id); 534 seq_printf(s, "| %-8s |", d_dbg_entry.dev_sec ? "SEC" : "NSEC"); 535 seq_printf(s, "| %-12s |", d_dbg_entry.dev_priv ? "PRIV" : "NPRIV"); 536 seq_printf(s, "| %-13s |", str_enabled_disabled(d_dbg_entry.dev_cid_filt_en)); 537 seq_printf(s, "| %-14s |", str_enabled_disabled(d_dbg_entry.dev_sem_en)); 538 seq_printf(s, "| %-4d |", d_dbg_entry.dev_cid); 539 seq_printf(s, "| %#-7x |\n", d_dbg_entry.dev_sem_cids); 540 } 541 542 seq_puts(s, "\n=============================================\n"); 543 seq_puts(s, " RIMU dump\n"); 544 seq_puts(s, "=============================================\n"); 545 546 seq_puts(s, "| RIMU's name |"); 547 seq_puts(s, "| CIDSEL |"); 548 seq_puts(s, "| MCID |"); 549 seq_puts(s, "| N/SECURE |"); 550 seq_puts(s, "| N/PRIVILEGED |\n"); 551 552 for (i = 0; i < RIFSC_RIMU_ENTRIES && rifsc->nb_rimu; i++) { 553 struct rifsc_rimu_debug_data m_dbg_entry; 554 555 stm32_rifsc_fill_rimu_dbg_entry(rifsc, &m_dbg_entry, i); 556 557 seq_printf(s, "| %-11s |", m_dbg_entry.m_name); 558 seq_printf(s, "| %-6s |", m_dbg_entry.cidsel ? "CIDSEL" : ""); 559 seq_printf(s, "| %-4d |", m_dbg_entry.m_cid); 560 seq_printf(s, "| %-8s |", m_dbg_entry.m_sec ? "SEC" : "NSEC"); 561 seq_printf(s, "| %-12s |\n", m_dbg_entry.m_priv ? "PRIV" : "NPRIV"); 562 } 563 564 if (rifsc->nb_risal > 0) { 565 seq_puts(s, "\n=============================================\n"); 566 seq_puts(s, " RISAL dump\n"); 567 seq_puts(s, "=============================================\n"); 568 569 seq_puts(s, "| Memory |"); 570 seq_puts(s, "| Subreg. |"); 571 seq_puts(s, "| N/SECURE |"); 572 seq_puts(s, "| N/PRIVILEGED |"); 573 seq_puts(s, "| Subreg. CID |"); 574 seq_puts(s, "| Resource lock |"); 575 seq_puts(s, "| Subreg. enable |"); 576 seq_puts(s, "| Subreg. start |"); 577 seq_puts(s, "| Subreg. end |\n"); 578 579 for (i = 0; i < rifsc->nb_risal; i++) { 580 for (j = 0; j < RIFSC_RISAL_SUBREGIONS; j++) { 581 struct rifsc_subreg_debug_data sr_dbg_entry; 582 583 stm32_rifsc_fill_subreg_dbg_entry(rifsc, &sr_dbg_entry, i, j); 584 585 seq_printf(s, "| LPSRAM%1d |", i + 1); 586 seq_printf(s, "| %1s |", (j == 0) ? "A" : "B"); 587 seq_printf(s, "| %-8s |", sr_dbg_entry.sr_sec ? "SEC" : "NSEC"); 588 seq_printf(s, "| %-12s |", sr_dbg_entry.sr_priv ? "PRIV" : "NPRIV"); 589 seq_printf(s, "| 0x%-9x |", sr_dbg_entry.sr_cid); 590 seq_printf(s, "| %-13s |", 591 sr_dbg_entry.sr_rlock ? "locked (1)" : "unlocked (0)"); 592 seq_printf(s, "| %-14s |", 593 str_enabled_disabled(sr_dbg_entry.sr_enable)); 594 seq_printf(s, "| 0x%-11x |", sr_dbg_entry.sr_start); 595 seq_printf(s, "| 0x%-11x |\n", sr_dbg_entry.sr_start + 596 sr_dbg_entry.sr_length - 1); 597 } 598 } 599 } 600 601 return 0; 602 } 603 DEFINE_SHOW_ATTRIBUTE(stm32_rifsc_conf_dump); 604 605 static int stm32_rifsc_register_debugfs(struct stm32_firewall_controller *rifsc_controller, 606 u32 nb_risup, u32 nb_rimu, u32 nb_risal) 607 { 608 struct rifsc_dbg_private *rifsc_priv; 609 struct dentry *root = NULL; 610 611 rifsc_priv = devm_kzalloc(rifsc_controller->dev, sizeof(*rifsc_priv), GFP_KERNEL); 612 if (!rifsc_priv) 613 return -ENOMEM; 614 615 rifsc_priv->mmio = rifsc_controller->mmio; 616 rifsc_priv->nb_risup = nb_risup; 617 rifsc_priv->nb_rimu = nb_rimu; 618 rifsc_priv->nb_risal = nb_risal; 619 rifsc_priv->res_names = of_device_get_match_data(rifsc_controller->dev); 620 621 root = debugfs_lookup("stm32_firewall", NULL); 622 if (!root) 623 root = debugfs_create_dir("stm32_firewall", NULL); 624 625 if (IS_ERR(root)) 626 return PTR_ERR(root); 627 628 debugfs_create_file("rifsc", 0444, root, rifsc_priv, &stm32_rifsc_conf_dump_fops); 629 630 return 0; 631 } 632 #endif /* defined(CONFIG_DEBUG_FS) */ 633 634 static bool stm32_rifsc_is_semaphore_available(void __iomem *addr) 635 { 636 return !(readl(addr) & SEMCR_MUTEX); 637 } 638 639 static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, 640 int id) 641 { 642 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; 643 644 writel(SEMCR_MUTEX, addr); 645 646 /* Check that CID1 has the semaphore */ 647 if (stm32_rifsc_is_semaphore_available(addr) || 648 FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1) 649 return -EACCES; 650 651 return 0; 652 } 653 654 static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, 655 int id) 656 { 657 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; 658 659 if (stm32_rifsc_is_semaphore_available(addr)) 660 return; 661 662 writel(SEMCR_MUTEX, addr); 663 664 /* Ok if another compartment takes the semaphore before the check */ 665 WARN_ON(!stm32_rifsc_is_semaphore_available(addr) && 666 FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1); 667 } 668 669 static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) 670 { 671 struct stm32_firewall_controller *rifsc_controller = ctrl; 672 u32 reg_offset, reg_id, sec_reg_value, cid_reg_value; 673 int rc; 674 675 if (firewall_id >= rifsc_controller->max_entries) { 676 dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id); 677 return -EINVAL; 678 } 679 680 /* 681 * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for 682 * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register 683 * per peripheral 684 */ 685 reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS; 686 reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS; 687 sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 688 cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); 689 690 /* Check security configuration */ 691 if (sec_reg_value & BIT(reg_offset)) { 692 dev_dbg(rifsc_controller->dev, 693 "Invalid security configuration for peripheral: %d\n", firewall_id); 694 return -EACCES; 695 } 696 697 /* Skip CID check if CID filtering isn't enabled */ 698 if (!(cid_reg_value & CIDCFGR_CFEN)) 699 goto skip_cid_check; 700 701 /* First check conditions for semaphore mode, which doesn't take into account static CID. */ 702 if (cid_reg_value & CIDCFGR_SEMEN) { 703 if (!(cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT))) { 704 dev_dbg(rifsc_controller->dev, 705 "Invalid bus semaphore configuration: index %d\n", firewall_id); 706 return -EACCES; 707 } 708 709 rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id); 710 if (rc) { 711 dev_dbg(rifsc_controller->dev, 712 "Couldn't acquire semaphore for peripheral: %d\n", firewall_id); 713 return rc; 714 } 715 } else if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { 716 dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n", 717 firewall_id); 718 return -EACCES; 719 } 720 721 skip_cid_check: 722 return 0; 723 } 724 725 static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) 726 { 727 stm32_rif_release_semaphore(ctrl, firewall_id); 728 } 729 730 static int stm32_rifsc_probe(struct platform_device *pdev) 731 { 732 struct stm32_firewall_controller *rifsc_controller; 733 struct device_node *np = pdev->dev.of_node; 734 u32 nb_risup, nb_rimu, nb_risal; 735 struct resource *res; 736 void __iomem *mmio; 737 int rc; 738 739 rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL); 740 if (!rifsc_controller) 741 return -ENOMEM; 742 743 mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 744 if (IS_ERR(mmio)) 745 return PTR_ERR(mmio); 746 747 rifsc_controller->dev = &pdev->dev; 748 rifsc_controller->mmio = mmio; 749 rifsc_controller->name = dev_driver_string(rifsc_controller->dev); 750 rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; 751 rifsc_controller->grant_access = stm32_rifsc_grant_access; 752 rifsc_controller->release_access = stm32_rifsc_release_access; 753 754 /* Get number of RIFSC entries*/ 755 nb_risup = FIELD_GET(HWCFGR2_CONF1_MASK, 756 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); 757 nb_rimu = FIELD_GET(HWCFGR2_CONF2_MASK, 758 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); 759 nb_risal = FIELD_GET(HWCFGR2_CONF3_MASK, 760 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); 761 /* 762 * On STM32MP21, RIFSC_RISC_HWCFGR2 shows an incorrect number of RISAL (NUM_RISAL is 3 763 * instead of 0). A software workaround is implemented using the st,mem-map property in the 764 * device tree. This property is absent or left empty if there is no RISAL. 765 */ 766 if (of_device_is_compatible(np, "st,stm32mp21-rifsc")) 767 nb_risal = 0; 768 rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal; 769 770 platform_set_drvdata(pdev, rifsc_controller); 771 772 rc = stm32_firewall_controller_register(rifsc_controller); 773 if (rc) { 774 dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d", 775 rc); 776 return rc; 777 } 778 779 rc = stm32_firewall_populate_bus(rifsc_controller); 780 if (rc) { 781 dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d", 782 rc); 783 return rc; 784 } 785 786 #if defined(CONFIG_DEBUG_FS) 787 rc = stm32_rifsc_register_debugfs(rifsc_controller, nb_risup, nb_rimu, nb_risal); 788 if (rc) 789 return dev_err_probe(rifsc_controller->dev, rc, "Failed creating debugfs entry\n"); 790 #endif 791 792 /* Populate all allowed nodes */ 793 return of_platform_populate(np, NULL, NULL, &pdev->dev); 794 } 795 796 static const struct of_device_id stm32_rifsc_of_match[] = { 797 { 798 .compatible = "st,stm32mp25-rifsc", 799 #if defined(CONFIG_DEBUG_FS) 800 .data = &rifsc_mp25_res_names, 801 #endif 802 }, 803 { 804 .compatible = "st,stm32mp21-rifsc", 805 #if defined(CONFIG_DEBUG_FS) 806 .data = &rifsc_mp21_res_names, 807 #endif 808 }, 809 {} 810 }; 811 MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match); 812 813 static struct platform_driver stm32_rifsc_driver = { 814 .probe = stm32_rifsc_probe, 815 .driver = { 816 .name = "stm32-rifsc", 817 .of_match_table = stm32_rifsc_of_match, 818 }, 819 }; 820 module_platform_driver(stm32_rifsc_driver); 821 822 MODULE_AUTHOR("Gatien Chevallier <gatien.chevallier@foss.st.com>"); 823 MODULE_DESCRIPTION("STMicroelectronics RIFSC driver"); 824 MODULE_LICENSE("GPL"); 825