1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023, MediaTek Inc. 4 * Copyright (c) 2023, BayLibre Inc. 5 */ 6 7 #ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ 8 #define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__ 9 10 /* 11 * CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are 12 * applicable to the three PHYs. Where differences exist, they are denoted by 13 * macro names using CSI0 and CSI1, the latter being applicable to CSI1 and 14 * CSI2 alike. 15 */ 16 17 #define MIPI_RX_ANA00_CSIXA 0x0000 18 #define RG_CSI0A_CPHY_EN BIT(0) 19 #define RG_CSIXA_EQ_PROTECT_EN BIT(1) 20 #define RG_CSIXA_BG_LPF_EN BIT(2) 21 #define RG_CSIXA_BG_CORE_EN BIT(3) 22 #define RG_CSIXA_DPHY_L0_CKMODE_EN BIT(5) 23 #define RG_CSIXA_DPHY_L0_CKSEL BIT(6) 24 #define RG_CSIXA_DPHY_L1_CKMODE_EN BIT(8) 25 #define RG_CSIXA_DPHY_L1_CKSEL BIT(9) 26 #define RG_CSIXA_DPHY_L2_CKMODE_EN BIT(11) 27 #define RG_CSIXA_DPHY_L2_CKSEL BIT(12) 28 29 #define MIPI_RX_ANA18_CSIXA 0x0018 30 #define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4) 31 #define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6) 32 #define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20) 33 #define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22) 34 #define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20) 35 #define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22) 36 #define RG_CSI1A_L0_EQ_IS GENMASK(5, 4) 37 #define RG_CSI1A_L0_EQ_BW GENMASK(7, 6) 38 #define RG_CSI1A_L1_EQ_IS GENMASK(21, 20) 39 #define RG_CSI1A_L1_EQ_BW GENMASK(23, 22) 40 #define RG_CSI1A_L2_EQ_IS GENMASK(5, 4) 41 #define RG_CSI1A_L2_EQ_BW GENMASK(7, 6) 42 43 #define MIPI_RX_ANA1C_CSIXA 0x001c 44 #define MIPI_RX_ANA20_CSI0A 0x0020 45 46 #define MIPI_RX_ANA24_CSIXA 0x0024 47 #define RG_CSIXA_RESERVE GENMASK(31, 24) 48 49 #define MIPI_RX_ANA40_CSIXA 0x0040 50 #define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0) 51 #define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4) 52 #define RG_CSIXA_CPHY_SPARE GENMASK(31, 16) 53 54 #define MIPI_RX_WRAPPER80_CSIXA 0x0080 55 #define CSR_CSI_RST_MODE GENMASK(17, 16) 56 57 #define MIPI_RX_ANAA8_CSIXA 0x00a8 58 #define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT BIT(0) 59 #define RG_CSIXA_DPHY_L1_BYTECK_INVERT BIT(1) 60 #define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT BIT(2) 61 62 #endif 63