1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-19, Linaro Limited
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/of_net.h>
7 #include <linux/platform_device.h>
8 #include <linux/phy.h>
9 #include <linux/phy/phy.h>
10
11 #include "stmmac.h"
12 #include "stmmac_platform.h"
13
14 #define RGMII_IO_MACRO_CONFIG 0x0
15 #define SDCC_HC_REG_DLL_CONFIG 0x4
16 #define SDCC_TEST_CTL 0x8
17 #define SDCC_HC_REG_DDR_CONFIG 0xC
18 #define SDCC_HC_REG_DLL_CONFIG2 0x10
19 #define SDC4_STATUS 0x14
20 #define SDCC_USR_CTL 0x18
21 #define RGMII_IO_MACRO_CONFIG2 0x1C
22 #define RGMII_IO_MACRO_DEBUG1 0x20
23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
24 #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4
25
26 /* RGMII_IO_MACRO_CONFIG fields */
27 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
28 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
29 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
30 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
31 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
32 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
33 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
34 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
35 #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
36 #define RGMII_CONFIG_PROG_SWAP BIT(1)
37 #define RGMII_CONFIG_DDR_MODE BIT(0)
38 #define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
39
40 /* SDCC_HC_REG_DLL_CONFIG fields */
41 #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
42 #define SDCC_DLL_CONFIG_PDN BIT(29)
43 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
44 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
45 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
46 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
47 #define SDCC_DLL_CONFIG_CDR_EN BIT(17)
48 #define SDCC_DLL_CONFIG_DLL_EN BIT(16)
49 #define SDCC_DLL_MCLK_GATING_EN BIT(5)
50 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
51
52 /* SDCC_HC_REG_DDR_CONFIG fields */
53 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
56 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
57 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9)
58 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
59
60 /* SDCC_HC_REG_DLL_CONFIG2 fields */
61 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
62 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
64 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
65 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
66
67 /* SDC4_STATUS bits */
68 #define SDC4_STATUS_DLL_LOCK BIT(7)
69
70 /* RGMII_IO_MACRO_CONFIG2 fields */
71 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
72 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
73 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
74 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
75 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
76 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
77 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
78
79 /* MAC_CTRL_REG bits */
80 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
81 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
82
83 /* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */
84 #define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3)
85
86 #define SGMII_10M_RX_CLK_DVDR 0x31
87
88 struct ethqos_emac_por {
89 unsigned int offset;
90 unsigned int value;
91 };
92
93 struct ethqos_emac_driver_data {
94 const struct ethqos_emac_por *por;
95 unsigned int num_por;
96 bool rgmii_config_loopback_en;
97 bool has_emac_ge_3;
98 const char *link_clk_name;
99 bool has_integrated_pcs;
100 u32 dma_addr_width;
101 struct dwmac4_addrs dwmac4_addrs;
102 bool needs_sgmii_loopback;
103 };
104
105 struct qcom_ethqos {
106 struct platform_device *pdev;
107 void __iomem *rgmii_base;
108 void __iomem *mac_base;
109 int (*configure_func)(struct qcom_ethqos *ethqos);
110
111 unsigned int link_clk_rate;
112 struct clk *link_clk;
113 struct phy *serdes_phy;
114 int speed;
115 int serdes_speed;
116 phy_interface_t phy_mode;
117
118 const struct ethqos_emac_por *por;
119 unsigned int num_por;
120 bool rgmii_config_loopback_en;
121 bool has_emac_ge_3;
122 bool needs_sgmii_loopback;
123 };
124
rgmii_readl(struct qcom_ethqos * ethqos,unsigned int offset)125 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
126 {
127 return readl(ethqos->rgmii_base + offset);
128 }
129
rgmii_writel(struct qcom_ethqos * ethqos,int value,unsigned int offset)130 static void rgmii_writel(struct qcom_ethqos *ethqos,
131 int value, unsigned int offset)
132 {
133 writel(value, ethqos->rgmii_base + offset);
134 }
135
rgmii_updatel(struct qcom_ethqos * ethqos,int mask,int val,unsigned int offset)136 static void rgmii_updatel(struct qcom_ethqos *ethqos,
137 int mask, int val, unsigned int offset)
138 {
139 unsigned int temp;
140
141 temp = rgmii_readl(ethqos, offset);
142 temp = (temp & ~(mask)) | val;
143 rgmii_writel(ethqos, temp, offset);
144 }
145
rgmii_dump(void * priv)146 static void rgmii_dump(void *priv)
147 {
148 struct qcom_ethqos *ethqos = priv;
149 struct device *dev = ðqos->pdev->dev;
150
151 dev_dbg(dev, "Rgmii register dump\n");
152 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n",
153 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
154 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
155 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
156 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
157 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
158 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
159 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
160 dev_dbg(dev, "SDC4_STATUS: %x\n",
161 rgmii_readl(ethqos, SDC4_STATUS));
162 dev_dbg(dev, "SDCC_USR_CTL: %x\n",
163 rgmii_readl(ethqos, SDCC_USR_CTL));
164 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
165 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
166 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
167 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
168 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
169 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
170 }
171
172 static void
ethqos_update_link_clk(struct qcom_ethqos * ethqos,int speed)173 ethqos_update_link_clk(struct qcom_ethqos *ethqos, int speed)
174 {
175 long rate;
176
177 if (!phy_interface_mode_is_rgmii(ethqos->phy_mode))
178 return;
179
180 rate = rgmii_clock(speed);
181 if (rate > 0)
182 ethqos->link_clk_rate = rate * 2;
183
184 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
185 }
186
187 static void
qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos * ethqos,bool enable)188 qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)
189 {
190 if (!ethqos->needs_sgmii_loopback ||
191 ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX)
192 return;
193
194 rgmii_updatel(ethqos,
195 SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN,
196 enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0,
197 EMAC_WRAPPER_SGMII_PHY_CNTRL1);
198 }
199
ethqos_set_func_clk_en(struct qcom_ethqos * ethqos)200 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
201 {
202 qcom_ethqos_set_sgmii_loopback(ethqos, true);
203 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
204 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
205 }
206
207 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
208 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
209 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
210 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
211 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
212 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
213 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
214 };
215
216 static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
217 .por = emac_v2_3_0_por,
218 .num_por = ARRAY_SIZE(emac_v2_3_0_por),
219 .rgmii_config_loopback_en = true,
220 .has_emac_ge_3 = false,
221 };
222
223 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
224 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
225 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
226 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
227 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
228 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
229 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
230 };
231
232 static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
233 .por = emac_v2_1_0_por,
234 .num_por = ARRAY_SIZE(emac_v2_1_0_por),
235 .rgmii_config_loopback_en = false,
236 .has_emac_ge_3 = false,
237 };
238
239 static const struct ethqos_emac_por emac_v3_0_0_por[] = {
240 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
241 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
242 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
243 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
244 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
245 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
246 };
247
248 static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
249 .por = emac_v3_0_0_por,
250 .num_por = ARRAY_SIZE(emac_v3_0_0_por),
251 .rgmii_config_loopback_en = false,
252 .has_emac_ge_3 = true,
253 .dwmac4_addrs = {
254 .dma_chan = 0x00008100,
255 .dma_chan_offset = 0x1000,
256 .mtl_chan = 0x00008000,
257 .mtl_chan_offset = 0x1000,
258 .mtl_ets_ctrl = 0x00008010,
259 .mtl_ets_ctrl_offset = 0x1000,
260 .mtl_txq_weight = 0x00008018,
261 .mtl_txq_weight_offset = 0x1000,
262 .mtl_send_slp_cred = 0x0000801c,
263 .mtl_send_slp_cred_offset = 0x1000,
264 .mtl_high_cred = 0x00008020,
265 .mtl_high_cred_offset = 0x1000,
266 .mtl_low_cred = 0x00008024,
267 .mtl_low_cred_offset = 0x1000,
268 },
269 };
270
271 static const struct ethqos_emac_por emac_v4_0_0_por[] = {
272 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
273 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
274 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
275 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
276 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
277 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
278 };
279
280 static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
281 .por = emac_v4_0_0_por,
282 .num_por = ARRAY_SIZE(emac_v4_0_0_por),
283 .rgmii_config_loopback_en = false,
284 .has_emac_ge_3 = true,
285 .link_clk_name = "phyaux",
286 .has_integrated_pcs = true,
287 .needs_sgmii_loopback = true,
288 .dma_addr_width = 36,
289 .dwmac4_addrs = {
290 .dma_chan = 0x00008100,
291 .dma_chan_offset = 0x1000,
292 .mtl_chan = 0x00008000,
293 .mtl_chan_offset = 0x1000,
294 .mtl_ets_ctrl = 0x00008010,
295 .mtl_ets_ctrl_offset = 0x1000,
296 .mtl_txq_weight = 0x00008018,
297 .mtl_txq_weight_offset = 0x1000,
298 .mtl_send_slp_cred = 0x0000801c,
299 .mtl_send_slp_cred_offset = 0x1000,
300 .mtl_high_cred = 0x00008020,
301 .mtl_high_cred_offset = 0x1000,
302 .mtl_low_cred = 0x00008024,
303 .mtl_low_cred_offset = 0x1000,
304 },
305 };
306
ethqos_dll_configure(struct qcom_ethqos * ethqos)307 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
308 {
309 struct device *dev = ðqos->pdev->dev;
310 unsigned int val;
311 int retry = 1000;
312
313 /* Set CDR_EN */
314 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
315 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
316
317 /* Set CDR_EXT_EN */
318 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
319 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
320
321 /* Clear CK_OUT_EN */
322 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
323 0, SDCC_HC_REG_DLL_CONFIG);
324
325 /* Set DLL_EN */
326 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
327 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
328
329 if (!ethqos->has_emac_ge_3) {
330 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
331 0, SDCC_HC_REG_DLL_CONFIG);
332
333 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
334 0, SDCC_HC_REG_DLL_CONFIG);
335 }
336
337 /* Wait for CK_OUT_EN clear */
338 do {
339 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
340 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
341 if (!val)
342 break;
343 mdelay(1);
344 retry--;
345 } while (retry > 0);
346 if (!retry)
347 dev_err(dev, "Clear CK_OUT_EN timedout\n");
348
349 /* Set CK_OUT_EN */
350 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
351 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
352
353 /* Wait for CK_OUT_EN set */
354 retry = 1000;
355 do {
356 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
357 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
358 if (val)
359 break;
360 mdelay(1);
361 retry--;
362 } while (retry > 0);
363 if (!retry)
364 dev_err(dev, "Set CK_OUT_EN timedout\n");
365
366 /* Set DDR_CAL_EN */
367 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
368 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
369
370 if (!ethqos->has_emac_ge_3) {
371 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
372 0, SDCC_HC_REG_DLL_CONFIG2);
373
374 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
375 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
376
377 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
378 BIT(2), SDCC_HC_REG_DLL_CONFIG2);
379
380 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
381 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
382 SDCC_HC_REG_DLL_CONFIG2);
383 }
384
385 return 0;
386 }
387
ethqos_rgmii_macro_init(struct qcom_ethqos * ethqos)388 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
389 {
390 struct device *dev = ðqos->pdev->dev;
391 int phase_shift;
392 int loopback;
393
394 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
395 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
396 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
397 phase_shift = 0;
398 else
399 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
400
401 /* Disable loopback mode */
402 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
403 0, RGMII_IO_MACRO_CONFIG2);
404
405 /* Determine if this platform wants loopback enabled after programming */
406 if (ethqos->rgmii_config_loopback_en)
407 loopback = RGMII_CONFIG_LOOPBACK_EN;
408 else
409 loopback = 0;
410
411 /* Select RGMII, write 0 to interface select */
412 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
413 0, RGMII_IO_MACRO_CONFIG);
414
415 switch (ethqos->speed) {
416 case SPEED_1000:
417 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
418 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
419 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
420 0, RGMII_IO_MACRO_CONFIG);
421 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
422 RGMII_CONFIG_POS_NEG_DATA_SEL,
423 RGMII_IO_MACRO_CONFIG);
424 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
425 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
426 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
427 0, RGMII_IO_MACRO_CONFIG2);
428
429 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
430 phase_shift, RGMII_IO_MACRO_CONFIG2);
431 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
432 0, RGMII_IO_MACRO_CONFIG2);
433 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
434 RGMII_CONFIG2_RX_PROG_SWAP,
435 RGMII_IO_MACRO_CONFIG2);
436
437 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
438 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
439 */
440 if (ethqos->has_emac_ge_3) {
441 /* 0.9 ns */
442 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
443 115, SDCC_HC_REG_DDR_CONFIG);
444 } else {
445 /* 1.8 ns */
446 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
447 57, SDCC_HC_REG_DDR_CONFIG);
448 }
449 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
450 SDCC_DDR_CONFIG_PRG_DLY_EN,
451 SDCC_HC_REG_DDR_CONFIG);
452 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
453 loopback, RGMII_IO_MACRO_CONFIG);
454 break;
455
456 case SPEED_100:
457 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
458 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
459 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
460 RGMII_CONFIG_BYPASS_TX_ID_EN,
461 RGMII_IO_MACRO_CONFIG);
462 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
463 0, RGMII_IO_MACRO_CONFIG);
464 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
465 0, RGMII_IO_MACRO_CONFIG);
466 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
467 0, RGMII_IO_MACRO_CONFIG2);
468 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
469 phase_shift, RGMII_IO_MACRO_CONFIG2);
470 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
471 BIT(6), RGMII_IO_MACRO_CONFIG);
472 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
473 0, RGMII_IO_MACRO_CONFIG2);
474
475 if (ethqos->has_emac_ge_3)
476 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
477 RGMII_CONFIG2_RX_PROG_SWAP,
478 RGMII_IO_MACRO_CONFIG2);
479 else
480 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
481 0, RGMII_IO_MACRO_CONFIG2);
482
483 /* Write 0x5 to PRG_RCLK_DLY_CODE */
484 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
485 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
486 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
487 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
488 SDCC_HC_REG_DDR_CONFIG);
489 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
490 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
491 SDCC_HC_REG_DDR_CONFIG);
492 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
493 loopback, RGMII_IO_MACRO_CONFIG);
494 break;
495
496 case SPEED_10:
497 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
498 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
499 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
500 RGMII_CONFIG_BYPASS_TX_ID_EN,
501 RGMII_IO_MACRO_CONFIG);
502 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
503 0, RGMII_IO_MACRO_CONFIG);
504 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
505 0, RGMII_IO_MACRO_CONFIG);
506 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
507 0, RGMII_IO_MACRO_CONFIG2);
508 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
509 phase_shift, RGMII_IO_MACRO_CONFIG2);
510 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
511 BIT(12) | GENMASK(9, 8),
512 RGMII_IO_MACRO_CONFIG);
513 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
514 0, RGMII_IO_MACRO_CONFIG2);
515 if (ethqos->has_emac_ge_3)
516 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
517 RGMII_CONFIG2_RX_PROG_SWAP,
518 RGMII_IO_MACRO_CONFIG2);
519 else
520 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
521 0, RGMII_IO_MACRO_CONFIG2);
522 /* Write 0x5 to PRG_RCLK_DLY_CODE */
523 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
524 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
525 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
526 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
527 SDCC_HC_REG_DDR_CONFIG);
528 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
529 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
530 SDCC_HC_REG_DDR_CONFIG);
531 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
532 loopback, RGMII_IO_MACRO_CONFIG);
533 break;
534 default:
535 dev_err(dev, "Invalid speed %d\n", ethqos->speed);
536 return -EINVAL;
537 }
538
539 return 0;
540 }
541
ethqos_configure_rgmii(struct qcom_ethqos * ethqos)542 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
543 {
544 struct device *dev = ðqos->pdev->dev;
545 volatile unsigned int dll_lock;
546 unsigned int i, retry = 1000;
547
548 /* Reset to POR values and enable clk */
549 for (i = 0; i < ethqos->num_por; i++)
550 rgmii_writel(ethqos, ethqos->por[i].value,
551 ethqos->por[i].offset);
552 ethqos_set_func_clk_en(ethqos);
553
554 /* Initialize the DLL first */
555
556 /* Set DLL_RST */
557 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
558 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
559
560 /* Set PDN */
561 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
562 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
563
564 if (ethqos->has_emac_ge_3) {
565 if (ethqos->speed == SPEED_1000) {
566 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
567 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
568 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
569 } else {
570 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
571 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
572 }
573 }
574
575 /* Clear DLL_RST */
576 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
577 SDCC_HC_REG_DLL_CONFIG);
578
579 /* Clear PDN */
580 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
581 SDCC_HC_REG_DLL_CONFIG);
582
583 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
584 /* Set DLL_EN */
585 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
586 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
587
588 /* Set CK_OUT_EN */
589 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
590 SDCC_DLL_CONFIG_CK_OUT_EN,
591 SDCC_HC_REG_DLL_CONFIG);
592
593 /* Set USR_CTL bit 26 with mask of 3 bits */
594 if (!ethqos->has_emac_ge_3)
595 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
596 SDCC_USR_CTL);
597
598 /* wait for DLL LOCK */
599 do {
600 mdelay(1);
601 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
602 if (dll_lock & SDC4_STATUS_DLL_LOCK)
603 break;
604 retry--;
605 } while (retry > 0);
606 if (!retry)
607 dev_err(dev, "Timeout while waiting for DLL lock\n");
608 }
609
610 if (ethqos->speed == SPEED_1000)
611 ethqos_dll_configure(ethqos);
612
613 ethqos_rgmii_macro_init(ethqos);
614
615 return 0;
616 }
617
ethqos_set_serdes_speed(struct qcom_ethqos * ethqos,int speed)618 static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed)
619 {
620 if (ethqos->serdes_speed != speed) {
621 phy_set_speed(ethqos->serdes_phy, speed);
622 ethqos->serdes_speed = speed;
623 }
624 }
625
626 /* On interface toggle MAC registers gets reset.
627 * Configure MAC block for SGMII on ethernet phy link up
628 */
ethqos_configure_sgmii(struct qcom_ethqos * ethqos)629 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
630 {
631 struct net_device *dev = platform_get_drvdata(ethqos->pdev);
632 struct stmmac_priv *priv = netdev_priv(dev);
633 int val;
634
635 val = readl(ethqos->mac_base + MAC_CTRL_REG);
636
637 switch (ethqos->speed) {
638 case SPEED_2500:
639 val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
640 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
641 RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
642 RGMII_IO_MACRO_CONFIG2);
643 ethqos_set_serdes_speed(ethqos, SPEED_2500);
644 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 0, 0, 0);
645 break;
646 case SPEED_1000:
647 val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
648 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
649 RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
650 RGMII_IO_MACRO_CONFIG2);
651 ethqos_set_serdes_speed(ethqos, SPEED_1000);
652 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0);
653 break;
654 case SPEED_100:
655 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
656 ethqos_set_serdes_speed(ethqos, SPEED_1000);
657 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0);
658 break;
659 case SPEED_10:
660 val |= ETHQOS_MAC_CTRL_PORT_SEL;
661 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
662 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
663 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,
664 SGMII_10M_RX_CLK_DVDR),
665 RGMII_IO_MACRO_CONFIG);
666 ethqos_set_serdes_speed(ethqos, SPEED_1000);
667 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, 0, 0);
668 break;
669 }
670
671 writel(val, ethqos->mac_base + MAC_CTRL_REG);
672
673 return val;
674 }
675
qcom_ethqos_speed_mode_2500(struct net_device * ndev,void * data)676 static void qcom_ethqos_speed_mode_2500(struct net_device *ndev, void *data)
677 {
678 struct stmmac_priv *priv = netdev_priv(ndev);
679
680 priv->plat->max_speed = 2500;
681 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
682 }
683
ethqos_configure(struct qcom_ethqos * ethqos)684 static int ethqos_configure(struct qcom_ethqos *ethqos)
685 {
686 return ethqos->configure_func(ethqos);
687 }
688
ethqos_fix_mac_speed(void * priv,int speed,unsigned int mode)689 static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode)
690 {
691 struct qcom_ethqos *ethqos = priv;
692
693 qcom_ethqos_set_sgmii_loopback(ethqos, false);
694 ethqos->speed = speed;
695 ethqos_update_link_clk(ethqos, speed);
696 ethqos_configure(ethqos);
697 }
698
qcom_ethqos_serdes_powerup(struct net_device * ndev,void * priv)699 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
700 {
701 struct qcom_ethqos *ethqos = priv;
702 int ret;
703
704 ret = phy_init(ethqos->serdes_phy);
705 if (ret)
706 return ret;
707
708 ret = phy_power_on(ethqos->serdes_phy);
709 if (ret)
710 return ret;
711
712 return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
713 }
714
qcom_ethqos_serdes_powerdown(struct net_device * ndev,void * priv)715 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
716 {
717 struct qcom_ethqos *ethqos = priv;
718
719 phy_power_off(ethqos->serdes_phy);
720 phy_exit(ethqos->serdes_phy);
721 }
722
ethqos_clks_config(void * priv,bool enabled)723 static int ethqos_clks_config(void *priv, bool enabled)
724 {
725 struct qcom_ethqos *ethqos = priv;
726 int ret = 0;
727
728 if (enabled) {
729 ret = clk_prepare_enable(ethqos->link_clk);
730 if (ret) {
731 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
732 return ret;
733 }
734
735 /* Enable functional clock to prevent DMA reset to timeout due
736 * to lacking PHY clock after the hardware block has been power
737 * cycled. The actual configuration will be adjusted once
738 * ethqos_fix_mac_speed() is invoked.
739 */
740 ethqos_set_func_clk_en(ethqos);
741 } else {
742 clk_disable_unprepare(ethqos->link_clk);
743 }
744
745 return ret;
746 }
747
ethqos_clks_disable(void * data)748 static void ethqos_clks_disable(void *data)
749 {
750 ethqos_clks_config(data, false);
751 }
752
ethqos_ptp_clk_freq_config(struct stmmac_priv * priv)753 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv)
754 {
755 struct plat_stmmacenet_data *plat_dat = priv->plat;
756 int err;
757
758 if (!plat_dat->clk_ptp_ref)
759 return;
760
761 /* Max the PTP ref clock out to get the best resolution possible */
762 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX);
763 if (err)
764 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err);
765 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref);
766
767 netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate);
768 }
769
qcom_ethqos_probe(struct platform_device * pdev)770 static int qcom_ethqos_probe(struct platform_device *pdev)
771 {
772 struct device_node *np = pdev->dev.of_node;
773 const struct ethqos_emac_driver_data *data;
774 struct plat_stmmacenet_data *plat_dat;
775 struct stmmac_resources stmmac_res;
776 struct device *dev = &pdev->dev;
777 struct qcom_ethqos *ethqos;
778 int ret, i;
779
780 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
781 if (ret)
782 return dev_err_probe(dev, ret,
783 "Failed to get platform resources\n");
784
785 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
786 if (IS_ERR(plat_dat)) {
787 return dev_err_probe(dev, PTR_ERR(plat_dat),
788 "dt configuration failed\n");
789 }
790
791 plat_dat->clks_config = ethqos_clks_config;
792
793 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
794 if (!ethqos)
795 return -ENOMEM;
796
797 ethqos->phy_mode = plat_dat->phy_interface;
798 switch (ethqos->phy_mode) {
799 case PHY_INTERFACE_MODE_RGMII:
800 case PHY_INTERFACE_MODE_RGMII_ID:
801 case PHY_INTERFACE_MODE_RGMII_RXID:
802 case PHY_INTERFACE_MODE_RGMII_TXID:
803 ethqos->configure_func = ethqos_configure_rgmii;
804 break;
805 case PHY_INTERFACE_MODE_2500BASEX:
806 plat_dat->speed_mode_2500 = qcom_ethqos_speed_mode_2500;
807 fallthrough;
808 case PHY_INTERFACE_MODE_SGMII:
809 ethqos->configure_func = ethqos_configure_sgmii;
810 break;
811 default:
812 dev_err(dev, "Unsupported phy mode %s\n",
813 phy_modes(ethqos->phy_mode));
814 return -EINVAL;
815 }
816
817 ethqos->pdev = pdev;
818 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
819 if (IS_ERR(ethqos->rgmii_base))
820 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
821 "Failed to map rgmii resource\n");
822
823 ethqos->mac_base = stmmac_res.addr;
824
825 data = of_device_get_match_data(dev);
826 ethqos->por = data->por;
827 ethqos->num_por = data->num_por;
828 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
829 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
830 ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback;
831
832 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
833 if (IS_ERR(ethqos->link_clk))
834 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
835 "Failed to get link_clk\n");
836
837 ret = ethqos_clks_config(ethqos, true);
838 if (ret)
839 return ret;
840
841 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
842 if (ret)
843 return ret;
844
845 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
846 if (IS_ERR(ethqos->serdes_phy))
847 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
848 "Failed to get serdes phy\n");
849
850 ethqos->speed = SPEED_1000;
851 ethqos->serdes_speed = SPEED_1000;
852 ethqos_update_link_clk(ethqos, SPEED_1000);
853 ethqos_set_func_clk_en(ethqos);
854
855 plat_dat->bsp_priv = ethqos;
856 plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
857 plat_dat->dump_debug_regs = rgmii_dump;
858 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
859 plat_dat->has_gmac4 = 1;
860 if (ethqos->has_emac_ge_3)
861 plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
862 plat_dat->pmt = 1;
863 if (of_property_read_bool(np, "snps,tso"))
864 plat_dat->flags |= STMMAC_FLAG_TSO_EN;
865 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
866 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI;
867 if (data->has_integrated_pcs)
868 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS;
869 if (data->dma_addr_width)
870 plat_dat->host_dma_width = data->dma_addr_width;
871
872 if (ethqos->serdes_phy) {
873 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
874 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
875 }
876
877 /* Enable TSO on queue0 and enable TBS on rest of the queues */
878 for (i = 1; i < plat_dat->tx_queues_to_use; i++)
879 plat_dat->tx_queues_cfg[i].tbs_en = 1;
880
881 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
882 }
883
884 static const struct of_device_id qcom_ethqos_match[] = {
885 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
886 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
887 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
888 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
889 { }
890 };
891 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
892
893 static struct platform_driver qcom_ethqos_driver = {
894 .probe = qcom_ethqos_probe,
895 .driver = {
896 .name = "qcom-ethqos",
897 .pm = &stmmac_pltfr_pm_ops,
898 .of_match_table = qcom_ethqos_match,
899 },
900 };
901 module_platform_driver(qcom_ethqos_driver);
902
903 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
904 MODULE_LICENSE("GPL v2");
905