1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025 SpacemiT Technology Co. Ltd 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ 7 #define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ 8 9 /* MPMU resets */ 10 #define RESET_MPMU_WDT 0 11 #define RESET_MPMU_RIPC 1 12 13 /* APBC resets */ 14 #define RESET_APBC_UART0 0 15 #define RESET_APBC_UART2 1 16 #define RESET_APBC_UART3 2 17 #define RESET_APBC_UART4 3 18 #define RESET_APBC_UART5 4 19 #define RESET_APBC_UART6 5 20 #define RESET_APBC_UART7 6 21 #define RESET_APBC_UART8 7 22 #define RESET_APBC_UART9 8 23 #define RESET_APBC_UART10 9 24 #define RESET_APBC_GPIO 10 25 #define RESET_APBC_PWM0 11 26 #define RESET_APBC_PWM1 12 27 #define RESET_APBC_PWM2 13 28 #define RESET_APBC_PWM3 14 29 #define RESET_APBC_PWM4 15 30 #define RESET_APBC_PWM5 16 31 #define RESET_APBC_PWM6 17 32 #define RESET_APBC_PWM7 18 33 #define RESET_APBC_PWM8 19 34 #define RESET_APBC_PWM9 20 35 #define RESET_APBC_PWM10 21 36 #define RESET_APBC_PWM11 22 37 #define RESET_APBC_PWM12 23 38 #define RESET_APBC_PWM13 24 39 #define RESET_APBC_PWM14 25 40 #define RESET_APBC_PWM15 26 41 #define RESET_APBC_PWM16 27 42 #define RESET_APBC_PWM17 28 43 #define RESET_APBC_PWM18 29 44 #define RESET_APBC_PWM19 30 45 #define RESET_APBC_SPI0 31 46 #define RESET_APBC_SPI1 32 47 #define RESET_APBC_SPI3 33 48 #define RESET_APBC_RTC 34 49 #define RESET_APBC_TWSI0 35 50 #define RESET_APBC_TWSI1 36 51 #define RESET_APBC_TWSI2 37 52 #define RESET_APBC_TWSI4 38 53 #define RESET_APBC_TWSI5 39 54 #define RESET_APBC_TWSI6 40 55 #define RESET_APBC_TWSI8 41 56 #define RESET_APBC_TIMERS0 42 57 #define RESET_APBC_TIMERS1 43 58 #define RESET_APBC_TIMERS2 44 59 #define RESET_APBC_TIMERS3 45 60 #define RESET_APBC_TIMERS4 46 61 #define RESET_APBC_TIMERS5 47 62 #define RESET_APBC_TIMERS6 48 63 #define RESET_APBC_TIMERS7 49 64 #define RESET_APBC_AIB 50 65 #define RESET_APBC_ONEWIRE 51 66 #define RESET_APBC_I2S0 52 67 #define RESET_APBC_I2S1 53 68 #define RESET_APBC_I2S2 54 69 #define RESET_APBC_I2S3 55 70 #define RESET_APBC_I2S4 56 71 #define RESET_APBC_I2S5 57 72 #define RESET_APBC_DRO 58 73 #define RESET_APBC_IR0 59 74 #define RESET_APBC_IR1 60 75 #define RESET_APBC_TSEN 61 76 #define RESET_IPC_AP2AUD 62 77 #define RESET_APBC_CAN0 63 78 #define RESET_APBC_CAN1 64 79 #define RESET_APBC_CAN2 65 80 #define RESET_APBC_CAN3 66 81 #define RESET_APBC_CAN4 67 82 83 /* APMU resets */ 84 #define RESET_APMU_CSI 0 85 #define RESET_APMU_CCIC2PHY 1 86 #define RESET_APMU_CCIC3PHY 2 87 #define RESET_APMU_ISP_CIBUS 3 88 #define RESET_APMU_DSI_ESC 4 89 #define RESET_APMU_LCD 5 90 #define RESET_APMU_V2D 6 91 #define RESET_APMU_LCD_MCLK 7 92 #define RESET_APMU_LCD_DSCCLK 8 93 #define RESET_APMU_SC2_HCLK 9 94 #define RESET_APMU_CCIC_4X 10 95 #define RESET_APMU_CCIC1_PHY 11 96 #define RESET_APMU_SDH_AXI 12 97 #define RESET_APMU_SDH0 13 98 #define RESET_APMU_SDH1 14 99 #define RESET_APMU_SDH2 15 100 #define RESET_APMU_USB2_AHB 16 101 #define RESET_APMU_USB2_VCC 17 102 #define RESET_APMU_USB2_PHY 18 103 #define RESET_APMU_USB3_A_AHB 19 104 #define RESET_APMU_USB3_A_VCC 20 105 #define RESET_APMU_QSPI 21 106 #define RESET_APMU_QSPI_BUS 22 107 #define RESET_APMU_DMA 23 108 #define RESET_APMU_AES_WTM 24 109 #define RESET_APMU_MCB_DCLK 25 110 #define RESET_APMU_MCB_ACLK 26 111 #define RESET_APMU_VPU 27 112 #define RESET_APMU_DTC 28 113 #define RESET_APMU_GPU 29 114 #define RESET_APMU_ALZO 30 115 #define RESET_APMU_MC 31 116 #define RESET_APMU_CPU0_POP 32 117 #define RESET_APMU_CPU0_SW 33 118 #define RESET_APMU_CPU1_POP 34 119 #define RESET_APMU_CPU1_SW 35 120 #define RESET_APMU_CPU2_POP 36 121 #define RESET_APMU_CPU2_SW 37 122 #define RESET_APMU_CPU3_POP 38 123 #define RESET_APMU_CPU3_SW 39 124 #define RESET_APMU_C0_MPSUB_SW 40 125 #define RESET_APMU_CPU4_POP 41 126 #define RESET_APMU_CPU4_SW 42 127 #define RESET_APMU_CPU5_POP 43 128 #define RESET_APMU_CPU5_SW 44 129 #define RESET_APMU_CPU6_POP 45 130 #define RESET_APMU_CPU6_SW 46 131 #define RESET_APMU_CPU7_POP 47 132 #define RESET_APMU_CPU7_SW 48 133 #define RESET_APMU_C1_MPSUB_SW 49 134 #define RESET_APMU_MPSUB_DBG 50 135 #define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ 136 #define RESET_APMU_USB3_B_AHB 52 137 #define RESET_APMU_DSI4LN2_ESCCLK 53 138 #define RESET_APMU_DSI4LN2_LCD_SW 54 139 #define RESET_APMU_DSI4LN2_LCD_MCLK 55 140 #define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 141 #define RESET_APMU_DSI4LN2_DPU_ACLK 57 142 #define RESET_APMU_DPU_ACLK 58 143 #define RESET_APMU_UFS_ACLK 59 144 #define RESET_APMU_EDP0 60 145 #define RESET_APMU_EDP1 61 146 #define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ 147 #define RESET_APMU_USB3_B_PHY 63 148 #define RESET_APMU_USB3_C_AHB 64 149 #define RESET_APMU_USB3_C_VCC 65 150 #define RESET_APMU_USB3_C_PHY 66 151 #define RESET_APMU_EMAC0 67 152 #define RESET_APMU_EMAC1 68 153 #define RESET_APMU_EMAC2 69 154 #define RESET_APMU_ESPI_MCLK 70 155 #define RESET_APMU_ESPI_SCLK 71 156 #define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ 157 #define RESET_APMU_USB3_D_VCC 73 158 #define RESET_APMU_USB3_D_PHY 74 159 #define RESET_APMU_UCIE_IP 75 160 #define RESET_APMU_UCIE_HOT 76 161 #define RESET_APMU_UCIE_MON 77 162 #define RESET_APMU_RCPU_AUDIO_SYS 78 163 #define RESET_APMU_RCPU_MCU_CORE 79 164 #define RESET_APMU_RCPU_AUDIO_APMU 80 165 #define RESET_APMU_PCIE_A_DBI 81 166 #define RESET_APMU_PCIE_A_SLAVE 82 167 #define RESET_APMU_PCIE_A_MASTER 83 168 #define RESET_APMU_PCIE_B_DBI 84 169 #define RESET_APMU_PCIE_B_SLAVE 85 170 #define RESET_APMU_PCIE_B_MASTER 86 171 #define RESET_APMU_PCIE_C_DBI 87 172 #define RESET_APMU_PCIE_C_SLAVE 88 173 #define RESET_APMU_PCIE_C_MASTER 89 174 #define RESET_APMU_PCIE_D_DBI 90 175 #define RESET_APMU_PCIE_D_SLAVE 91 176 #define RESET_APMU_PCIE_D_MASTER 92 177 #define RESET_APMU_PCIE_E_DBI 93 178 #define RESET_APMU_PCIE_E_SLAVE 94 179 #define RESET_APMU_PCIE_E_MASTER 95 180 181 /* DCIU resets*/ 182 #define RESET_DCIU_HDMA 0 183 #define RESET_DCIU_DMA350 1 184 #define RESET_DCIU_DMA350_0 2 185 #define RESET_DCIU_DMA350_1 3 186 #define RESET_DCIU_AXIDMA0 4 187 #define RESET_DCIU_AXIDMA1 5 188 #define RESET_DCIU_AXIDMA2 6 189 #define RESET_DCIU_AXIDMA3 7 190 #define RESET_DCIU_AXIDMA4 8 191 #define RESET_DCIU_AXIDMA5 9 192 #define RESET_DCIU_AXIDMA6 10 193 #define RESET_DCIU_AXIDMA7 11 194 195 #endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ 196