1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2018 Mellanox Technologies. All rights reserved. 4 */ 5 6 #ifndef _MLX5_ESWITCH_ 7 #define _MLX5_ESWITCH_ 8 9 #include <linux/mlx5/driver.h> 10 #include <linux/mlx5/vport.h> 11 #include <net/devlink.h> 12 13 #define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager) 14 15 enum { 16 MLX5_ESWITCH_LEGACY, 17 MLX5_ESWITCH_OFFLOADS 18 }; 19 20 enum { 21 REP_ETH, 22 REP_IB, 23 NUM_REP_TYPES, 24 }; 25 26 enum { 27 REP_UNREGISTERED, 28 REP_REGISTERED, 29 REP_LOADED, 30 }; 31 32 enum mlx5_switchdev_event { 33 MLX5_SWITCHDEV_EVENT_PAIR, 34 MLX5_SWITCHDEV_EVENT_UNPAIR, 35 }; 36 37 struct mlx5_eswitch_rep; 38 struct mlx5_eswitch_rep_ops { 39 int (*load)(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep); 40 void (*unload)(struct mlx5_eswitch_rep *rep); 41 void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep); 42 int (*event)(struct mlx5_eswitch *esw, 43 struct mlx5_eswitch_rep *rep, 44 enum mlx5_switchdev_event event, 45 void *data); 46 }; 47 48 struct mlx5_eswitch_rep_data { 49 void *priv; 50 atomic_t state; 51 }; 52 53 struct mlx5_eswitch_rep { 54 struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES]; 55 u16 vport; 56 u16 vlan; 57 /* Only IB rep is using vport_index */ 58 u16 vport_index; 59 u32 vlan_refcount; 60 struct mlx5_eswitch *esw; 61 }; 62 63 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw, 64 const struct mlx5_eswitch_rep_ops *ops, 65 u8 rep_type); 66 void 67 mlx5_eswitch_register_vport_reps_nested(struct mlx5_eswitch *esw, 68 const struct mlx5_eswitch_rep_ops *ops, 69 u8 rep_type); 70 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type); 71 void mlx5_eswitch_unregister_vport_reps_nested(struct mlx5_eswitch *esw, 72 u8 rep_type); 73 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, 74 u16 vport_num, 75 u8 rep_type); 76 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw, 77 u16 vport_num); 78 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type); 79 struct mlx5_flow_handle * 80 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw, 81 struct mlx5_eswitch *from_esw, 82 struct mlx5_eswitch_rep *rep, u32 sqn); 83 84 #ifdef CONFIG_MLX5_ESWITCH 85 enum devlink_eswitch_encap_mode 86 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev); 87 88 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw); 89 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw); 90 91 /* Reg C0 usage: 92 * Reg C0 = < ESW_PFNUM_BITS(4) | ESW_VPORT BITS(12) | ESW_REG_C0_OBJ(16) > 93 * 94 * Highest 4 bits of the reg c0 is the PF_NUM (range 0-15), 12 bits of 95 * unique non-zero vport id (range 1-4095). The rest (lowest 16 bits) is left 96 * for user data objects managed by a common mapping context. 97 * PFNUM + VPORT comprise the SOURCE_PORT matching. 98 */ 99 #define ESW_VPORT_BITS 12 100 #define ESW_PFNUM_BITS 4 101 #define ESW_SOURCE_PORT_METADATA_BITS (ESW_PFNUM_BITS + ESW_VPORT_BITS) 102 #define ESW_SOURCE_PORT_METADATA_OFFSET (32 - ESW_SOURCE_PORT_METADATA_BITS) 103 #define ESW_REG_C0_USER_DATA_METADATA_BITS (32 - ESW_SOURCE_PORT_METADATA_BITS) 104 #define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0) 105 106 static inline u32 mlx5_eswitch_get_vport_metadata_mask(void) 107 { 108 return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS); 109 } 110 111 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, 112 u16 vport_num); 113 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw, 114 u16 vport_num); 115 116 /* Reg C1 usage: 117 * Reg C1 = < Reserved(1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) > 118 * 119 * Highest bit is reserved for other offloads as marker bit, next 12 bits of reg c1 120 * is the encapsulation tunnel id, next 11 bits is encapsulation tunnel options, 121 * and the lowest 8 bits are used for zone id. 122 * 123 * Zone id is used to restore CT flow when packet misses on chain. 124 * 125 * Tunnel id and options are used together to restore the tunnel info metadata 126 * on miss and to support inner header rewrite by means of implicit chain 0 127 * flows. 128 */ 129 #define ESW_RESERVED_BITS 1 130 #define ESW_ZONE_ID_BITS 8 131 #define ESW_TUN_OPTS_BITS 11 132 #define ESW_TUN_ID_BITS 12 133 #define ESW_TUN_OPTS_OFFSET ESW_ZONE_ID_BITS 134 #define ESW_TUN_OFFSET ESW_TUN_OPTS_OFFSET 135 #define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0) 136 #define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET) 137 #define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET) 138 #define ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 0 /* 0 is not a valid tunnel id */ 139 #define ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 140 /* 0x7FF is a reserved mapping */ 141 #define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0) 142 #define ESW_TUN_SLOW_TABLE_GOTO_VPORT ((ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT << ESW_TUN_OPTS_BITS) | \ 143 ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT) 144 #define ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK ESW_TUN_OPTS_MASK 145 /* 0x7FE is a reserved mapping for bridge ingress push vlan mark */ 146 #define ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN (ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT - 1) 147 #define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN ((ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN << \ 148 ESW_TUN_OPTS_BITS) | \ 149 ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN) 150 #define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN_MARK \ 151 GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \ 152 ESW_TUN_OPTS_OFFSET + 1) 153 154 /* reuse tun_opts for the mapped ipsec obj id when tun_id is 0 (invalid) */ 155 #define ESW_IPSEC_RX_MAPPED_ID_MASK GENMASK(ESW_TUN_OPTS_BITS - 1, 0) 156 #define ESW_IPSEC_RX_MAPPED_ID_MATCH_MASK \ 157 GENMASK(31 - ESW_RESERVED_BITS, ESW_ZONE_ID_BITS) 158 159 u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev); 160 u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev); 161 struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw); 162 163 #else /* CONFIG_MLX5_ESWITCH */ 164 165 static inline u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev) 166 { 167 return MLX5_ESWITCH_LEGACY; 168 } 169 170 static inline enum devlink_eswitch_encap_mode 171 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev) 172 { 173 return DEVLINK_ESWITCH_ENCAP_MODE_NONE; 174 } 175 176 static inline bool 177 mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw) 178 { 179 return false; 180 }; 181 182 static inline bool 183 mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw) 184 { 185 return false; 186 }; 187 188 static inline u32 189 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, u16 vport_num) 190 { 191 return 0; 192 }; 193 194 static inline u32 195 mlx5_eswitch_get_vport_metadata_mask(void) 196 { 197 return 0; 198 } 199 200 static inline u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev) 201 { 202 return 0; 203 } 204 205 static inline struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw) 206 { 207 return NULL; 208 } 209 210 #endif /* CONFIG_MLX5_ESWITCH */ 211 212 static inline bool is_mdev_legacy_mode(struct mlx5_core_dev *dev) 213 { 214 return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_LEGACY; 215 } 216 217 static inline bool is_mdev_switchdev_mode(struct mlx5_core_dev *dev) 218 { 219 return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_OFFLOADS; 220 } 221 222 /* The returned number is valid only when the dev is eswitch manager. */ 223 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) 224 { 225 return mlx5_core_is_ecpf_esw_manager(dev) ? 226 MLX5_VPORT_ECPF : MLX5_VPORT_HOST_PF; 227 } 228 229 #endif 230