1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright 2021 NXP */
3
4 #include <dt-bindings/firmware/imx/rsrc.h>
5 #include <linux/arm-smccc.h>
6 #include <linux/clk.h>
7 #include <linux/err.h>
8 #include <linux/firmware.h>
9 #include <linux/firmware/imx/sci.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_client.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_reserved_mem.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_domain.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/remoteproc.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24
25 #include "imx_rproc.h"
26 #include "remoteproc_elf_helpers.h"
27 #include "remoteproc_internal.h"
28
29 #define DSP_RPROC_CLK_MAX 5
30
31 /*
32 * Module parameters
33 */
34 static unsigned int no_mailboxes;
35 module_param_named(no_mailboxes, no_mailboxes, int, 0644);
36 MODULE_PARM_DESC(no_mailboxes,
37 "There is no mailbox between cores, so ignore remote proc reply after start, default is 0 (off).");
38
39 /* Flag indicating that the remote is up and running */
40 #define REMOTE_IS_READY BIT(0)
41 /* Flag indicating that the host should wait for a firmware-ready response */
42 #define WAIT_FW_READY BIT(1)
43 #define REMOTE_READY_WAIT_MAX_RETRIES 500
44
45 /*
46 * This flag is set in the DSP resource table's features field to indicate
47 * that the firmware requires the host NOT to wait for a FW_READY response.
48 */
49 #define FEATURE_DONT_WAIT_FW_READY BIT(0)
50
51 /* att flags */
52 /* DSP own area */
53 #define ATT_OWN BIT(31)
54 /* DSP instruction area */
55 #define ATT_IRAM BIT(30)
56
57 /* Definitions for i.MX8MP */
58 /* DAP registers */
59 #define IMX8M_DAP_DEBUG 0x28800000
60 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
61 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
62 #define IMX8M_PWRCTL_CORERESET BIT(16)
63
64 /* DSP audio mix registers */
65 #define IMX8M_AudioDSP_REG0 0x100
66 #define IMX8M_AudioDSP_REG1 0x104
67 #define IMX8M_AudioDSP_REG2 0x108
68 #define IMX8M_AudioDSP_REG3 0x10c
69
70 #define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5)
71 #define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1)
72
73 /* Definitions for i.MX8ULP */
74 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8
75 #define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25)
76 #define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19)
77 #define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18)
78 #define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17)
79 #define IMX8ULP_SYSCTRL0_DSP_RST BIT(16)
80 #define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14)
81 #define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13)
82
83 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e
84
85 #define FW_RSC_NXP_S_MAGIC ((uint32_t)'n' << 24 | \
86 (uint32_t)'x' << 16 | \
87 (uint32_t)'p' << 8 | \
88 (uint32_t)'s')
89 /*
90 * enum - Predefined Mailbox Messages
91 *
92 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor
93 *
94 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a
95 * suspend request
96 *
97 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor
98 *
99 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a
100 * resume request
101 */
102 enum imx_dsp_rp_mbox_messages {
103 RP_MBOX_SUSPEND_SYSTEM = 0xFF11,
104 RP_MBOX_SUSPEND_ACK = 0xFF12,
105 RP_MBOX_RESUME_SYSTEM = 0xFF13,
106 RP_MBOX_RESUME_ACK = 0xFF14,
107 };
108
109 /**
110 * struct imx_dsp_rproc - DSP remote processor state
111 * @regmap: regmap handler
112 * @run_stall: reset control handle used for Run/Stall operation
113 * @rproc: rproc handler
114 * @dsp_dcfg: device configuration pointer
115 * @clks: clocks needed by this device
116 * @cl: mailbox client to request the mailbox channel
117 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell
118 * @tx_ch: mailbox tx channel handle
119 * @rx_ch: mailbox rx channel handle
120 * @rxdb_ch: mailbox rx doorbell channel handle
121 * @pd_list: power domain list
122 * @ipc_handle: System Control Unit ipc handle
123 * @rproc_work: work for processing virtio interrupts
124 * @pm_comp: completion primitive to sync for suspend response
125 * @flags: control flags
126 */
127 struct imx_dsp_rproc {
128 struct regmap *regmap;
129 struct reset_control *run_stall;
130 struct rproc *rproc;
131 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
132 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX];
133 struct mbox_client cl;
134 struct mbox_client cl_rxdb;
135 struct mbox_chan *tx_ch;
136 struct mbox_chan *rx_ch;
137 struct mbox_chan *rxdb_ch;
138 struct dev_pm_domain_list *pd_list;
139 struct imx_sc_ipc *ipc_handle;
140 struct work_struct rproc_work;
141 struct completion pm_comp;
142 u32 flags;
143 };
144
145 /**
146 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration
147 * @dcfg: imx_rproc_dcfg handler
148 * @reset: reset callback function
149 */
150 struct imx_dsp_rproc_dcfg {
151 const struct imx_rproc_dcfg *dcfg;
152 int (*reset)(struct imx_dsp_rproc *priv);
153 };
154
155 /**
156 * struct fw_rsc_imx_dsp - i.MX DSP specific info
157 *
158 * @len: length of the resource entry
159 * @magic_num: 32-bit magic number
160 * @version: version of data structure
161 * @features: feature flags supported by the i.MX DSP firmware
162 *
163 * This represents a DSP-specific resource in the firmware's
164 * resource table, providing information on supported features.
165 */
166 struct fw_rsc_imx_dsp {
167 uint32_t len;
168 uint32_t magic_num;
169 uint32_t version;
170 uint32_t features;
171 } __packed;
172
173 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = {
174 /* dev addr , sys addr , size , flags */
175 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN },
176 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN },
177 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM},
178 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN },
179 /* DDR (Data) */
180 { 0x80000000, 0x80000000, 0x60000000, 0},
181 };
182
183 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = {
184 /* dev addr , sys addr , size , flags */
185 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN },
186 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN },
187 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM},
188 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN },
189 /* DDR (Data) */
190 { 0x80000000, 0x80000000, 0x60000000, 0},
191 };
192
193 static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = {
194 /* dev addr , sys addr , size , flags */
195 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN },
196 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN },
197 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM},
198 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN },
199 /* DDR (Data) */
200 { 0x40000000, 0x40000000, 0x80000000, 0},
201 };
202
203 static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = {
204 /* dev addr , sys addr , size , flags */
205 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM},
206 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN },
207 /* DDR (Data) */
208 { 0x0c000000, 0x80000000, 0x10000000, 0},
209 { 0x30000000, 0x90000000, 0x10000000, 0},
210 };
211
212 /* Initialize the mailboxes between cores, if exists */
213 static int (*imx_dsp_rproc_mbox_init)(struct imx_dsp_rproc *priv);
214
215 /* Reset function for DSP on i.MX8MP */
imx8mp_dsp_reset(struct imx_dsp_rproc * priv)216 static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv)
217 {
218 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
219 int pwrctl;
220
221 /* Put DSP into reset and stall */
222 pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
223 pwrctl |= IMX8M_PWRCTL_CORERESET;
224 writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
225
226 /* Keep reset asserted for 10 cycles */
227 usleep_range(1, 2);
228
229 reset_control_assert(priv->run_stall);
230
231 /* Take the DSP out of reset and keep stalled for FW loading */
232 pwrctl = readl(dap + IMX8M_DAP_PWRCTL);
233 pwrctl &= ~IMX8M_PWRCTL_CORERESET;
234 writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
235
236 iounmap(dap);
237 return 0;
238 }
239
240 /* Reset function for DSP on i.MX8ULP */
imx8ulp_dsp_reset(struct imx_dsp_rproc * priv)241 static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv)
242 {
243 struct arm_smccc_res res;
244
245 /* Put DSP into reset and stall */
246 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
247 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST);
248 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
249 IMX8ULP_SYSCTRL0_DSP_STALL,
250 IMX8ULP_SYSCTRL0_DSP_STALL);
251
252 /* Configure resources of DSP through TFA */
253 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res);
254
255 /* Take the DSP out of reset and keep stalled for FW loading */
256 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
257 IMX8ULP_SYSCTRL0_DSP_RST, 0);
258 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
259 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0);
260
261 return 0;
262 }
263
imx_dsp_rproc_ready(struct rproc * rproc)264 static int imx_dsp_rproc_ready(struct rproc *rproc)
265 {
266 struct imx_dsp_rproc *priv = rproc->priv;
267 int i;
268
269 if (!priv->rxdb_ch)
270 return 0;
271
272 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) {
273 if (priv->flags & REMOTE_IS_READY)
274 return 0;
275 usleep_range(100, 200);
276 }
277
278 return -ETIMEDOUT;
279 }
280
281 /**
282 * imx_dsp_rproc_handle_rsc() - Handle DSP-specific resource table entries
283 * @rproc: remote processor instance
284 * @rsc_type: resource type identifier
285 * @rsc: pointer to the resource entry
286 * @offset: offset of the resource entry
287 * @avail: available space in the resource table
288 *
289 * Parse the DSP-specific resource entry and update flags accordingly.
290 * If the WAIT_FW_READY feature is set, the host must wait for the firmware
291 * to signal readiness before proceeding with execution.
292 *
293 * Return: RSC_HANDLED if processed successfully, RSC_IGNORED otherwise.
294 */
imx_dsp_rproc_handle_rsc(struct rproc * rproc,u32 rsc_type,void * rsc,int offset,int avail)295 static int imx_dsp_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type,
296 void *rsc, int offset, int avail)
297 {
298 struct imx_dsp_rproc *priv = rproc->priv;
299 struct fw_rsc_imx_dsp *imx_dsp_rsc = rsc;
300 struct device *dev = rproc->dev.parent;
301
302 if (!imx_dsp_rsc) {
303 dev_dbg(dev, "Invalid fw_rsc_imx_dsp.\n");
304 return RSC_IGNORED;
305 }
306
307 /* Make sure resource isn't truncated */
308 if (sizeof(struct fw_rsc_imx_dsp) > avail ||
309 sizeof(struct fw_rsc_imx_dsp) != imx_dsp_rsc->len) {
310 dev_dbg(dev, "Resource fw_rsc_imx_dsp is truncated.\n");
311 return RSC_IGNORED;
312 }
313
314 /*
315 * If FW_RSC_NXP_S_MAGIC number is not found then
316 * wait for fw_ready reply (default work flow)
317 */
318 if (imx_dsp_rsc->magic_num != FW_RSC_NXP_S_MAGIC) {
319 dev_dbg(dev, "Invalid resource table magic number.\n");
320 return RSC_IGNORED;
321 }
322
323 /*
324 * For now, in struct fw_rsc_imx_dsp, version 0,
325 * only FEATURE_DONT_WAIT_FW_READY is valid.
326 *
327 * When adding new features, please upgrade version.
328 */
329 if (imx_dsp_rsc->version > 0) {
330 dev_warn(dev, "Unexpected fw_rsc_imx_dsp version %d.\n",
331 imx_dsp_rsc->version);
332 return RSC_IGNORED;
333 }
334
335 if (imx_dsp_rsc->features & FEATURE_DONT_WAIT_FW_READY)
336 priv->flags &= ~WAIT_FW_READY;
337
338 return RSC_HANDLED;
339 }
340
imx_dsp_rproc_mmio_start(struct rproc * rproc)341 static int imx_dsp_rproc_mmio_start(struct rproc *rproc)
342 {
343 struct imx_dsp_rproc *priv = rproc->priv;
344 const struct imx_rproc_dcfg *dcfg = priv->dsp_dcfg->dcfg;
345
346 return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_start);
347 }
348
imx_dsp_rproc_reset_ctrl_start(struct rproc * rproc)349 static int imx_dsp_rproc_reset_ctrl_start(struct rproc *rproc)
350 {
351 struct imx_dsp_rproc *priv = rproc->priv;
352
353 return reset_control_deassert(priv->run_stall);
354 }
355
imx_dsp_rproc_scu_api_start(struct rproc * rproc)356 static int imx_dsp_rproc_scu_api_start(struct rproc *rproc)
357 {
358 struct imx_dsp_rproc *priv = rproc->priv;
359
360 return imx_sc_pm_cpu_start(priv->ipc_handle, IMX_SC_R_DSP, true, rproc->bootaddr);
361 }
362
363 /*
364 * Start function for rproc_ops
365 *
366 * There is a handshake for start procedure: when DSP starts, it
367 * will send a doorbell message to this driver, then the
368 * REMOTE_IS_READY flags is set, then driver will kick
369 * a message to DSP.
370 */
imx_dsp_rproc_start(struct rproc * rproc)371 static int imx_dsp_rproc_start(struct rproc *rproc)
372 {
373 struct imx_dsp_rproc *priv = rproc->priv;
374 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
375 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
376 struct device *dev = rproc->dev.parent;
377 int ret;
378
379 if (!dcfg->ops || !dcfg->ops->start)
380 return -EOPNOTSUPP;
381
382 ret = dcfg->ops->start(rproc);
383 if (ret) {
384 dev_err(dev, "Failed to enable remote core!\n");
385 return ret;
386 }
387
388 if (priv->flags & WAIT_FW_READY)
389 return imx_dsp_rproc_ready(rproc);
390
391 return 0;
392 }
393
imx_dsp_rproc_mmio_stop(struct rproc * rproc)394 static int imx_dsp_rproc_mmio_stop(struct rproc *rproc)
395 {
396 struct imx_dsp_rproc *priv = rproc->priv;
397 const struct imx_rproc_dcfg *dcfg = priv->dsp_dcfg->dcfg;
398
399 return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_stop);
400 }
401
imx_dsp_rproc_reset_ctrl_stop(struct rproc * rproc)402 static int imx_dsp_rproc_reset_ctrl_stop(struct rproc *rproc)
403 {
404 struct imx_dsp_rproc *priv = rproc->priv;
405
406 return reset_control_assert(priv->run_stall);
407 }
408
imx_dsp_rproc_scu_api_stop(struct rproc * rproc)409 static int imx_dsp_rproc_scu_api_stop(struct rproc *rproc)
410 {
411 struct imx_dsp_rproc *priv = rproc->priv;
412
413 return imx_sc_pm_cpu_start(priv->ipc_handle, IMX_SC_R_DSP, false, rproc->bootaddr);
414 }
415
416 /*
417 * Stop function for rproc_ops
418 * It clears the REMOTE_IS_READY flags
419 */
imx_dsp_rproc_stop(struct rproc * rproc)420 static int imx_dsp_rproc_stop(struct rproc *rproc)
421 {
422 struct imx_dsp_rproc *priv = rproc->priv;
423 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
424 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
425 struct device *dev = rproc->dev.parent;
426 int ret = 0;
427
428 if (rproc->state == RPROC_CRASHED) {
429 priv->flags &= ~REMOTE_IS_READY;
430 return 0;
431 }
432
433 if (!dcfg->ops || !dcfg->ops->stop)
434 return -EOPNOTSUPP;
435
436 ret = dcfg->ops->stop(rproc);
437 if (ret) {
438 dev_err(dev, "Failed to stop remote core\n");
439 return ret;
440 }
441
442 priv->flags &= ~REMOTE_IS_READY;
443
444 return 0;
445 }
446
447 /**
448 * imx_dsp_rproc_sys_to_da() - internal memory translation helper
449 * @priv: private data pointer
450 * @sys: system address (DDR address)
451 * @len: length of the memory buffer
452 * @da: device address to translate
453 *
454 * Convert system address (DDR address) to device address (DSP)
455 * for there may be memory remap for device.
456 */
imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc * priv,u64 sys,size_t len,u64 * da)457 static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys,
458 size_t len, u64 *da)
459 {
460 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
461 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
462 int i;
463
464 /* Parse address translation table */
465 for (i = 0; i < dcfg->att_size; i++) {
466 const struct imx_rproc_att *att = &dcfg->att[i];
467
468 if (sys >= att->sa && sys + len <= att->sa + att->size) {
469 unsigned int offset = sys - att->sa;
470
471 *da = att->da + offset;
472 return 0;
473 }
474 }
475
476 return -ENOENT;
477 }
478
479 /* Main virtqueue message work function
480 *
481 * This function is executed upon scheduling of the i.MX DSP remoteproc
482 * driver's workqueue. The workqueue is scheduled by the mailbox rx
483 * handler.
484 *
485 * This work function processes both the Tx and Rx virtqueue indices on
486 * every invocation. The rproc_vq_interrupt function can detect if there
487 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED),
488 * but there is no need to check for these return values. The index 0
489 * triggering will process all pending Rx buffers, and the index 1 triggering
490 * will process all newly available Tx buffers and will wakeup any potentially
491 * blocked senders.
492 *
493 * NOTE:
494 * The current logic is based on an inherent design assumption of supporting
495 * only 2 vrings, but this can be changed if needed.
496 */
imx_dsp_rproc_vq_work(struct work_struct * work)497 static void imx_dsp_rproc_vq_work(struct work_struct *work)
498 {
499 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc,
500 rproc_work);
501 struct rproc *rproc = priv->rproc;
502
503 mutex_lock(&rproc->lock);
504
505 if (rproc->state != RPROC_RUNNING)
506 goto unlock_mutex;
507
508 rproc_vq_interrupt(priv->rproc, 0);
509 rproc_vq_interrupt(priv->rproc, 1);
510
511 unlock_mutex:
512 mutex_unlock(&rproc->lock);
513 }
514
515 /**
516 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler
517 * @cl: mailbox client pointer used for requesting the mailbox channel
518 * @data: mailbox payload
519 *
520 * This handler is invoked by mailbox driver whenever a mailbox
521 * message is received. Usually, the SUSPEND and RESUME related messages
522 * are handled in this function, other messages are handled by remoteproc core
523 */
imx_dsp_rproc_rx_tx_callback(struct mbox_client * cl,void * data)524 static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data)
525 {
526 struct rproc *rproc = dev_get_drvdata(cl->dev);
527 struct imx_dsp_rproc *priv = rproc->priv;
528 struct device *dev = rproc->dev.parent;
529 u32 message = (u32)(*(u32 *)data);
530
531 dev_dbg(dev, "mbox msg: 0x%x\n", message);
532
533 switch (message) {
534 case RP_MBOX_SUSPEND_ACK:
535 complete(&priv->pm_comp);
536 break;
537 case RP_MBOX_RESUME_ACK:
538 complete(&priv->pm_comp);
539 break;
540 default:
541 schedule_work(&priv->rproc_work);
542 break;
543 }
544 }
545
546 /**
547 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler
548 * @cl: mailbox client pointer used for requesting the mailbox channel
549 * @data: mailbox payload
550 *
551 * For doorbell, there is no message specified, just set REMOTE_IS_READY
552 * flag.
553 */
imx_dsp_rproc_rxdb_callback(struct mbox_client * cl,void * data)554 static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data)
555 {
556 struct rproc *rproc = dev_get_drvdata(cl->dev);
557 struct imx_dsp_rproc *priv = rproc->priv;
558
559 /* Remote is ready after firmware is loaded and running */
560 priv->flags |= REMOTE_IS_READY;
561 }
562
563 /**
564 * imx_dsp_rproc_mbox_alloc() - request mailbox channels
565 * @priv: private data pointer
566 *
567 * Request three mailbox channels (tx, rx, rxdb).
568 */
imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc * priv)569 static int imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc *priv)
570 {
571 struct device *dev = priv->rproc->dev.parent;
572 struct mbox_client *cl;
573 int ret;
574
575 if (!of_property_present(dev->of_node, "mbox-names"))
576 return 0;
577
578 cl = &priv->cl;
579 cl->dev = dev;
580 cl->tx_block = true;
581 cl->tx_tout = 100;
582 cl->knows_txdone = false;
583 cl->rx_callback = imx_dsp_rproc_rx_tx_callback;
584
585 /* Channel for sending message */
586 priv->tx_ch = mbox_request_channel_byname(cl, "tx");
587 if (IS_ERR(priv->tx_ch)) {
588 ret = PTR_ERR(priv->tx_ch);
589 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n",
590 ret);
591 return ret;
592 }
593
594 /* Channel for receiving message */
595 priv->rx_ch = mbox_request_channel_byname(cl, "rx");
596 if (IS_ERR(priv->rx_ch)) {
597 ret = PTR_ERR(priv->rx_ch);
598 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n",
599 ret);
600 goto free_channel_tx;
601 }
602
603 cl = &priv->cl_rxdb;
604 cl->dev = dev;
605 cl->rx_callback = imx_dsp_rproc_rxdb_callback;
606
607 /*
608 * RX door bell is used to receive the ready signal from remote
609 * after firmware loaded.
610 */
611 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb");
612 if (IS_ERR(priv->rxdb_ch)) {
613 ret = PTR_ERR(priv->rxdb_ch);
614 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n",
615 ret);
616 goto free_channel_rx;
617 }
618
619 return 0;
620
621 free_channel_rx:
622 mbox_free_channel(priv->rx_ch);
623 free_channel_tx:
624 mbox_free_channel(priv->tx_ch);
625 return ret;
626 }
627
628 /*
629 * imx_dsp_rproc_mbox_no_alloc()
630 *
631 * Empty function for no mailbox between cores
632 *
633 * Always return 0
634 */
imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc * priv)635 static int imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc *priv)
636 {
637 return 0;
638 }
639
imx_dsp_rproc_free_mbox(struct imx_dsp_rproc * priv)640 static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv)
641 {
642 mbox_free_channel(priv->tx_ch);
643 mbox_free_channel(priv->rx_ch);
644 mbox_free_channel(priv->rxdb_ch);
645 }
646
647 /**
648 * imx_dsp_rproc_add_carveout() - request mailbox channels
649 * @priv: private data pointer
650 *
651 * This function registers specified memory entry in @rproc carveouts list
652 * The carveouts can help to mapping the memory address for DSP.
653 */
imx_dsp_rproc_add_carveout(struct imx_dsp_rproc * priv)654 static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv)
655 {
656 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
657 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
658 struct rproc *rproc = priv->rproc;
659 struct device *dev = rproc->dev.parent;
660 struct device_node *np = dev->of_node;
661 struct rproc_mem_entry *mem;
662 void __iomem *cpu_addr;
663 int a, i = 0;
664 u64 da;
665
666 /* Remap required addresses */
667 for (a = 0; a < dcfg->att_size; a++) {
668 const struct imx_rproc_att *att = &dcfg->att[a];
669
670 if (!(att->flags & ATT_OWN))
671 continue;
672
673 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da))
674 return -EINVAL;
675
676 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size);
677 if (!cpu_addr) {
678 dev_err(dev, "failed to map memory %p\n", &att->sa);
679 return -ENOMEM;
680 }
681
682 /* Register memory region */
683 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa,
684 att->size, da, NULL, NULL, "dsp_mem");
685
686 if (mem)
687 rproc_coredump_add_segment(rproc, da, att->size);
688 else
689 return -ENOMEM;
690
691 rproc_add_carveout(rproc, mem);
692 }
693
694 while (1) {
695 int err;
696 struct resource res;
697
698 err = of_reserved_mem_region_to_resource(np, i++, &res);
699 if (err)
700 return 0;
701
702 /*
703 * Ignore the first memory region which will be used vdev buffer.
704 * No need to do extra handlings, rproc_add_virtio_dev will handle it.
705 */
706 if (strstarts(res.name, "vdev0buffer"))
707 continue;
708
709 if (imx_dsp_rproc_sys_to_da(priv, res.start, resource_size(&res), &da))
710 return -EINVAL;
711
712 cpu_addr = devm_ioremap_resource_wc(dev, &res);
713 if (IS_ERR(cpu_addr)) {
714 dev_err(dev, "failed to map memory %pR\n", &res);
715 return PTR_ERR(cpu_addr);
716 }
717
718 /* Register memory region */
719 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)res.start,
720 resource_size(&res), da, NULL, NULL,
721 "%.*s", strchrnul(res.name, '@') - res.name, res.name);
722 if (!mem)
723 return -ENOMEM;
724
725 rproc_coredump_add_segment(rproc, da, resource_size(&res));
726 rproc_add_carveout(rproc, mem);
727 }
728 }
729
730 /* Prepare function for rproc_ops */
imx_dsp_rproc_prepare(struct rproc * rproc)731 static int imx_dsp_rproc_prepare(struct rproc *rproc)
732 {
733 struct imx_dsp_rproc *priv = rproc->priv;
734 struct device *dev = rproc->dev.parent;
735 int ret;
736
737 ret = imx_dsp_rproc_add_carveout(priv);
738 if (ret) {
739 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n");
740 return ret;
741 }
742
743 pm_runtime_get_sync(dev);
744
745 return 0;
746 }
747
748 /* Unprepare function for rproc_ops */
imx_dsp_rproc_unprepare(struct rproc * rproc)749 static int imx_dsp_rproc_unprepare(struct rproc *rproc)
750 {
751 pm_runtime_put_sync(rproc->dev.parent);
752
753 return 0;
754 }
755
756 /* Kick function for rproc_ops */
imx_dsp_rproc_kick(struct rproc * rproc,int vqid)757 static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid)
758 {
759 struct imx_dsp_rproc *priv = rproc->priv;
760 struct device *dev = rproc->dev.parent;
761 int err;
762 __u32 mmsg;
763
764 if (!priv->tx_ch) {
765 dev_err(dev, "No initialized mbox tx channel\n");
766 return;
767 }
768
769 /*
770 * Send the index of the triggered virtqueue as the mu payload.
771 * Let remote processor know which virtqueue is used.
772 */
773 mmsg = vqid;
774
775 err = mbox_send_message(priv->tx_ch, (void *)&mmsg);
776 if (err < 0)
777 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err);
778 }
779
780 /*
781 * Custom memory copy implementation for i.MX DSP Cores
782 *
783 * The IRAM is part of the HiFi DSP.
784 * According to hw specs only 32-bits writes are allowed.
785 */
imx_dsp_rproc_memcpy(void * dst,const void * src,size_t size)786 static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size)
787 {
788 void __iomem *dest = (void __iomem *)dst;
789 const u8 *src_byte = src;
790 const u32 *source = src;
791 u32 affected_mask;
792 int i, q, r;
793 u32 tmp;
794
795 /* destination must be 32bit aligned */
796 if (!IS_ALIGNED((uintptr_t)dest, 4))
797 return -EINVAL;
798
799 q = size / 4;
800 r = size % 4;
801
802 /* copy data in units of 32 bits at a time */
803 for (i = 0; i < q; i++)
804 writel(source[i], dest + i * 4);
805
806 if (r) {
807 affected_mask = GENMASK(8 * r, 0);
808
809 /*
810 * first read the 32bit data of dest, then change affected
811 * bytes, and write back to dest.
812 * For unaffected bytes, it should not be changed
813 */
814 tmp = readl(dest + q * 4);
815 tmp &= ~affected_mask;
816
817 /* avoid reading after end of source */
818 for (i = 0; i < r; i++)
819 tmp |= (src_byte[q * 4 + i] << (8 * i));
820
821 writel(tmp, dest + q * 4);
822 }
823
824 return 0;
825 }
826
827 /*
828 * Custom memset implementation for i.MX DSP Cores
829 *
830 * The IRAM is part of the HiFi DSP.
831 * According to hw specs only 32-bits writes are allowed.
832 */
imx_dsp_rproc_memset(void * addr,u8 value,size_t size)833 static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size)
834 {
835 void __iomem *tmp_dst = (void __iomem *)addr;
836 u32 tmp_val = value;
837 u32 affected_mask;
838 int q, r;
839 u32 tmp;
840
841 /* destination must be 32bit aligned */
842 if (!IS_ALIGNED((uintptr_t)addr, 4))
843 return -EINVAL;
844
845 tmp_val |= tmp_val << 8;
846 tmp_val |= tmp_val << 16;
847
848 q = size / 4;
849 r = size % 4;
850
851 while (q--)
852 writel(tmp_val, tmp_dst++);
853
854 if (r) {
855 affected_mask = GENMASK(8 * r, 0);
856
857 /*
858 * first read the 32bit data of addr, then change affected
859 * bytes, and write back to addr.
860 * For unaffected bytes, it should not be changed
861 */
862 tmp = readl(tmp_dst);
863 tmp &= ~affected_mask;
864
865 tmp |= (tmp_val & affected_mask);
866 writel(tmp, tmp_dst);
867 }
868
869 return 0;
870 }
871
872 /*
873 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory
874 * @rproc: remote processor which will be booted using these fw segments
875 * @fw: the ELF firmware image
876 *
877 * This function loads the firmware segments to memory, where the remote
878 * processor expects them.
879 *
880 * Return: 0 on success and an appropriate error code otherwise
881 */
imx_dsp_rproc_elf_load_segments(struct rproc * rproc,const struct firmware * fw)882 static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
883 {
884 struct device *dev = &rproc->dev;
885 const void *ehdr, *phdr;
886 int i, ret = 0;
887 u16 phnum;
888 const u8 *elf_data = fw->data;
889 u8 class = fw_elf_get_class(fw);
890 u32 elf_phdr_get_size = elf_size_of_phdr(class);
891
892 ehdr = elf_data;
893 phnum = elf_hdr_get_e_phnum(class, ehdr);
894 phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr);
895
896 /* go through the available ELF segments */
897 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) {
898 u64 da = elf_phdr_get_p_paddr(class, phdr);
899 u64 memsz = elf_phdr_get_p_memsz(class, phdr);
900 u64 filesz = elf_phdr_get_p_filesz(class, phdr);
901 u64 offset = elf_phdr_get_p_offset(class, phdr);
902 u32 type = elf_phdr_get_p_type(class, phdr);
903 void *ptr;
904
905 if (type != PT_LOAD || !memsz)
906 continue;
907
908 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n",
909 type, da, memsz, filesz);
910
911 if (filesz > memsz) {
912 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n",
913 filesz, memsz);
914 ret = -EINVAL;
915 break;
916 }
917
918 if (offset + filesz > fw->size) {
919 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n",
920 offset + filesz, fw->size);
921 ret = -EINVAL;
922 break;
923 }
924
925 if (!rproc_u64_fit_in_size_t(memsz)) {
926 dev_err(dev, "size (%llx) does not fit in size_t type\n",
927 memsz);
928 ret = -EOVERFLOW;
929 break;
930 }
931
932 /* grab the kernel address for this device address */
933 ptr = rproc_da_to_va(rproc, da, memsz, NULL);
934 if (!ptr) {
935 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da,
936 memsz);
937 ret = -EINVAL;
938 break;
939 }
940
941 /* put the segment where the remote processor expects it */
942 if (filesz) {
943 ret = imx_dsp_rproc_memcpy(ptr, elf_data + offset, filesz);
944 if (ret) {
945 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n",
946 da, memsz);
947 break;
948 }
949 }
950
951 /* zero out remaining memory for this segment */
952 if (memsz > filesz) {
953 ret = imx_dsp_rproc_memset(ptr + filesz, 0, memsz - filesz);
954 if (ret) {
955 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n",
956 da, memsz);
957 break;
958 }
959 }
960 }
961
962 return ret;
963 }
964
imx_dsp_rproc_parse_fw(struct rproc * rproc,const struct firmware * fw)965 static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
966 {
967 if (rproc_elf_load_rsc_table(rproc, fw))
968 dev_warn(&rproc->dev, "no resource table found for this firmware\n");
969
970 return 0;
971 }
972
imx_dsp_rproc_load(struct rproc * rproc,const struct firmware * fw)973 static int imx_dsp_rproc_load(struct rproc *rproc, const struct firmware *fw)
974 {
975 struct imx_dsp_rproc *priv = rproc->priv;
976 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
977 struct rproc_mem_entry *carveout;
978 int ret;
979
980 /* Reset DSP if needed */
981 if (dsp_dcfg->reset)
982 dsp_dcfg->reset(priv);
983 /*
984 * Clear buffers after pm rumtime for internal ocram is not
985 * accessible if power and clock are not enabled.
986 */
987 list_for_each_entry(carveout, &rproc->carveouts, node) {
988 if (carveout->va)
989 memset(carveout->va, 0, carveout->len);
990 }
991
992 ret = imx_dsp_rproc_elf_load_segments(rproc, fw);
993 if (ret)
994 return ret;
995
996 return 0;
997 }
998
999 static const struct rproc_ops imx_dsp_rproc_ops = {
1000 .prepare = imx_dsp_rproc_prepare,
1001 .unprepare = imx_dsp_rproc_unprepare,
1002 .start = imx_dsp_rproc_start,
1003 .stop = imx_dsp_rproc_stop,
1004 .kick = imx_dsp_rproc_kick,
1005 .load = imx_dsp_rproc_load,
1006 .parse_fw = imx_dsp_rproc_parse_fw,
1007 .handle_rsc = imx_dsp_rproc_handle_rsc,
1008 .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
1009 .sanity_check = rproc_elf_sanity_check,
1010 .get_boot_addr = rproc_elf_get_boot_addr,
1011 };
1012
1013 /**
1014 * imx_dsp_attach_pm_domains() - attach the power domains
1015 * @priv: private data pointer
1016 *
1017 * On i.MX8QM and i.MX8QXP there is multiple power domains
1018 * required, so need to link them.
1019 */
imx_dsp_attach_pm_domains(struct imx_dsp_rproc * priv)1020 static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv)
1021 {
1022 struct device *dev = priv->rproc->dev.parent;
1023
1024 /* A single PM domain is already attached. */
1025 if (dev->pm_domain)
1026 return 0;
1027
1028 return devm_pm_domain_attach_list(dev, NULL, &priv->pd_list);
1029 }
1030
imx_dsp_rproc_mmio_detect_mode(struct rproc * rproc)1031 static int imx_dsp_rproc_mmio_detect_mode(struct rproc *rproc)
1032 {
1033 struct imx_dsp_rproc *priv = rproc->priv;
1034 struct device *dev = rproc->dev.parent;
1035 struct regmap *regmap;
1036
1037 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl");
1038 if (IS_ERR(regmap)) {
1039 dev_err(dev, "failed to find syscon\n");
1040 return PTR_ERR(regmap);
1041 }
1042
1043 priv->regmap = regmap;
1044
1045 return 0;
1046 }
1047
imx_dsp_rproc_reset_ctrl_detect_mode(struct rproc * rproc)1048 static int imx_dsp_rproc_reset_ctrl_detect_mode(struct rproc *rproc)
1049 {
1050 struct imx_dsp_rproc *priv = rproc->priv;
1051 struct device *dev = rproc->dev.parent;
1052
1053 priv->run_stall = devm_reset_control_get_exclusive(dev, "runstall");
1054 if (IS_ERR(priv->run_stall)) {
1055 dev_err(dev, "Failed to get DSP runstall reset control\n");
1056 return PTR_ERR(priv->run_stall);
1057 }
1058
1059 return 0;
1060 }
1061
imx_dsp_rproc_scu_api_detect_mode(struct rproc * rproc)1062 static int imx_dsp_rproc_scu_api_detect_mode(struct rproc *rproc)
1063 {
1064 struct imx_dsp_rproc *priv = rproc->priv;
1065
1066 return imx_scu_get_handle(&priv->ipc_handle);
1067 }
1068
1069 /**
1070 * imx_dsp_rproc_detect_mode() - detect DSP control mode
1071 * @priv: private data pointer
1072 *
1073 * Different platform has different control method for DSP, which depends
1074 * on how the DSP is integrated in platform.
1075 *
1076 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
1077 * Control Unit.
1078 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system
1079 * integration module.
1080 */
imx_dsp_rproc_detect_mode(struct imx_dsp_rproc * priv)1081 static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv)
1082 {
1083 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
1084 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
1085
1086 if (dcfg->ops && dcfg->ops->detect_mode)
1087 return dcfg->ops->detect_mode(priv->rproc);
1088
1089 return -EOPNOTSUPP;
1090 }
1091
1092 static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = {
1093 /* DSP clocks */
1094 "core", "ocram", "debug", "ipg", "mu",
1095 };
1096
imx_dsp_rproc_clk_get(struct imx_dsp_rproc * priv)1097 static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv)
1098 {
1099 struct device *dev = priv->rproc->dev.parent;
1100 struct clk_bulk_data *clks = priv->clks;
1101 int i;
1102
1103 for (i = 0; i < DSP_RPROC_CLK_MAX; i++)
1104 clks[i].id = imx_dsp_clks_names[i];
1105
1106 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks);
1107 }
1108
imx_dsp_rproc_probe(struct platform_device * pdev)1109 static int imx_dsp_rproc_probe(struct platform_device *pdev)
1110 {
1111 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
1112 struct device *dev = &pdev->dev;
1113 struct imx_dsp_rproc *priv;
1114 struct rproc *rproc;
1115 const char *fw_name;
1116 int ret;
1117
1118 dsp_dcfg = of_device_get_match_data(dev);
1119 if (!dsp_dcfg)
1120 return -ENODEV;
1121
1122 ret = rproc_of_parse_firmware(dev, 0, &fw_name);
1123 if (ret)
1124 return dev_err_probe(dev, ret, "failed to parse firmware-name property\n");
1125
1126 rproc = devm_rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops,
1127 fw_name, sizeof(*priv));
1128 if (!rproc)
1129 return -ENOMEM;
1130
1131 priv = rproc->priv;
1132 priv->rproc = rproc;
1133 priv->dsp_dcfg = dsp_dcfg;
1134 /* By default, host waits for fw_ready reply */
1135 priv->flags |= WAIT_FW_READY;
1136
1137 if (no_mailboxes)
1138 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_no_alloc;
1139 else
1140 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_alloc;
1141
1142 dev_set_drvdata(dev, rproc);
1143
1144 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work);
1145
1146 ret = imx_dsp_rproc_detect_mode(priv);
1147 if (ret)
1148 return dev_err_probe(dev, ret, "failed on imx_dsp_rproc_detect_mode\n");
1149
1150 /* There are multiple power domains required by DSP on some platform */
1151 ret = imx_dsp_attach_pm_domains(priv);
1152 if (ret < 0)
1153 return dev_err_probe(dev, ret, "failed on imx_dsp_attach_pm_domains\n");
1154
1155 /* Get clocks */
1156 ret = imx_dsp_rproc_clk_get(priv);
1157 if (ret)
1158 return dev_err_probe(dev, ret, "failed on imx_dsp_rproc_clk_get\n");
1159
1160 init_completion(&priv->pm_comp);
1161 rproc->auto_boot = false;
1162 ret = devm_rproc_add(dev, rproc);
1163 if (ret)
1164 return dev_err_probe(dev, ret, "rproc_add failed\n");
1165
1166 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_XTENSA);
1167
1168 return devm_pm_runtime_enable(dev);
1169 }
1170
1171 /* pm runtime functions */
imx_dsp_runtime_resume(struct device * dev)1172 static int imx_dsp_runtime_resume(struct device *dev)
1173 {
1174 struct rproc *rproc = dev_get_drvdata(dev);
1175 struct imx_dsp_rproc *priv = rproc->priv;
1176 int ret;
1177
1178 /*
1179 * There is power domain attached with mailbox, if setup mailbox
1180 * in probe(), then the power of mailbox is always enabled,
1181 * the power can't be saved.
1182 * So move setup of mailbox to runtime resume.
1183 */
1184 ret = imx_dsp_rproc_mbox_init(priv);
1185 if (ret) {
1186 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n");
1187 return ret;
1188 }
1189
1190 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks);
1191 if (ret) {
1192 dev_err(dev, "failed on clk_bulk_prepare_enable\n");
1193 return ret;
1194 }
1195
1196 return 0;
1197 }
1198
imx_dsp_runtime_suspend(struct device * dev)1199 static int imx_dsp_runtime_suspend(struct device *dev)
1200 {
1201 struct rproc *rproc = dev_get_drvdata(dev);
1202 struct imx_dsp_rproc *priv = rproc->priv;
1203
1204 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks);
1205
1206 imx_dsp_rproc_free_mbox(priv);
1207
1208 return 0;
1209 }
1210
imx_dsp_load_firmware(const struct firmware * fw,void * context)1211 static void imx_dsp_load_firmware(const struct firmware *fw, void *context)
1212 {
1213 struct rproc *rproc = context;
1214 int ret;
1215
1216 /*
1217 * Same flow as start procedure.
1218 * Load the ELF segments to memory firstly.
1219 */
1220 ret = rproc_load_segments(rproc, fw);
1221 if (ret)
1222 goto out;
1223
1224 /* Start the remote processor */
1225 ret = rproc->ops->start(rproc);
1226 if (ret)
1227 goto out;
1228
1229 rproc->ops->kick(rproc, 0);
1230
1231 out:
1232 release_firmware(fw);
1233 }
1234
imx_dsp_suspend(struct device * dev)1235 static int imx_dsp_suspend(struct device *dev)
1236 {
1237 struct rproc *rproc = dev_get_drvdata(dev);
1238 struct imx_dsp_rproc *priv = rproc->priv;
1239 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM;
1240 int ret;
1241
1242 if (rproc->state != RPROC_RUNNING)
1243 goto out;
1244
1245 reinit_completion(&priv->pm_comp);
1246
1247 /* Tell DSP that suspend is happening */
1248 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg);
1249 if (ret < 0) {
1250 dev_err(dev, "PM mbox_send_message failed: %d\n", ret);
1251 return ret;
1252 }
1253
1254 /*
1255 * DSP need to save the context at suspend.
1256 * Here waiting the response for DSP, then power can be disabled.
1257 */
1258 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100)))
1259 return -EBUSY;
1260
1261 out:
1262 /*
1263 * The power of DSP is disabled in suspend, so force pm runtime
1264 * to be suspend, then we can reenable the power and clocks at
1265 * resume stage.
1266 */
1267 return pm_runtime_force_suspend(dev);
1268 }
1269
imx_dsp_resume(struct device * dev)1270 static int imx_dsp_resume(struct device *dev)
1271 {
1272 struct rproc *rproc = dev_get_drvdata(dev);
1273 int ret = 0;
1274
1275 ret = pm_runtime_force_resume(dev);
1276 if (ret)
1277 return ret;
1278
1279 if (rproc->state != RPROC_RUNNING)
1280 return 0;
1281
1282 /*
1283 * The power of DSP is disabled at suspend, the memory of dsp
1284 * is reset, the image segments are lost. So need to reload
1285 * firmware and restart the DSP if it is in running state.
1286 */
1287 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
1288 rproc->firmware, dev, GFP_KERNEL,
1289 rproc, imx_dsp_load_firmware);
1290 if (ret < 0) {
1291 dev_err(dev, "load firmware failed: %d\n", ret);
1292 goto err;
1293 }
1294
1295 return 0;
1296
1297 err:
1298 pm_runtime_force_suspend(dev);
1299
1300 return ret;
1301 }
1302
1303 static const struct dev_pm_ops imx_dsp_rproc_pm_ops = {
1304 SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
1305 RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL)
1306 };
1307
1308 static const struct imx_rproc_plat_ops imx_dsp_rproc_ops_mmio = {
1309 .start = imx_dsp_rproc_mmio_start,
1310 .stop = imx_dsp_rproc_mmio_stop,
1311 .detect_mode = imx_dsp_rproc_mmio_detect_mode,
1312 };
1313
1314 static const struct imx_rproc_plat_ops imx_dsp_rproc_ops_reset_ctrl = {
1315 .start = imx_dsp_rproc_reset_ctrl_start,
1316 .stop = imx_dsp_rproc_reset_ctrl_stop,
1317 .detect_mode = imx_dsp_rproc_reset_ctrl_detect_mode,
1318 };
1319
1320 static const struct imx_rproc_plat_ops imx_dsp_rproc_ops_scu_api = {
1321 .start = imx_dsp_rproc_scu_api_start,
1322 .stop = imx_dsp_rproc_scu_api_stop,
1323 .detect_mode = imx_dsp_rproc_scu_api_detect_mode,
1324 };
1325
1326 /* Specific configuration for i.MX8MP */
1327 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = {
1328 .att = imx_dsp_rproc_att_imx8mp,
1329 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp),
1330 .ops = &imx_dsp_rproc_ops_reset_ctrl,
1331 };
1332
1333 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = {
1334 .dcfg = &dsp_rproc_cfg_imx8mp,
1335 .reset = imx8mp_dsp_reset,
1336 };
1337
1338 /* Specific configuration for i.MX8ULP */
1339 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = {
1340 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
1341 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL,
1342 .src_start = 0,
1343 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL,
1344 .att = imx_dsp_rproc_att_imx8ulp,
1345 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp),
1346 .ops = &imx_dsp_rproc_ops_mmio,
1347 };
1348
1349 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = {
1350 .dcfg = &dsp_rproc_cfg_imx8ulp,
1351 .reset = imx8ulp_dsp_reset,
1352 };
1353
1354 /* Specific configuration for i.MX8QXP */
1355 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = {
1356 .att = imx_dsp_rproc_att_imx8qxp,
1357 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp),
1358 .ops = &imx_dsp_rproc_ops_scu_api,
1359 };
1360
1361 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = {
1362 .dcfg = &dsp_rproc_cfg_imx8qxp,
1363 };
1364
1365 /* Specific configuration for i.MX8QM */
1366 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = {
1367 .att = imx_dsp_rproc_att_imx8qm,
1368 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm),
1369 .ops = &imx_dsp_rproc_ops_scu_api,
1370 };
1371
1372 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = {
1373 .dcfg = &dsp_rproc_cfg_imx8qm,
1374 };
1375
1376 static const struct of_device_id imx_dsp_rproc_of_match[] = {
1377 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp },
1378 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm },
1379 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp },
1380 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp },
1381 {},
1382 };
1383 MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match);
1384
1385 static struct platform_driver imx_dsp_rproc_driver = {
1386 .probe = imx_dsp_rproc_probe,
1387 .driver = {
1388 .name = "imx-dsp-rproc",
1389 .of_match_table = imx_dsp_rproc_of_match,
1390 .pm = pm_ptr(&imx_dsp_rproc_pm_ops),
1391 },
1392 };
1393 module_platform_driver(imx_dsp_rproc_driver);
1394
1395 MODULE_LICENSE("GPL v2");
1396 MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver");
1397 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
1398