1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright 2024 Fiona Klute 3 * 4 * Based on code originally in rtw8723d.[ch], 5 * Copyright(c) 2018-2019 Realtek Corporation 6 */ 7 8 #ifndef __RTW8723X_H__ 9 #define __RTW8723X_H__ 10 11 #include "main.h" 12 #include "debug.h" 13 #include "phy.h" 14 #include "reg.h" 15 16 enum rtw8723x_path { 17 PATH_S1, 18 PATH_S0, 19 PATH_NR, 20 }; 21 22 enum rtw8723x_iqk_round { 23 IQK_ROUND_0, 24 IQK_ROUND_1, 25 IQK_ROUND_2, 26 IQK_ROUND_HYBRID, 27 IQK_ROUND_SIZE, 28 IQK_ROUND_INVALID = 0xff, 29 }; 30 31 enum rtw8723x_iqk_result { 32 IQK_S1_TX_X, 33 IQK_S1_TX_Y, 34 IQK_S1_RX_X, 35 IQK_S1_RX_Y, 36 IQK_S0_TX_X, 37 IQK_S0_TX_Y, 38 IQK_S0_RX_X, 39 IQK_S0_RX_Y, 40 IQK_NR, 41 IQK_SX_NR = IQK_NR / PATH_NR, 42 }; 43 44 struct rtw8723xe_efuse { 45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */ 46 u8 vendor_id[2]; 47 u8 device_id[2]; 48 u8 sub_vendor_id[2]; 49 u8 sub_device_id[2]; 50 } __packed; 51 52 struct rtw8723xu_efuse { 53 u8 res4[48]; /* 0xd0 */ 54 u8 vendor_id[2]; /* 0x100 */ 55 u8 product_id[2]; /* 0x102 */ 56 u8 usb_option; /* 0x104 */ 57 u8 res5[2]; /* 0x105 */ 58 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 59 } __packed; 60 61 struct rtw8723xs_efuse { 62 u8 res4[0x4a]; /* 0xd0 */ 63 u8 mac_addr[ETH_ALEN]; /* 0x11a */ 64 } __packed; 65 66 struct rtw8723x_efuse { 67 __le16 rtl_id; 68 u8 rsvd[2]; 69 u8 afe; 70 u8 rsvd1[11]; 71 72 /* power index for four RF paths */ 73 struct rtw_txpwr_idx txpwr_idx_table[4]; 74 75 u8 channel_plan; /* 0xb8 */ 76 u8 xtal_k; 77 u8 thermal_meter; 78 u8 iqk_lck; 79 u8 pa_type; /* 0xbc */ 80 u8 lna_type_2g[2]; /* 0xbd */ 81 u8 lna_type_5g[2]; 82 u8 rf_board_option; 83 u8 rf_feature_option; 84 u8 rf_bt_setting; 85 u8 eeprom_version; 86 u8 eeprom_customer_id; 87 u8 tx_bb_swing_setting_2g; 88 u8 res_c7; 89 u8 tx_pwr_calibrate_rate; 90 u8 rf_antenna_option; /* 0xc9 */ 91 u8 rfe_option; 92 u8 country_code[2]; 93 u8 res[3]; 94 union { 95 struct rtw8723xe_efuse e; 96 struct rtw8723xu_efuse u; 97 struct rtw8723xs_efuse s; 98 }; 99 } __packed; 100 101 #define RTW8723X_IQK_ADDA_REG_NUM 16 102 #define RTW8723X_IQK_MAC8_REG_NUM 3 103 #define RTW8723X_IQK_MAC32_REG_NUM 1 104 #define RTW8723X_IQK_BB_REG_NUM 9 105 106 struct rtw8723x_iqk_backup_regs { 107 u32 adda[RTW8723X_IQK_ADDA_REG_NUM]; 108 u8 mac8[RTW8723X_IQK_MAC8_REG_NUM]; 109 u32 mac32[RTW8723X_IQK_MAC32_REG_NUM]; 110 u32 bb[RTW8723X_IQK_BB_REG_NUM]; 111 112 u32 lte_path; 113 u32 lte_gnt; 114 115 u32 bb_sel_btg; 116 u8 btg_sel; 117 118 u8 igia; 119 u8 igib; 120 }; 121 122 struct rtw8723x_common { 123 /* registers that must be backed up before IQK and restored after */ 124 u32 iqk_adda_regs[RTW8723X_IQK_ADDA_REG_NUM]; 125 u32 iqk_mac8_regs[RTW8723X_IQK_MAC8_REG_NUM]; 126 u32 iqk_mac32_regs[RTW8723X_IQK_MAC32_REG_NUM]; 127 u32 iqk_bb_regs[RTW8723X_IQK_BB_REG_NUM]; 128 129 /* chip register definitions */ 130 struct rtw_ltecoex_addr ltecoex_addr; 131 struct rtw_rf_sipi_addr rf_sipi_addr[2]; 132 struct rtw_hw_reg dig[2]; 133 struct rtw_hw_reg dig_cck[1]; 134 struct rtw_prioq_addrs prioq_addrs; 135 136 /* common functions */ 137 void (*lck)(struct rtw_dev *rtwdev); 138 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *log_map); 139 int (*mac_init)(struct rtw_dev *rtwdev); 140 int (*mac_postinit)(struct rtw_dev *rtwdev); 141 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 142 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 143 void (*efuse_grant)(struct rtw_dev *rtwdev, bool on); 144 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 145 void (*iqk_backup_regs)(struct rtw_dev *rtwdev, 146 struct rtw8723x_iqk_backup_regs *backup); 147 void (*iqk_restore_regs)(struct rtw_dev *rtwdev, 148 const struct rtw8723x_iqk_backup_regs *backup); 149 bool (*iqk_similarity_cmp)(struct rtw_dev *rtwdev, s32 result[][IQK_NR], 150 u8 c1, u8 c2); 151 u8 (*pwrtrack_get_limit_ofdm)(struct rtw_dev *rtwdev); 152 void (*pwrtrack_set_xtal)(struct rtw_dev *rtwdev, u8 therm_path, 153 u8 delta); 154 void (*coex_cfg_init)(struct rtw_dev *rtwdev); 155 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 156 struct rtw_tx_pkt_info *pkt_info, 157 u8 *txdesc); 158 void (*debug_txpwr_limit)(struct rtw_dev *rtwdev, 159 struct rtw_txpwr_idx *table, 160 int tx_path_count); 161 }; 162 163 extern const struct rtw8723x_common rtw8723x_common; 164 165 struct phy_rx_agc_info { 166 #ifdef __LITTLE_ENDIAN 167 u8 gain: 7; 168 u8 trsw: 1; 169 #else 170 u8 trsw: 1; 171 u8 gain: 7; 172 #endif 173 } __packed; 174 175 /* Receive PHY status layout, shared by the 8723x chips. */ 176 struct phy_status_8723x { 177 struct phy_rx_agc_info path_agc[2]; 178 u8 ch_corr[2]; 179 u8 cck_sig_qual_ofdm_pwdb_all; 180 /* for CCK: bits 0:4: VGA index, bits 5:7: LNA index (low) */ 181 u8 cck_agc_rpt_ofdm_cfosho_a; 182 /* for CCK: bit 7 is high bit of LNA index if long report type */ 183 u8 cck_rpt_b_ofdm_cfosho_b; 184 u8 reserved_1; 185 u8 noise_power_db_msb; 186 s8 path_cfotail[2]; 187 u8 pcts_mask[2]; 188 s8 stream_rxevm[2]; 189 u8 path_rxsnr[2]; 190 u8 noise_power_db_lsb; 191 u8 reserved_2[3]; 192 u8 stream_csi[2]; 193 u8 stream_target_csi[2]; 194 s8 sig_evm; 195 u8 reserved_3; 196 197 #ifdef __LITTLE_ENDIAN 198 u8 antsel_rx_keep_2: 1; 199 u8 sgi_en: 1; 200 u8 rxsc: 2; 201 u8 idle_long: 1; 202 u8 r_ant_train_en: 1; 203 u8 ant_sel_b: 1; 204 u8 ant_sel: 1; 205 #else /* __BIG_ENDIAN */ 206 u8 ant_sel: 1; 207 u8 ant_sel_b: 1; 208 u8 r_ant_train_en: 1; 209 u8 idle_long: 1; 210 u8 rxsc: 2; 211 u8 sgi_en: 1; 212 u8 antsel_rx_keep_2: 1; 213 #endif 214 } __packed; 215 216 #define PATH_IQK_RETRY 2 217 #define MAX_TOLERANCE 5 218 #define IQK_TX_X_ERR 0x142 219 #define IQK_TX_Y_ERR 0x42 220 #define IQK_RX_X_ERR 0x132 221 #define IQK_RX_Y_ERR 0x36 222 #define IQK_RX_X_UPPER 0x11a 223 #define IQK_RX_X_LOWER 0xe6 224 #define IQK_RX_Y_LMT 0x1a 225 #define IQK_TX_OK BIT(0) 226 #define IQK_RX_OK BIT(1) 227 228 #define WLAN_TXQ_RPT_EN 0x1F 229 230 #define AGG_BURST_NUM 3 231 #define AGG_BURST_SIZE 0 /* 1K */ 232 #define BIT_MASK_AGG_BURST_NUM (GENMASK(3, 2)) 233 #define BIT_MASK_AGG_BURST_SIZE (GENMASK(5, 4)) 234 235 #define SPUR_THRES 0x16 236 #define DIS_3WIRE 0xccf000c0 237 #define EN_3WIRE 0xccc000c0 238 #define START_PSD 0x400000 239 #define FREQ_CH5 0xfccd 240 #define FREQ_CH6 0xfc4d 241 #define FREQ_CH7 0xffcd 242 #define FREQ_CH8 0xff4d 243 #define FREQ_CH13 0xfccd 244 #define FREQ_CH14 0xff9a 245 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) 246 #define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) 247 #define RFCFGCH_BW_20M (BIT(11) | BIT(10)) 248 #define RFCFGCH_BW_40M BIT(10) 249 #define BIT_MASK_RFMOD BIT(0) 250 #define BIT_LCK BIT(15) 251 252 #define REG_GPIO_INTM 0x0048 253 #define REG_BTG_SEL 0x0067 254 #define BIT_MASK_BTG_WL BIT(7) 255 #define REG_LTECOEX_PATH_CONTROL 0x0070 256 #define REG_LTECOEX_CTRL 0x07c0 257 #define REG_LTECOEX_WRITE_DATA 0x07c4 258 #define REG_LTECOEX_READ_DATA 0x07c8 259 #define REG_PSDFN 0x0808 260 #define REG_BB_PWR_SAV5_11N 0x0818 261 #define REG_BB_PWR_SAV1_11N 0x0874 262 #define REG_ANA_PARAM1 0x0880 263 #define REG_ANALOG_P4 0x088c 264 #define REG_PSDRPT 0x08b4 265 #define REG_FPGA1_RFMOD 0x0900 266 #define REG_BB_SEL_BTG 0x0948 267 #define REG_BBRX_DFIR 0x0954 268 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24) 269 #define BIT_RXBB_DFIR_EN BIT(19) 270 #define REG_CCK0_SYS 0x0a00 271 #define BIT_CCK_SIDE_BAND BIT(4) 272 #define REG_CCK_ANT_SEL_11N 0x0a04 273 #define REG_PWRTH 0x0a08 274 #define REG_CCK_FA_RST_11N 0x0a2c 275 #define BIT_MASK_CCK_CNT_KEEP BIT(12) 276 #define BIT_MASK_CCK_CNT_EN BIT(13) 277 #define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) 278 #define BIT_MASK_CCK_FA_KEEP BIT(14) 279 #define BIT_MASK_CCK_FA_EN BIT(15) 280 #define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) 281 #define REG_CCK_FA_LSB_11N 0x0a5c 282 #define REG_CCK_FA_MSB_11N 0x0a58 283 #define REG_CCK_CCA_CNT_11N 0x0a60 284 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) 285 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) 286 #define REG_PWRTH2 0x0aa8 287 #define REG_CSRATIO 0x0aaa 288 #define REG_OFDM_FA_HOLDC_11N 0x0c00 289 #define BIT_MASK_OFDM_FA_KEEP BIT(31) 290 #define REG_BB_RX_PATH_11N 0x0c04 291 #define REG_TRMUX_11N 0x0c08 292 #define REG_OFDM_FA_RSTC_11N 0x0c0c 293 #define BIT_MASK_OFDM_FA_RST BIT(31) 294 #define REG_A_RXIQI 0x0c14 295 #define BIT_MASK_RXIQ_S1_X 0x000003FF 296 #define BIT_MASK_RXIQ_S1_Y1 0x0000FC00 297 #define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F) 298 #define REG_OFDM0_RXDSP 0x0c40 299 #define BIT_MASK_RXDSP GENMASK(28, 24) 300 #define BIT_EN_RXDSP BIT(9) 301 #define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c 302 #define BIT_MASK_OFDM0_EXT_A BIT(31) 303 #define BIT_MASK_OFDM0_EXT_C BIT(29) 304 #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) 305 #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) 306 #define BIT_MASK_OFDM0_EXTS_B (BIT(27) | BIT(25) | BIT(24)) 307 #define BIT_SET_OFDM0_EXTS_B(a, c, d) (((a) << 27) | ((c) << 25) | ((d) << 24)) 308 #define REG_OFDM0_XAAGC1 0x0c50 309 #define REG_OFDM0_XBAGC1 0x0c58 310 #define REG_AGCRSSI 0x0c78 311 #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 312 #define REG_OFDM_0_XB_TX_IQ_IMBALANCE 0x0c88 313 #define BIT_MASK_TXIQ_ELM_A 0x03ff 314 #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ 315 ((a) & 0x03ff)) 316 #define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16) 317 #define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F) 318 #define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22) 319 #define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94 320 #define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6) 321 #define REG_TXIQK_MATRIXB_LSB2_11N 0x0c9c 322 #define REG_RXIQK_MATRIX_LSB_11N 0x0ca0 323 #define BIT_MASK_RXIQ_S1_Y2 0xF0000000 324 #define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF) 325 #define REG_TXIQ_AB_S0 0x0cd0 326 #define BIT_MASK_TXIQ_A_S0 0x000007FE 327 #define BIT_MASK_TXIQ_A_EXT_S0 BIT(0) 328 #define BIT_MASK_TXIQ_B_S0 0x0007E000 329 #define REG_TXIQ_CD_S0 0x0cd4 330 #define BIT_MASK_TXIQ_C_S0 0x000007FE 331 #define BIT_MASK_TXIQ_C_EXT_S0 BIT(0) 332 #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13) 333 #define BIT_MASK_TXIQ_D_EXT_S0 BIT(12) 334 #define REG_RXIQ_AB_S0 0x0cd8 335 #define BIT_MASK_RXIQ_X_S0 0x000003FF 336 #define BIT_MASK_RXIQ_Y_S0 0x003FF000 337 #define REG_OFDM0_TX_PSD_NOISE 0x0ce4 /* TX pseudo noise weighting */ 338 #define REG_OFDM_FA_TYPE1_11N 0x0cf0 339 #define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) 340 #define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) 341 #define REG_OFDM_FA_RSTD_11N 0x0d00 342 #define BIT_MASK_OFDM_FA_RST1 BIT(27) 343 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31) 344 #define REG_CTX 0x0d03 345 #define BIT_MASK_CTX_TYPE GENMASK(6, 4) 346 #define REG_OFDM1_CFOTRK 0x0d2c 347 #define BIT_EN_CFOTRK BIT(28) 348 #define REG_OFDM1_CSI1 0x0d40 349 #define REG_OFDM1_CSI2 0x0d44 350 #define REG_OFDM1_CSI3 0x0d48 351 #define REG_OFDM1_CSI4 0x0d4c 352 #define REG_OFDM_FA_TYPE2_11N 0x0da0 353 #define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) 354 #define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) 355 #define REG_OFDM_FA_TYPE3_11N 0x0da4 356 #define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) 357 #define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) 358 #define REG_OFDM_FA_TYPE4_11N 0x0da8 359 #define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) 360 #define REG_FPGA0_IQK_11N 0x0e28 361 #define BIT_MASK_IQK_MOD 0xffffff00 362 #define EN_IQK 0x808000 363 #define RST_IQK 0x000000 364 #define REG_TXIQK_TONE_A_11N 0x0e30 365 #define REG_RXIQK_TONE_A_11N 0x0e34 366 #define REG_TXIQK_PI_A_11N 0x0e38 367 #define REG_RXIQK_PI_A_11N 0x0e3c 368 #define REG_TXIQK_11N 0x0e40 369 #define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y)) 370 #define REG_RXIQK_11N 0x0e44 371 #define REG_IQK_AGC_PTS_11N 0x0e48 372 #define REG_IQK_AGC_RSP_11N 0x0e4c 373 #define REG_TX_IQK_TONE_B 0x0e50 374 #define REG_RX_IQK_TONE_B 0x0e54 375 #define REG_TXIQK_PI_B 0x0e58 376 #define REG_RXIQK_PI_B 0x0e5c 377 #define REG_IQK_RDY 0x0e90 /* is != 0 when IQK is done */ 378 #define REG_IQK_RES_TX 0x0e94 379 #define BIT_MASK_RES_TX GENMASK(25, 16) 380 #define REG_IQK_RES_TY 0x0e9c 381 #define BIT_MASK_RES_TY GENMASK(25, 16) 382 #define REG_IQK_RES_RX 0x0ea4 383 #define BIT_MASK_RES_RX GENMASK(25, 16) 384 #define REG_IQK_RES_RY 0x0eac 385 #define BIT_IQK_TX_FAIL BIT(28) 386 #define BIT_IQK_RX_FAIL BIT(27) 387 #define BIT_IQK_DONE BIT(26) 388 #define BIT_MASK_RES_RY GENMASK(25, 16) 389 #define REG_PAGE_F_RST_11N 0x0f14 390 #define BIT_MASK_F_RST_ALL BIT(16) 391 #define REG_IGI_C_11N 0x0f84 392 #define REG_IGI_D_11N 0x0f88 393 #define REG_HT_CRC32_CNT_11N 0x0f90 394 #define BIT_MASK_HT_CRC_OK GENMASK(15, 0) 395 #define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) 396 #define REG_OFDM_CRC32_CNT_11N 0x0f94 397 #define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) 398 #define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) 399 #define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 400 401 #define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing) 402 #define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing) 403 #define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing) 404 #define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing) 405 406 static inline s32 iqkxy_to_s32(s32 val) 407 { 408 /* val is Q10.8 */ 409 return sign_extend32(val, 9); 410 } 411 412 static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) 413 { 414 /* x, y and return value are Q10.8 */ 415 s32 t; 416 417 t = x * y; 418 if (ext) 419 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ 420 421 return (t >> 8); /* Q.16 --> Q.8 */ 422 } 423 424 static inline 425 void rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev, 426 struct rtw_txpwr_idx *table, 427 int tx_path_count) 428 { 429 rtw8723x_common.debug_txpwr_limit(rtwdev, table, tx_path_count); 430 } 431 432 static inline void rtw8723x_lck(struct rtw_dev *rtwdev) 433 { 434 rtw8723x_common.lck(rtwdev); 435 } 436 437 static inline int rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 438 { 439 return rtw8723x_common.read_efuse(rtwdev, log_map); 440 } 441 442 static inline int rtw8723x_mac_init(struct rtw_dev *rtwdev) 443 { 444 return rtw8723x_common.mac_init(rtwdev); 445 } 446 447 static inline int rtw8723x_mac_postinit(struct rtw_dev *rtwdev) 448 { 449 return rtw8723x_common.mac_postinit(rtwdev); 450 } 451 452 static inline void rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 453 { 454 rtw8723x_common.cfg_ldo25(rtwdev, enable); 455 } 456 457 static inline void rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev) 458 { 459 rtw8723x_common.set_tx_power_index(rtwdev); 460 } 461 462 static inline void rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on) 463 { 464 rtw8723x_common.efuse_grant(rtwdev, on); 465 } 466 467 static inline void rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev) 468 { 469 rtw8723x_common.false_alarm_statistics(rtwdev); 470 } 471 472 static inline 473 void rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev, 474 struct rtw8723x_iqk_backup_regs *backup) 475 { 476 rtw8723x_common.iqk_backup_regs(rtwdev, backup); 477 } 478 479 static inline 480 void rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev, 481 const struct rtw8723x_iqk_backup_regs *backup) 482 { 483 rtw8723x_common.iqk_restore_regs(rtwdev, backup); 484 } 485 486 static inline 487 bool rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], 488 u8 c1, u8 c2) 489 { 490 return rtw8723x_common.iqk_similarity_cmp(rtwdev, result, c1, c2); 491 } 492 493 static inline u8 rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 494 { 495 return rtw8723x_common.pwrtrack_get_limit_ofdm(rtwdev); 496 } 497 498 static inline 499 void rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 500 u8 delta) 501 { 502 rtw8723x_common.pwrtrack_set_xtal(rtwdev, therm_path, delta); 503 } 504 505 static inline void rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev) 506 { 507 rtw8723x_common.coex_cfg_init(rtwdev); 508 } 509 510 static inline 511 void rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev, 512 struct rtw_tx_pkt_info *pkt_info, 513 u8 *txdesc) 514 { 515 rtw8723x_common.fill_txdesc_checksum(rtwdev, pkt_info, txdesc); 516 } 517 518 /* IQK helper functions, defined as inline so they can be shared 519 * without needing an EXPORT_SYMBOL each. 520 */ 521 static inline void 522 rtw8723x_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, 523 struct rtw8723x_iqk_backup_regs *backup) 524 { 525 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); 526 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", 527 backup->btg_sel); 528 } 529 530 static inline void rtw8723x_iqk_config_path_ctrl(struct rtw_dev *rtwdev) 531 { 532 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); 533 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", 534 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 535 } 536 537 static inline void 538 rtw8723x_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, 539 const struct rtw8723x_iqk_backup_regs *backup) 540 { 541 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); 542 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", 543 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 544 } 545 546 static inline void 547 rtw8723x_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, 548 struct rtw8723x_iqk_backup_regs *backup) 549 { 550 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); 551 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); 552 mdelay(1); 553 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); 554 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", 555 backup->lte_gnt); 556 } 557 558 static inline void 559 rtw8723x_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev, 560 u32 write_data) 561 { 562 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, write_data); 563 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); 564 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, 565 BIT_LTE_MUX_CTRL_PATH, 0x1); 566 } 567 568 static inline void 569 rtw8723x_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, 570 const struct rtw8723x_iqk_backup_regs *bak) 571 { 572 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); 573 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); 574 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); 575 } 576 577 /* set all ADDA registers to the given value */ 578 static inline void rtw8723x_iqk_path_adda_on(struct rtw_dev *rtwdev, u32 value) 579 { 580 for (int i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) 581 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], value); 582 } 583 584 #endif /* __RTW8723X_H__ */ 585