xref: /linux/drivers/media/i2c/ov7670.c (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * A V4L2 driver for OmniVision OV7670 cameras.
4  *
5  * Copyright 2006 One Laptop Per Child Association, Inc.  Written
6  * by Jonathan Corbet with substantial inspiration from Mark
7  * McClelland's ovcamchip code.
8  *
9  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10  */
11 #include <linux/clk.h>
12 #include <linux/init.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <linux/gpio/consumer.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-event.h>
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-fwnode.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/v4l2-image-sizes.h>
26 #include <media/i2c/ov7670.h>
27 
28 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
29 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
30 MODULE_LICENSE("GPL");
31 
32 static bool debug;
33 module_param(debug, bool, 0644);
34 MODULE_PARM_DESC(debug, "Debug level (0-1)");
35 
36 /*
37  * The 7670 sits on i2c with ID 0x42
38  */
39 #define OV7670_I2C_ADDR 0x42
40 
41 #define PLL_FACTOR	4
42 
43 /* Registers */
44 #define REG_GAIN	0x00	/* Gain lower 8 bits (rest in vref) */
45 #define REG_BLUE	0x01	/* blue gain */
46 #define REG_RED		0x02	/* red gain */
47 #define REG_VREF	0x03	/* Pieces of GAIN, VSTART, VSTOP */
48 #define REG_COM1	0x04	/* Control 1 */
49 #define  COM1_CCIR656	  0x40  /* CCIR656 enable */
50 #define REG_BAVE	0x05	/* U/B Average level */
51 #define REG_GbAVE	0x06	/* Y/Gb Average level */
52 #define REG_AECHH	0x07	/* AEC MS 5 bits */
53 #define REG_RAVE	0x08	/* V/R Average level */
54 #define REG_COM2	0x09	/* Control 2 */
55 #define  COM2_SSLEEP	  0x10	/* Soft sleep mode */
56 #define REG_PID		0x0a	/* Product ID MSB */
57 #define REG_VER		0x0b	/* Product ID LSB */
58 #define REG_COM3	0x0c	/* Control 3 */
59 #define  COM3_SWAP	  0x40	  /* Byte swap */
60 #define  COM3_SCALEEN	  0x08	  /* Enable scaling */
61 #define  COM3_DCWEN	  0x04	  /* Enable downsamp/crop/window */
62 #define REG_COM4	0x0d	/* Control 4 */
63 #define REG_COM5	0x0e	/* All "reserved" */
64 #define REG_COM6	0x0f	/* Control 6 */
65 #define REG_AECH	0x10	/* More bits of AEC value */
66 #define REG_CLKRC	0x11	/* Clocl control */
67 #define   CLK_EXT	  0x40	  /* Use external clock directly */
68 #define   CLK_SCALE	  0x3f	  /* Mask for internal clock scale */
69 #define REG_COM7	0x12	/* Control 7 */
70 #define   COM7_RESET	  0x80	  /* Register reset */
71 #define   COM7_FMT_MASK	  0x38
72 #define   COM7_FMT_VGA	  0x00
73 #define	  COM7_FMT_CIF	  0x20	  /* CIF format */
74 #define   COM7_FMT_QVGA	  0x10	  /* QVGA format */
75 #define   COM7_FMT_QCIF	  0x08	  /* QCIF format */
76 #define	  COM7_RGB	  0x04	  /* bits 0 and 2 - RGB format */
77 #define	  COM7_YUV	  0x00	  /* YUV */
78 #define	  COM7_BAYER	  0x01	  /* Bayer format */
79 #define	  COM7_PBAYER	  0x05	  /* "Processed bayer" */
80 #define REG_COM8	0x13	/* Control 8 */
81 #define   COM8_FASTAEC	  0x80	  /* Enable fast AGC/AEC */
82 #define   COM8_AECSTEP	  0x40	  /* Unlimited AEC step size */
83 #define   COM8_BFILT	  0x20	  /* Band filter enable */
84 #define   COM8_AGC	  0x04	  /* Auto gain enable */
85 #define   COM8_AWB	  0x02	  /* White balance enable */
86 #define   COM8_AEC	  0x01	  /* Auto exposure enable */
87 #define REG_COM9	0x14	/* Control 9  - gain ceiling */
88 #define REG_COM10	0x15	/* Control 10 */
89 #define   COM10_HSYNC	  0x40	  /* HSYNC instead of HREF */
90 #define   COM10_PCLK_HB	  0x20	  /* Suppress PCLK on horiz blank */
91 #define   COM10_HREF_REV  0x08	  /* Reverse HREF */
92 #define   COM10_VS_LEAD	  0x04	  /* VSYNC on clock leading edge */
93 #define   COM10_VS_NEG	  0x02	  /* VSYNC negative */
94 #define   COM10_HS_NEG	  0x01	  /* HSYNC negative */
95 #define REG_HSTART	0x17	/* Horiz start high bits */
96 #define REG_HSTOP	0x18	/* Horiz stop high bits */
97 #define REG_VSTART	0x19	/* Vert start high bits */
98 #define REG_VSTOP	0x1a	/* Vert stop high bits */
99 #define REG_PSHFT	0x1b	/* Pixel delay after HREF */
100 #define REG_MIDH	0x1c	/* Manuf. ID high */
101 #define REG_MIDL	0x1d	/* Manuf. ID low */
102 #define REG_MVFP	0x1e	/* Mirror / vflip */
103 #define   MVFP_MIRROR	  0x20	  /* Mirror image */
104 #define   MVFP_FLIP	  0x10	  /* Vertical flip */
105 
106 #define REG_AEW		0x24	/* AGC upper limit */
107 #define REG_AEB		0x25	/* AGC lower limit */
108 #define REG_VPT		0x26	/* AGC/AEC fast mode op region */
109 #define REG_HSYST	0x30	/* HSYNC rising edge delay */
110 #define REG_HSYEN	0x31	/* HSYNC falling edge delay */
111 #define REG_HREF	0x32	/* HREF pieces */
112 #define REG_TSLB	0x3a	/* lots of stuff */
113 #define   TSLB_YLAST	  0x04	  /* UYVY or VYUY - see com13 */
114 #define REG_COM11	0x3b	/* Control 11 */
115 #define   COM11_NIGHT	  0x80	  /* NIght mode enable */
116 #define   COM11_NMFR	  0x60	  /* Two bit NM frame rate */
117 #define   COM11_HZAUTO	  0x10	  /* Auto detect 50/60 Hz */
118 #define	  COM11_50HZ	  0x08	  /* Manual 50Hz select */
119 #define   COM11_EXP	  0x02
120 #define REG_COM12	0x3c	/* Control 12 */
121 #define   COM12_HREF	  0x80	  /* HREF always */
122 #define REG_COM13	0x3d	/* Control 13 */
123 #define   COM13_GAMMA	  0x80	  /* Gamma enable */
124 #define	  COM13_UVSAT	  0x40	  /* UV saturation auto adjustment */
125 #define   COM13_UVSWAP	  0x01	  /* V before U - w/TSLB */
126 #define REG_COM14	0x3e	/* Control 14 */
127 #define   COM14_DCWEN	  0x10	  /* DCW/PCLK-scale enable */
128 #define REG_EDGE	0x3f	/* Edge enhancement factor */
129 #define REG_COM15	0x40	/* Control 15 */
130 #define   COM15_R10F0	  0x00	  /* Data range 10 to F0 */
131 #define	  COM15_R01FE	  0x80	  /*            01 to FE */
132 #define   COM15_R00FF	  0xc0	  /*            00 to FF */
133 #define   COM15_RGB565	  0x10	  /* RGB565 output */
134 #define   COM15_RGB555	  0x30	  /* RGB555 output */
135 #define REG_COM16	0x41	/* Control 16 */
136 #define   COM16_AWBGAIN   0x08	  /* AWB gain enable */
137 #define REG_COM17	0x42	/* Control 17 */
138 #define   COM17_AECWIN	  0xc0	  /* AEC window - must match COM4 */
139 #define   COM17_CBAR	  0x08	  /* DSP Color bar */
140 
141 /*
142  * This matrix defines how the colors are generated, must be
143  * tweaked to adjust hue and saturation.
144  *
145  * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
146  *
147  * They are nine-bit signed quantities, with the sign bit
148  * stored in 0x58.  Sign for v-red is bit 0, and up from there.
149  */
150 #define	REG_CMATRIX_BASE 0x4f
151 #define   CMATRIX_LEN 6
152 #define REG_CMATRIX_SIGN 0x58
153 
154 
155 #define REG_BRIGHT	0x55	/* Brightness */
156 #define REG_CONTRAS	0x56	/* Contrast control */
157 
158 #define REG_GFIX	0x69	/* Fix gain control */
159 
160 #define REG_DBLV	0x6b	/* PLL control an debugging */
161 #define   DBLV_BYPASS	  0x0a	  /* Bypass PLL */
162 #define   DBLV_X4	  0x4a	  /* clock x4 */
163 #define   DBLV_X6	  0x8a	  /* clock x6 */
164 #define   DBLV_X8	  0xca	  /* clock x8 */
165 
166 #define REG_SCALING_XSC	0x70	/* Test pattern and horizontal scale factor */
167 #define   TEST_PATTTERN_0 0x80
168 #define REG_SCALING_YSC	0x71	/* Test pattern and vertical scale factor */
169 #define   TEST_PATTTERN_1 0x80
170 
171 #define REG_REG76	0x76	/* OV's name */
172 #define   R76_BLKPCOR	  0x80	  /* Black pixel correction enable */
173 #define   R76_WHTPCOR	  0x40	  /* White pixel correction enable */
174 
175 #define REG_RGB444	0x8c	/* RGB 444 control */
176 #define   R444_ENABLE	  0x02	  /* Turn on RGB444, overrides 5x5 */
177 #define   R444_RGBX	  0x01	  /* Empty nibble at end */
178 
179 #define REG_HAECC1	0x9f	/* Hist AEC/AGC control 1 */
180 #define REG_HAECC2	0xa0	/* Hist AEC/AGC control 2 */
181 
182 #define REG_BD50MAX	0xa5	/* 50hz banding step limit */
183 #define REG_HAECC3	0xa6	/* Hist AEC/AGC control 3 */
184 #define REG_HAECC4	0xa7	/* Hist AEC/AGC control 4 */
185 #define REG_HAECC5	0xa8	/* Hist AEC/AGC control 5 */
186 #define REG_HAECC6	0xa9	/* Hist AEC/AGC control 6 */
187 #define REG_HAECC7	0xaa	/* Hist AEC/AGC control 7 */
188 #define REG_BD60MAX	0xab	/* 60hz banding step limit */
189 
190 struct ov7670_win_size {
191 	int	width;
192 	int	height;
193 	unsigned char com7_bit;
194 	int	hstart;		/* Start/stop values for the camera.  Note */
195 	int	hstop;		/* that they do not always make complete */
196 	int	vstart;		/* sense to humans, but evidently the sensor */
197 	int	vstop;		/* will do the right thing... */
198 	struct regval_list *regs; /* Regs to tweak */
199 };
200 
201 struct ov7670_devtype {
202 	/* formats supported for each model */
203 	struct ov7670_win_size *win_sizes;
204 	unsigned int n_win_sizes;
205 	/* callbacks for frame rate control */
206 	int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
207 	void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
208 };
209 
210 /*
211  * Information we maintain about a known sensor.
212  */
213 struct ov7670_format_struct;  /* coming later */
214 struct ov7670_info {
215 	struct v4l2_subdev sd;
216 	struct media_pad pad;
217 	struct v4l2_ctrl_handler hdl;
218 	struct {
219 		/* gain cluster */
220 		struct v4l2_ctrl *auto_gain;
221 		struct v4l2_ctrl *gain;
222 	};
223 	struct {
224 		/* exposure cluster */
225 		struct v4l2_ctrl *auto_exposure;
226 		struct v4l2_ctrl *exposure;
227 	};
228 	struct {
229 		/* saturation/hue cluster */
230 		struct v4l2_ctrl *saturation;
231 		struct v4l2_ctrl *hue;
232 	};
233 	struct v4l2_mbus_framefmt format;
234 	struct ov7670_format_struct *fmt;  /* Current format */
235 	struct ov7670_win_size *wsize;
236 	struct clk *clk;
237 	int on;
238 	struct gpio_desc *resetb_gpio;
239 	struct gpio_desc *pwdn_gpio;
240 	unsigned int mbus_config;	/* Media bus configuration flags */
241 	int min_width;			/* Filter out smaller sizes */
242 	int min_height;			/* Filter out smaller sizes */
243 	int clock_speed;		/* External clock speed (MHz) */
244 	u8 clkrc;			/* Clock divider value */
245 	bool use_smbus;			/* Use smbus I/O instead of I2C */
246 	bool pll_bypass;
247 	bool pclk_hb_disable;
248 	const struct ov7670_devtype *devtype; /* Device specifics */
249 };
250 
to_state(struct v4l2_subdev * sd)251 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
252 {
253 	return container_of(sd, struct ov7670_info, sd);
254 }
255 
to_sd(struct v4l2_ctrl * ctrl)256 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
257 {
258 	return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
259 }
260 
261 
262 
263 /*
264  * The default register settings, as obtained from OmniVision.  There
265  * is really no making sense of most of these - lots of "reserved" values
266  * and such.
267  *
268  * These settings give VGA YUYV.
269  */
270 
271 struct regval_list {
272 	unsigned char reg_num;
273 	unsigned char value;
274 };
275 
276 static struct regval_list ov7670_default_regs[] = {
277 	{ REG_COM7, COM7_RESET },
278 /*
279  * Clock scale: 3 = 15fps
280  *              2 = 20fps
281  *              1 = 30fps
282  */
283 	{ REG_CLKRC, 0x1 },	/* OV: clock scale (30 fps) */
284 	{ REG_TSLB,  0x04 },	/* OV */
285 	{ REG_COM7, 0 },	/* VGA */
286 	/*
287 	 * Set the hardware window.  These values from OV don't entirely
288 	 * make sense - hstop is less than hstart.  But they work...
289 	 */
290 	{ REG_HSTART, 0x13 },	{ REG_HSTOP, 0x01 },
291 	{ REG_HREF, 0xb6 },	{ REG_VSTART, 0x02 },
292 	{ REG_VSTOP, 0x7a },	{ REG_VREF, 0x0a },
293 
294 	{ REG_COM3, 0 },	{ REG_COM14, 0 },
295 	/* Mystery scaling numbers */
296 	{ REG_SCALING_XSC, 0x3a },
297 	{ REG_SCALING_YSC, 0x35 },
298 	{ 0x72, 0x11 },		{ 0x73, 0xf0 },
299 	{ 0xa2, 0x02 },		{ REG_COM10, 0x0 },
300 
301 	/* Gamma curve values */
302 	{ 0x7a, 0x20 },		{ 0x7b, 0x10 },
303 	{ 0x7c, 0x1e },		{ 0x7d, 0x35 },
304 	{ 0x7e, 0x5a },		{ 0x7f, 0x69 },
305 	{ 0x80, 0x76 },		{ 0x81, 0x80 },
306 	{ 0x82, 0x88 },		{ 0x83, 0x8f },
307 	{ 0x84, 0x96 },		{ 0x85, 0xa3 },
308 	{ 0x86, 0xaf },		{ 0x87, 0xc4 },
309 	{ 0x88, 0xd7 },		{ 0x89, 0xe8 },
310 
311 	/* AGC and AEC parameters.  Note we start by disabling those features,
312 	   then turn them only after tweaking the values. */
313 	{ REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
314 	{ REG_GAIN, 0 },	{ REG_AECH, 0 },
315 	{ REG_COM4, 0x40 }, /* magic reserved bit */
316 	{ REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
317 	{ REG_BD50MAX, 0x05 },	{ REG_BD60MAX, 0x07 },
318 	{ REG_AEW, 0x95 },	{ REG_AEB, 0x33 },
319 	{ REG_VPT, 0xe3 },	{ REG_HAECC1, 0x78 },
320 	{ REG_HAECC2, 0x68 },	{ 0xa1, 0x03 }, /* magic */
321 	{ REG_HAECC3, 0xd8 },	{ REG_HAECC4, 0xd8 },
322 	{ REG_HAECC5, 0xf0 },	{ REG_HAECC6, 0x90 },
323 	{ REG_HAECC7, 0x94 },
324 	{ REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
325 
326 	/* Almost all of these are magic "reserved" values.  */
327 	{ REG_COM5, 0x61 },	{ REG_COM6, 0x4b },
328 	{ 0x16, 0x02 },		{ REG_MVFP, 0x07 },
329 	{ 0x21, 0x02 },		{ 0x22, 0x91 },
330 	{ 0x29, 0x07 },		{ 0x33, 0x0b },
331 	{ 0x35, 0x0b },		{ 0x37, 0x1d },
332 	{ 0x38, 0x71 },		{ 0x39, 0x2a },
333 	{ REG_COM12, 0x78 },	{ 0x4d, 0x40 },
334 	{ 0x4e, 0x20 },		{ REG_GFIX, 0 },
335 	{ 0x6b, 0x4a },		{ 0x74, 0x10 },
336 	{ 0x8d, 0x4f },		{ 0x8e, 0 },
337 	{ 0x8f, 0 },		{ 0x90, 0 },
338 	{ 0x91, 0 },		{ 0x96, 0 },
339 	{ 0x9a, 0 },		{ 0xb0, 0x84 },
340 	{ 0xb1, 0x0c },		{ 0xb2, 0x0e },
341 	{ 0xb3, 0x82 },		{ 0xb8, 0x0a },
342 
343 	/* More reserved magic, some of which tweaks white balance */
344 	{ 0x43, 0x0a },		{ 0x44, 0xf0 },
345 	{ 0x45, 0x34 },		{ 0x46, 0x58 },
346 	{ 0x47, 0x28 },		{ 0x48, 0x3a },
347 	{ 0x59, 0x88 },		{ 0x5a, 0x88 },
348 	{ 0x5b, 0x44 },		{ 0x5c, 0x67 },
349 	{ 0x5d, 0x49 },		{ 0x5e, 0x0e },
350 	{ 0x6c, 0x0a },		{ 0x6d, 0x55 },
351 	{ 0x6e, 0x11 },		{ 0x6f, 0x9f }, /* "9e for advance AWB" */
352 	{ 0x6a, 0x40 },		{ REG_BLUE, 0x40 },
353 	{ REG_RED, 0x60 },
354 	{ REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
355 
356 	/* Matrix coefficients */
357 	{ 0x4f, 0x80 },		{ 0x50, 0x80 },
358 	{ 0x51, 0 },		{ 0x52, 0x22 },
359 	{ 0x53, 0x5e },		{ 0x54, 0x80 },
360 	{ 0x58, 0x9e },
361 
362 	{ REG_COM16, COM16_AWBGAIN },	{ REG_EDGE, 0 },
363 	{ 0x75, 0x05 },		{ 0x76, 0xe1 },
364 	{ 0x4c, 0 },		{ 0x77, 0x01 },
365 	{ REG_COM13, 0xc3 },	{ 0x4b, 0x09 },
366 	{ 0xc9, 0x60 },		{ REG_COM16, 0x38 },
367 	{ 0x56, 0x40 },
368 
369 	{ 0x34, 0x11 },		{ REG_COM11, COM11_EXP|COM11_HZAUTO },
370 	{ 0xa4, 0x88 },		{ 0x96, 0 },
371 	{ 0x97, 0x30 },		{ 0x98, 0x20 },
372 	{ 0x99, 0x30 },		{ 0x9a, 0x84 },
373 	{ 0x9b, 0x29 },		{ 0x9c, 0x03 },
374 	{ 0x9d, 0x4c },		{ 0x9e, 0x3f },
375 	{ 0x78, 0x04 },
376 
377 	/* Extra-weird stuff.  Some sort of multiplexor register */
378 	{ 0x79, 0x01 },		{ 0xc8, 0xf0 },
379 	{ 0x79, 0x0f },		{ 0xc8, 0x00 },
380 	{ 0x79, 0x10 },		{ 0xc8, 0x7e },
381 	{ 0x79, 0x0a },		{ 0xc8, 0x80 },
382 	{ 0x79, 0x0b },		{ 0xc8, 0x01 },
383 	{ 0x79, 0x0c },		{ 0xc8, 0x0f },
384 	{ 0x79, 0x0d },		{ 0xc8, 0x20 },
385 	{ 0x79, 0x09 },		{ 0xc8, 0x80 },
386 	{ 0x79, 0x02 },		{ 0xc8, 0xc0 },
387 	{ 0x79, 0x03 },		{ 0xc8, 0x40 },
388 	{ 0x79, 0x05 },		{ 0xc8, 0x30 },
389 	{ 0x79, 0x26 },
390 
391 	{ 0xff, 0xff },	/* END MARKER */
392 };
393 
394 
395 /*
396  * Here we'll try to encapsulate the changes for just the output
397  * video format.
398  *
399  * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
400  *
401  * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
402  */
403 
404 
405 static struct regval_list ov7670_fmt_yuv422[] = {
406 	{ REG_COM7, 0x0 },  /* Selects YUV mode */
407 	{ REG_RGB444, 0 },	/* No RGB444 please */
408 	{ REG_COM1, 0 },	/* CCIR601 */
409 	{ REG_COM15, COM15_R00FF },
410 	{ REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
411 	{ 0x4f, 0x80 },		/* "matrix coefficient 1" */
412 	{ 0x50, 0x80 },		/* "matrix coefficient 2" */
413 	{ 0x51, 0    },		/* vb */
414 	{ 0x52, 0x22 },		/* "matrix coefficient 4" */
415 	{ 0x53, 0x5e },		/* "matrix coefficient 5" */
416 	{ 0x54, 0x80 },		/* "matrix coefficient 6" */
417 	{ REG_COM13, COM13_GAMMA|COM13_UVSAT },
418 	{ 0xff, 0xff },
419 };
420 
421 static struct regval_list ov7670_fmt_rgb565[] = {
422 	{ REG_COM7, COM7_RGB },	/* Selects RGB mode */
423 	{ REG_RGB444, 0 },	/* No RGB444 please */
424 	{ REG_COM1, 0x0 },	/* CCIR601 */
425 	{ REG_COM15, COM15_RGB565 },
426 	{ REG_COM9, 0x38 },	/* 16x gain ceiling; 0x8 is reserved bit */
427 	{ 0x4f, 0xb3 },		/* "matrix coefficient 1" */
428 	{ 0x50, 0xb3 },		/* "matrix coefficient 2" */
429 	{ 0x51, 0    },		/* vb */
430 	{ 0x52, 0x3d },		/* "matrix coefficient 4" */
431 	{ 0x53, 0xa7 },		/* "matrix coefficient 5" */
432 	{ 0x54, 0xe4 },		/* "matrix coefficient 6" */
433 	{ REG_COM13, COM13_GAMMA|COM13_UVSAT },
434 	{ 0xff, 0xff },
435 };
436 
437 static struct regval_list ov7670_fmt_rgb444[] = {
438 	{ REG_COM7, COM7_RGB },	/* Selects RGB mode */
439 	{ REG_RGB444, R444_ENABLE },	/* Enable xxxxrrrr ggggbbbb */
440 	{ REG_COM1, 0x0 },	/* CCIR601 */
441 	{ REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
442 	{ REG_COM9, 0x38 },	/* 16x gain ceiling; 0x8 is reserved bit */
443 	{ 0x4f, 0xb3 },		/* "matrix coefficient 1" */
444 	{ 0x50, 0xb3 },		/* "matrix coefficient 2" */
445 	{ 0x51, 0    },		/* vb */
446 	{ 0x52, 0x3d },		/* "matrix coefficient 4" */
447 	{ 0x53, 0xa7 },		/* "matrix coefficient 5" */
448 	{ 0x54, 0xe4 },		/* "matrix coefficient 6" */
449 	{ REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 },  /* Magic rsvd bit */
450 	{ 0xff, 0xff },
451 };
452 
453 static struct regval_list ov7670_fmt_raw[] = {
454 	{ REG_COM7, COM7_BAYER },
455 	{ REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
456 	{ REG_COM16, 0x3d }, /* Edge enhancement, denoise */
457 	{ REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
458 	{ 0xff, 0xff },
459 };
460 
461 
462 
463 /*
464  * Low-level register I/O.
465  *
466  * Note that there are two versions of these.  On the XO 1, the
467  * i2c controller only does SMBUS, so that's what we use.  The
468  * ov7670 is not really an SMBUS device, though, so the communication
469  * is not always entirely reliable.
470  */
ov7670_read_smbus(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)471 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
472 		unsigned char *value)
473 {
474 	struct i2c_client *client = v4l2_get_subdevdata(sd);
475 	int ret;
476 
477 	ret = i2c_smbus_read_byte_data(client, reg);
478 	if (ret >= 0) {
479 		*value = (unsigned char)ret;
480 		ret = 0;
481 	}
482 	return ret;
483 }
484 
485 
ov7670_write_smbus(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)486 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
487 		unsigned char value)
488 {
489 	struct i2c_client *client = v4l2_get_subdevdata(sd);
490 	int ret = i2c_smbus_write_byte_data(client, reg, value);
491 
492 	if (reg == REG_COM7 && (value & COM7_RESET))
493 		msleep(5);  /* Wait for reset to run */
494 	return ret;
495 }
496 
497 /*
498  * On most platforms, we'd rather do straight i2c I/O.
499  */
ov7670_read_i2c(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)500 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
501 		unsigned char *value)
502 {
503 	struct i2c_client *client = v4l2_get_subdevdata(sd);
504 	u8 data = reg;
505 	struct i2c_msg msg;
506 	int ret;
507 
508 	/*
509 	 * Send out the register address...
510 	 */
511 	msg.addr = client->addr;
512 	msg.flags = 0;
513 	msg.len = 1;
514 	msg.buf = &data;
515 	ret = i2c_transfer(client->adapter, &msg, 1);
516 	if (ret < 0) {
517 		printk(KERN_ERR "Error %d on register write\n", ret);
518 		return ret;
519 	}
520 	/*
521 	 * ...then read back the result.
522 	 */
523 	msg.flags = I2C_M_RD;
524 	ret = i2c_transfer(client->adapter, &msg, 1);
525 	if (ret >= 0) {
526 		*value = data;
527 		ret = 0;
528 	}
529 	return ret;
530 }
531 
532 
ov7670_write_i2c(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)533 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
534 		unsigned char value)
535 {
536 	struct i2c_client *client = v4l2_get_subdevdata(sd);
537 	struct i2c_msg msg;
538 	unsigned char data[2] = { reg, value };
539 	int ret;
540 
541 	msg.addr = client->addr;
542 	msg.flags = 0;
543 	msg.len = 2;
544 	msg.buf = data;
545 	ret = i2c_transfer(client->adapter, &msg, 1);
546 	if (ret > 0)
547 		ret = 0;
548 	if (reg == REG_COM7 && (value & COM7_RESET))
549 		msleep(5);  /* Wait for reset to run */
550 	return ret;
551 }
552 
ov7670_read(struct v4l2_subdev * sd,unsigned char reg,unsigned char * value)553 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
554 		unsigned char *value)
555 {
556 	struct ov7670_info *info = to_state(sd);
557 
558 	if (info->use_smbus)
559 		return ov7670_read_smbus(sd, reg, value);
560 	else
561 		return ov7670_read_i2c(sd, reg, value);
562 }
563 
ov7670_write(struct v4l2_subdev * sd,unsigned char reg,unsigned char value)564 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
565 		unsigned char value)
566 {
567 	struct ov7670_info *info = to_state(sd);
568 
569 	if (info->use_smbus)
570 		return ov7670_write_smbus(sd, reg, value);
571 	else
572 		return ov7670_write_i2c(sd, reg, value);
573 }
574 
ov7670_update_bits(struct v4l2_subdev * sd,unsigned char reg,unsigned char mask,unsigned char value)575 static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
576 		unsigned char mask, unsigned char value)
577 {
578 	unsigned char orig;
579 	int ret;
580 
581 	ret = ov7670_read(sd, reg, &orig);
582 	if (ret)
583 		return ret;
584 
585 	return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
586 }
587 
588 /*
589  * Write a list of register settings; ff/ff stops the process.
590  */
ov7670_write_array(struct v4l2_subdev * sd,struct regval_list * vals)591 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
592 {
593 	while (vals->reg_num != 0xff || vals->value != 0xff) {
594 		int ret = ov7670_write(sd, vals->reg_num, vals->value);
595 
596 		if (ret < 0)
597 			return ret;
598 		vals++;
599 	}
600 	return 0;
601 }
602 
603 
604 /*
605  * Stuff that knows about the sensor.
606  */
ov7670_reset(struct v4l2_subdev * sd,u32 val)607 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
608 {
609 	ov7670_write(sd, REG_COM7, COM7_RESET);
610 	msleep(1);
611 	return 0;
612 }
613 
614 
ov7670_init(struct v4l2_subdev * sd,u32 val)615 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
616 {
617 	return ov7670_write_array(sd, ov7670_default_regs);
618 }
619 
ov7670_detect(struct v4l2_subdev * sd)620 static int ov7670_detect(struct v4l2_subdev *sd)
621 {
622 	unsigned char v;
623 	int ret;
624 
625 	ret = ov7670_init(sd, 0);
626 	if (ret < 0)
627 		return ret;
628 	ret = ov7670_read(sd, REG_MIDH, &v);
629 	if (ret < 0)
630 		return ret;
631 	if (v != 0x7f) /* OV manuf. id. */
632 		return -ENODEV;
633 	ret = ov7670_read(sd, REG_MIDL, &v);
634 	if (ret < 0)
635 		return ret;
636 	if (v != 0xa2)
637 		return -ENODEV;
638 	/*
639 	 * OK, we know we have an OmniVision chip...but which one?
640 	 */
641 	ret = ov7670_read(sd, REG_PID, &v);
642 	if (ret < 0)
643 		return ret;
644 	if (v != 0x76)  /* PID + VER = 0x76 / 0x73 */
645 		return -ENODEV;
646 	ret = ov7670_read(sd, REG_VER, &v);
647 	if (ret < 0)
648 		return ret;
649 	if (v != 0x73)  /* PID + VER = 0x76 / 0x73 */
650 		return -ENODEV;
651 	return 0;
652 }
653 
654 
655 /*
656  * Store information about the video data format.  The color matrix
657  * is deeply tied into the format, so keep the relevant values here.
658  * The magic matrix numbers come from OmniVision.
659  */
660 static struct ov7670_format_struct {
661 	u32 mbus_code;
662 	enum v4l2_colorspace colorspace;
663 	struct regval_list *regs;
664 	int cmatrix[CMATRIX_LEN];
665 } ov7670_formats[] = {
666 	{
667 		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
668 		.colorspace	= V4L2_COLORSPACE_SRGB,
669 		.regs		= ov7670_fmt_yuv422,
670 		.cmatrix	= { 128, -128, 0, -34, -94, 128 },
671 	},
672 	{
673 		.mbus_code	= MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
674 		.colorspace	= V4L2_COLORSPACE_SRGB,
675 		.regs		= ov7670_fmt_rgb444,
676 		.cmatrix	= { 179, -179, 0, -61, -176, 228 },
677 	},
678 	{
679 		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
680 		.colorspace	= V4L2_COLORSPACE_SRGB,
681 		.regs		= ov7670_fmt_rgb565,
682 		.cmatrix	= { 179, -179, 0, -61, -176, 228 },
683 	},
684 	{
685 		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
686 		.colorspace	= V4L2_COLORSPACE_SRGB,
687 		.regs		= ov7670_fmt_raw,
688 		.cmatrix	= { 0, 0, 0, 0, 0, 0 },
689 	},
690 };
691 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
692 
693 
694 /*
695  * Then there is the issue of window sizes.  Try to capture the info here.
696  */
697 
698 /*
699  * QCIF mode is done (by OV) in a very strange way - it actually looks like
700  * VGA with weird scaling options - they do *not* use the canned QCIF mode
701  * which is allegedly provided by the sensor.  So here's the weird register
702  * settings.
703  */
704 static struct regval_list ov7670_qcif_regs[] = {
705 	{ REG_COM3, COM3_SCALEEN|COM3_DCWEN },
706 	{ REG_COM3, COM3_DCWEN },
707 	{ REG_COM14, COM14_DCWEN | 0x01},
708 	{ 0x73, 0xf1 },
709 	{ 0xa2, 0x52 },
710 	{ 0x7b, 0x1c },
711 	{ 0x7c, 0x28 },
712 	{ 0x7d, 0x3c },
713 	{ 0x7f, 0x69 },
714 	{ REG_COM9, 0x38 },
715 	{ 0xa1, 0x0b },
716 	{ 0x74, 0x19 },
717 	{ 0x9a, 0x80 },
718 	{ 0x43, 0x14 },
719 	{ REG_COM13, 0xc0 },
720 	{ 0xff, 0xff },
721 };
722 
723 static struct ov7670_win_size ov7670_win_sizes[] = {
724 	/* VGA */
725 	{
726 		.width		= VGA_WIDTH,
727 		.height		= VGA_HEIGHT,
728 		.com7_bit	= COM7_FMT_VGA,
729 		.hstart		= 158,	/* These values from */
730 		.hstop		=  14,	/* Omnivision */
731 		.vstart		=  10,
732 		.vstop		= 490,
733 		.regs		= NULL,
734 	},
735 	/* CIF */
736 	{
737 		.width		= CIF_WIDTH,
738 		.height		= CIF_HEIGHT,
739 		.com7_bit	= COM7_FMT_CIF,
740 		.hstart		= 170,	/* Empirically determined */
741 		.hstop		=  90,
742 		.vstart		=  14,
743 		.vstop		= 494,
744 		.regs		= NULL,
745 	},
746 	/* QVGA */
747 	{
748 		.width		= QVGA_WIDTH,
749 		.height		= QVGA_HEIGHT,
750 		.com7_bit	= COM7_FMT_QVGA,
751 		.hstart		= 168,	/* Empirically determined */
752 		.hstop		=  24,
753 		.vstart		=  12,
754 		.vstop		= 492,
755 		.regs		= NULL,
756 	},
757 	/* QCIF */
758 	{
759 		.width		= QCIF_WIDTH,
760 		.height		= QCIF_HEIGHT,
761 		.com7_bit	= COM7_FMT_VGA, /* see comment above */
762 		.hstart		= 456,	/* Empirically determined */
763 		.hstop		=  24,
764 		.vstart		=  14,
765 		.vstop		= 494,
766 		.regs		= ov7670_qcif_regs,
767 	}
768 };
769 
770 static struct ov7670_win_size ov7675_win_sizes[] = {
771 	/*
772 	 * Currently, only VGA is supported. Theoretically it could be possible
773 	 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
774 	 * base and tweak them empirically could be required.
775 	 */
776 	{
777 		.width		= VGA_WIDTH,
778 		.height		= VGA_HEIGHT,
779 		.com7_bit	= COM7_FMT_VGA,
780 		.hstart		= 158,	/* These values from */
781 		.hstop		=  14,	/* Omnivision */
782 		.vstart		=  14,  /* Empirically determined */
783 		.vstop		= 494,
784 		.regs		= NULL,
785 	}
786 };
787 
ov7675_get_framerate(struct v4l2_subdev * sd,struct v4l2_fract * tpf)788 static void ov7675_get_framerate(struct v4l2_subdev *sd,
789 				 struct v4l2_fract *tpf)
790 {
791 	struct ov7670_info *info = to_state(sd);
792 	u32 clkrc = info->clkrc;
793 	int pll_factor;
794 
795 	if (info->pll_bypass)
796 		pll_factor = 1;
797 	else
798 		pll_factor = PLL_FACTOR;
799 
800 	clkrc++;
801 	if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
802 		clkrc = (clkrc >> 1);
803 
804 	tpf->numerator = 1;
805 	tpf->denominator = (5 * pll_factor * info->clock_speed) /
806 			(4 * clkrc);
807 }
808 
ov7675_apply_framerate(struct v4l2_subdev * sd)809 static int ov7675_apply_framerate(struct v4l2_subdev *sd)
810 {
811 	struct ov7670_info *info = to_state(sd);
812 	int ret;
813 
814 	ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
815 	if (ret < 0)
816 		return ret;
817 
818 	return ov7670_write(sd, REG_DBLV,
819 			    info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
820 }
821 
ov7675_set_framerate(struct v4l2_subdev * sd,struct v4l2_fract * tpf)822 static int ov7675_set_framerate(struct v4l2_subdev *sd,
823 				 struct v4l2_fract *tpf)
824 {
825 	struct ov7670_info *info = to_state(sd);
826 	u32 clkrc;
827 	int pll_factor;
828 
829 	/*
830 	 * The formula is fps = 5/4*pixclk for YUV/RGB and
831 	 * fps = 5/2*pixclk for RAW.
832 	 *
833 	 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
834 	 *
835 	 */
836 	if (tpf->numerator == 0 || tpf->denominator == 0) {
837 		clkrc = 0;
838 	} else {
839 		pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
840 		clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
841 			(4 * tpf->denominator);
842 		if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
843 			clkrc = (clkrc << 1);
844 		clkrc--;
845 	}
846 
847 	/*
848 	 * The datasheet claims that clkrc = 0 will divide the input clock by 1
849 	 * but we've checked with an oscilloscope that it divides by 2 instead.
850 	 * So, if clkrc = 0 just bypass the divider.
851 	 */
852 	if (clkrc <= 0)
853 		clkrc = CLK_EXT;
854 	else if (clkrc > CLK_SCALE)
855 		clkrc = CLK_SCALE;
856 	info->clkrc = clkrc;
857 
858 	/* Recalculate frame rate */
859 	ov7675_get_framerate(sd, tpf);
860 
861 	/*
862 	 * If the device is not powered up by the host driver do
863 	 * not apply any changes to H/W at this time. Instead
864 	 * the framerate will be restored right after power-up.
865 	 */
866 	if (info->on)
867 		return ov7675_apply_framerate(sd);
868 
869 	return 0;
870 }
871 
ov7670_get_framerate_legacy(struct v4l2_subdev * sd,struct v4l2_fract * tpf)872 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
873 				 struct v4l2_fract *tpf)
874 {
875 	struct ov7670_info *info = to_state(sd);
876 
877 	tpf->numerator = 1;
878 	tpf->denominator = info->clock_speed;
879 	if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
880 		tpf->denominator /= (info->clkrc & CLK_SCALE);
881 }
882 
ov7670_set_framerate_legacy(struct v4l2_subdev * sd,struct v4l2_fract * tpf)883 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
884 					struct v4l2_fract *tpf)
885 {
886 	struct ov7670_info *info = to_state(sd);
887 	int div;
888 
889 	if (tpf->numerator == 0 || tpf->denominator == 0)
890 		div = 1;  /* Reset to full rate */
891 	else
892 		div = (tpf->numerator * info->clock_speed) / tpf->denominator;
893 	if (div == 0)
894 		div = 1;
895 	else if (div > CLK_SCALE)
896 		div = CLK_SCALE;
897 	info->clkrc = (info->clkrc & 0x80) | div;
898 	tpf->numerator = 1;
899 	tpf->denominator = info->clock_speed / div;
900 
901 	/*
902 	 * If the device is not powered up by the host driver do
903 	 * not apply any changes to H/W at this time. Instead
904 	 * the framerate will be restored right after power-up.
905 	 */
906 	if (info->on)
907 		return ov7670_write(sd, REG_CLKRC, info->clkrc);
908 
909 	return 0;
910 }
911 
912 /*
913  * Store a set of start/stop values into the camera.
914  */
ov7670_set_hw(struct v4l2_subdev * sd,int hstart,int hstop,int vstart,int vstop)915 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
916 		int vstart, int vstop)
917 {
918 	int ret;
919 	unsigned char v;
920 	/*
921 	 * Horizontal: 11 bits, top 8 live in hstart and hstop.  Bottom 3 of
922 	 * hstart are in href[2:0], bottom 3 of hstop in href[5:3].  There is
923 	 * a mystery "edge offset" value in the top two bits of href.
924 	 */
925 	ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
926 	if (ret)
927 		return ret;
928 	ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
929 	if (ret)
930 		return ret;
931 	ret = ov7670_read(sd, REG_HREF, &v);
932 	if (ret)
933 		return ret;
934 	v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
935 	msleep(10);
936 	ret = ov7670_write(sd, REG_HREF, v);
937 	if (ret)
938 		return ret;
939 	/* Vertical: similar arrangement, but only 10 bits. */
940 	ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
941 	if (ret)
942 		return ret;
943 	ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
944 	if (ret)
945 		return ret;
946 	ret = ov7670_read(sd, REG_VREF, &v);
947 	if (ret)
948 		return ret;
949 	v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
950 	msleep(10);
951 	return ov7670_write(sd, REG_VREF, v);
952 }
953 
954 
ov7670_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)955 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
956 		struct v4l2_subdev_state *sd_state,
957 		struct v4l2_subdev_mbus_code_enum *code)
958 {
959 	if (code->pad || code->index >= N_OV7670_FMTS)
960 		return -EINVAL;
961 
962 	code->code = ov7670_formats[code->index].mbus_code;
963 	return 0;
964 }
965 
ov7670_try_fmt_internal(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt,struct ov7670_format_struct ** ret_fmt,struct ov7670_win_size ** ret_wsize)966 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
967 		struct v4l2_mbus_framefmt *fmt,
968 		struct ov7670_format_struct **ret_fmt,
969 		struct ov7670_win_size **ret_wsize)
970 {
971 	int index, i;
972 	struct ov7670_win_size *wsize;
973 	struct ov7670_info *info = to_state(sd);
974 	unsigned int n_win_sizes = info->devtype->n_win_sizes;
975 	unsigned int win_sizes_limit = n_win_sizes;
976 
977 	for (index = 0; index < N_OV7670_FMTS; index++)
978 		if (ov7670_formats[index].mbus_code == fmt->code)
979 			break;
980 	if (index >= N_OV7670_FMTS) {
981 		/* default to first format */
982 		index = 0;
983 		fmt->code = ov7670_formats[0].mbus_code;
984 	}
985 	if (ret_fmt != NULL)
986 		*ret_fmt = ov7670_formats + index;
987 	/*
988 	 * Fields: the OV devices claim to be progressive.
989 	 */
990 	fmt->field = V4L2_FIELD_NONE;
991 
992 	/*
993 	 * Don't consider values that don't match min_height and min_width
994 	 * constraints.
995 	 */
996 	if (info->min_width || info->min_height)
997 		for (i = 0; i < n_win_sizes; i++) {
998 			wsize = info->devtype->win_sizes + i;
999 
1000 			if (wsize->width < info->min_width ||
1001 				wsize->height < info->min_height) {
1002 				win_sizes_limit = i;
1003 				break;
1004 			}
1005 		}
1006 	/*
1007 	 * Round requested image size down to the nearest
1008 	 * we support, but not below the smallest.
1009 	 */
1010 	for (wsize = info->devtype->win_sizes;
1011 	     wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
1012 		if (fmt->width >= wsize->width && fmt->height >= wsize->height)
1013 			break;
1014 	if (wsize >= info->devtype->win_sizes + win_sizes_limit)
1015 		wsize--;   /* Take the smallest one */
1016 	if (ret_wsize != NULL)
1017 		*ret_wsize = wsize;
1018 	/*
1019 	 * Note the size we'll actually handle.
1020 	 */
1021 	fmt->width = wsize->width;
1022 	fmt->height = wsize->height;
1023 	fmt->colorspace = ov7670_formats[index].colorspace;
1024 
1025 	info->format = *fmt;
1026 
1027 	return 0;
1028 }
1029 
ov7670_apply_fmt(struct v4l2_subdev * sd)1030 static int ov7670_apply_fmt(struct v4l2_subdev *sd)
1031 {
1032 	struct ov7670_info *info = to_state(sd);
1033 	struct ov7670_win_size *wsize = info->wsize;
1034 	unsigned char com7, com10 = 0;
1035 	int ret;
1036 
1037 	/*
1038 	 * COM7 is a pain in the ass, it doesn't like to be read then
1039 	 * quickly written afterward.  But we have everything we need
1040 	 * to set it absolutely here, as long as the format-specific
1041 	 * register sets list it first.
1042 	 */
1043 	com7 = info->fmt->regs[0].value;
1044 	com7 |= wsize->com7_bit;
1045 	ret = ov7670_write(sd, REG_COM7, com7);
1046 	if (ret)
1047 		return ret;
1048 
1049 	/*
1050 	 * Configure the media bus through COM10 register
1051 	 */
1052 	if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1053 		com10 |= COM10_VS_NEG;
1054 	if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1055 		com10 |= COM10_HREF_REV;
1056 	if (info->pclk_hb_disable)
1057 		com10 |= COM10_PCLK_HB;
1058 	ret = ov7670_write(sd, REG_COM10, com10);
1059 	if (ret)
1060 		return ret;
1061 
1062 	/*
1063 	 * Now write the rest of the array.  Also store start/stops
1064 	 */
1065 	ret = ov7670_write_array(sd, info->fmt->regs + 1);
1066 	if (ret)
1067 		return ret;
1068 
1069 	ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1070 			    wsize->vstop);
1071 	if (ret)
1072 		return ret;
1073 
1074 	if (wsize->regs) {
1075 		ret = ov7670_write_array(sd, wsize->regs);
1076 		if (ret)
1077 			return ret;
1078 	}
1079 
1080 	/*
1081 	 * If we're running RGB565, we must rewrite clkrc after setting
1082 	 * the other parameters or the image looks poor.  If we're *not*
1083 	 * doing RGB565, we must not rewrite clkrc or the image looks
1084 	 * *really* poor.
1085 	 *
1086 	 * (Update) Now that we retain clkrc state, we should be able
1087 	 * to write it unconditionally, and that will make the frame
1088 	 * rate persistent too.
1089 	 */
1090 	ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1091 	if (ret)
1092 		return ret;
1093 
1094 	return 0;
1095 }
1096 
1097 /*
1098  * Set a format.
1099  */
ov7670_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1100 static int ov7670_set_fmt(struct v4l2_subdev *sd,
1101 		struct v4l2_subdev_state *sd_state,
1102 		struct v4l2_subdev_format *format)
1103 {
1104 	struct ov7670_info *info = to_state(sd);
1105 	struct v4l2_mbus_framefmt *mbus_fmt;
1106 	int ret;
1107 
1108 	if (format->pad)
1109 		return -EINVAL;
1110 
1111 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1112 		ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
1113 		if (ret)
1114 			return ret;
1115 		mbus_fmt = v4l2_subdev_state_get_format(sd_state, format->pad);
1116 		*mbus_fmt = format->format;
1117 		return 0;
1118 	}
1119 
1120 	ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
1121 	if (ret)
1122 		return ret;
1123 
1124 	/*
1125 	 * If the device is not powered up by the host driver do
1126 	 * not apply any changes to H/W at this time. Instead
1127 	 * the frame format will be restored right after power-up.
1128 	 */
1129 	if (info->on)
1130 		return ov7670_apply_fmt(sd);
1131 
1132 	return 0;
1133 }
1134 
ov7670_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1135 static int ov7670_get_fmt(struct v4l2_subdev *sd,
1136 			  struct v4l2_subdev_state *sd_state,
1137 			  struct v4l2_subdev_format *format)
1138 {
1139 	struct ov7670_info *info = to_state(sd);
1140 	struct v4l2_mbus_framefmt *mbus_fmt;
1141 
1142 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1143 		mbus_fmt = v4l2_subdev_state_get_format(sd_state, 0);
1144 		format->format = *mbus_fmt;
1145 		return 0;
1146 	} else {
1147 		format->format = info->format;
1148 	}
1149 
1150 	return 0;
1151 }
1152 
1153 /*
1154  * Implement G/S_PARM.  There is a "high quality" mode we could try
1155  * to do someday; for now, we just do the frame rate tweak.
1156  */
ov7670_get_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * ival)1157 static int ov7670_get_frame_interval(struct v4l2_subdev *sd,
1158 				     struct v4l2_subdev_state *sd_state,
1159 				     struct v4l2_subdev_frame_interval *ival)
1160 {
1161 	struct ov7670_info *info = to_state(sd);
1162 
1163 	/*
1164 	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1165 	 * subdev active state API.
1166 	 */
1167 	if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1168 		return -EINVAL;
1169 
1170 	info->devtype->get_framerate(sd, &ival->interval);
1171 
1172 	return 0;
1173 }
1174 
ov7670_set_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * ival)1175 static int ov7670_set_frame_interval(struct v4l2_subdev *sd,
1176 				     struct v4l2_subdev_state *sd_state,
1177 				     struct v4l2_subdev_frame_interval *ival)
1178 {
1179 	struct v4l2_fract *tpf = &ival->interval;
1180 	struct ov7670_info *info = to_state(sd);
1181 
1182 	/*
1183 	 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1184 	 * subdev active state API.
1185 	 */
1186 	if (ival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1187 		return -EINVAL;
1188 
1189 	return info->devtype->set_framerate(sd, tpf);
1190 }
1191 
1192 
1193 /*
1194  * Frame intervals.  Since frame rates are controlled with the clock
1195  * divider, we can only do 30/n for integer n values.  So no continuous
1196  * or stepwise options.  Here we just pick a handful of logical values.
1197  */
1198 
1199 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1200 
ov7670_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)1201 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1202 				      struct v4l2_subdev_state *sd_state,
1203 				      struct v4l2_subdev_frame_interval_enum *fie)
1204 {
1205 	struct ov7670_info *info = to_state(sd);
1206 	unsigned int n_win_sizes = info->devtype->n_win_sizes;
1207 	int i;
1208 
1209 	if (fie->pad)
1210 		return -EINVAL;
1211 	if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1212 		return -EINVAL;
1213 
1214 	/*
1215 	 * Check if the width/height is valid.
1216 	 *
1217 	 * If a minimum width/height was requested, filter out the capture
1218 	 * windows that fall outside that.
1219 	 */
1220 	for (i = 0; i < n_win_sizes; i++) {
1221 		struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1222 
1223 		if (info->min_width && win->width < info->min_width)
1224 			continue;
1225 		if (info->min_height && win->height < info->min_height)
1226 			continue;
1227 		if (fie->width == win->width && fie->height == win->height)
1228 			break;
1229 	}
1230 	if (i == n_win_sizes)
1231 		return -EINVAL;
1232 	fie->interval.numerator = 1;
1233 	fie->interval.denominator = ov7670_frame_rates[fie->index];
1234 	return 0;
1235 }
1236 
1237 /*
1238  * Frame size enumeration
1239  */
ov7670_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1240 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1241 				  struct v4l2_subdev_state *sd_state,
1242 				  struct v4l2_subdev_frame_size_enum *fse)
1243 {
1244 	struct ov7670_info *info = to_state(sd);
1245 	int i;
1246 	int num_valid = -1;
1247 	__u32 index = fse->index;
1248 	unsigned int n_win_sizes = info->devtype->n_win_sizes;
1249 
1250 	if (fse->pad)
1251 		return -EINVAL;
1252 
1253 	/*
1254 	 * If a minimum width/height was requested, filter out the capture
1255 	 * windows that fall outside that.
1256 	 */
1257 	for (i = 0; i < n_win_sizes; i++) {
1258 		struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1259 
1260 		if (info->min_width && win->width < info->min_width)
1261 			continue;
1262 		if (info->min_height && win->height < info->min_height)
1263 			continue;
1264 		if (index == ++num_valid) {
1265 			fse->min_width = fse->max_width = win->width;
1266 			fse->min_height = fse->max_height = win->height;
1267 			return 0;
1268 		}
1269 	}
1270 
1271 	return -EINVAL;
1272 }
1273 
1274 /*
1275  * Code for dealing with controls.
1276  */
1277 
ov7670_store_cmatrix(struct v4l2_subdev * sd,int matrix[CMATRIX_LEN])1278 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1279 		int matrix[CMATRIX_LEN])
1280 {
1281 	int i, ret;
1282 	unsigned char signbits = 0;
1283 
1284 	/*
1285 	 * Weird crap seems to exist in the upper part of
1286 	 * the sign bits register, so let's preserve it.
1287 	 */
1288 	ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1289 	signbits &= 0xc0;
1290 
1291 	for (i = 0; i < CMATRIX_LEN; i++) {
1292 		unsigned char raw;
1293 
1294 		if (matrix[i] < 0) {
1295 			signbits |= (1 << i);
1296 			if (matrix[i] < -255)
1297 				raw = 0xff;
1298 			else
1299 				raw = (-1 * matrix[i]) & 0xff;
1300 		} else {
1301 			if (matrix[i] > 255)
1302 				raw = 0xff;
1303 			else
1304 				raw = matrix[i] & 0xff;
1305 		}
1306 		ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1307 		if (ret)
1308 			return ret;
1309 	}
1310 	return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1311 }
1312 
1313 
1314 /*
1315  * Hue also requires messing with the color matrix.  It also requires
1316  * trig functions, which tend not to be well supported in the kernel.
1317  * So here is a simple table of sine values, 0-90 degrees, in steps
1318  * of five degrees.  Values are multiplied by 1000.
1319  *
1320  * The following naive approximate trig functions require an argument
1321  * carefully limited to -180 <= theta <= 180.
1322  */
1323 #define SIN_STEP 5
1324 static const int ov7670_sin_table[] = {
1325 	   0,	 87,   173,   258,   342,   422,
1326 	 499,	573,   642,   707,   766,   819,
1327 	 866,	906,   939,   965,   984,   996,
1328 	1000
1329 };
1330 
ov7670_sine(int theta)1331 static int ov7670_sine(int theta)
1332 {
1333 	int chs = 1;
1334 	int sine;
1335 
1336 	if (theta < 0) {
1337 		theta = -theta;
1338 		chs = -1;
1339 	}
1340 	if (theta <= 90)
1341 		sine = ov7670_sin_table[theta/SIN_STEP];
1342 	else {
1343 		theta -= 90;
1344 		sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1345 	}
1346 	return sine*chs;
1347 }
1348 
ov7670_cosine(int theta)1349 static int ov7670_cosine(int theta)
1350 {
1351 	theta = 90 - theta;
1352 	if (theta > 180)
1353 		theta -= 360;
1354 	else if (theta < -180)
1355 		theta += 360;
1356 	return ov7670_sine(theta);
1357 }
1358 
1359 
1360 
1361 
ov7670_calc_cmatrix(struct ov7670_info * info,int matrix[CMATRIX_LEN],int sat,int hue)1362 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1363 		int matrix[CMATRIX_LEN], int sat, int hue)
1364 {
1365 	int i;
1366 	/*
1367 	 * Apply the current saturation setting first.
1368 	 */
1369 	for (i = 0; i < CMATRIX_LEN; i++)
1370 		matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1371 	/*
1372 	 * Then, if need be, rotate the hue value.
1373 	 */
1374 	if (hue != 0) {
1375 		int sinth, costh, tmpmatrix[CMATRIX_LEN];
1376 
1377 		memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1378 		sinth = ov7670_sine(hue);
1379 		costh = ov7670_cosine(hue);
1380 
1381 		matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1382 		matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1383 		matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1384 		matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1385 		matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1386 		matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1387 	}
1388 }
1389 
1390 
1391 
ov7670_s_sat_hue(struct v4l2_subdev * sd,int sat,int hue)1392 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1393 {
1394 	struct ov7670_info *info = to_state(sd);
1395 	int matrix[CMATRIX_LEN];
1396 
1397 	ov7670_calc_cmatrix(info, matrix, sat, hue);
1398 	return ov7670_store_cmatrix(sd, matrix);
1399 }
1400 
1401 
1402 /*
1403  * Some weird registers seem to store values in a sign/magnitude format!
1404  */
1405 
ov7670_abs_to_sm(unsigned char v)1406 static unsigned char ov7670_abs_to_sm(unsigned char v)
1407 {
1408 	if (v > 127)
1409 		return v & 0x7f;
1410 	return (128 - v) | 0x80;
1411 }
1412 
ov7670_s_brightness(struct v4l2_subdev * sd,int value)1413 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1414 {
1415 	unsigned char com8 = 0, v;
1416 
1417 	ov7670_read(sd, REG_COM8, &com8);
1418 	com8 &= ~COM8_AEC;
1419 	ov7670_write(sd, REG_COM8, com8);
1420 	v = ov7670_abs_to_sm(value);
1421 	return ov7670_write(sd, REG_BRIGHT, v);
1422 }
1423 
ov7670_s_contrast(struct v4l2_subdev * sd,int value)1424 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1425 {
1426 	return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1427 }
1428 
ov7670_s_hflip(struct v4l2_subdev * sd,int value)1429 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1430 {
1431 	unsigned char v = 0;
1432 	int ret;
1433 
1434 	ret = ov7670_read(sd, REG_MVFP, &v);
1435 	if (ret)
1436 		return ret;
1437 	if (value)
1438 		v |= MVFP_MIRROR;
1439 	else
1440 		v &= ~MVFP_MIRROR;
1441 	msleep(10);  /* FIXME */
1442 	return ov7670_write(sd, REG_MVFP, v);
1443 }
1444 
ov7670_s_vflip(struct v4l2_subdev * sd,int value)1445 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1446 {
1447 	unsigned char v = 0;
1448 	int ret;
1449 
1450 	ret = ov7670_read(sd, REG_MVFP, &v);
1451 	if (ret)
1452 		return ret;
1453 	if (value)
1454 		v |= MVFP_FLIP;
1455 	else
1456 		v &= ~MVFP_FLIP;
1457 	msleep(10);  /* FIXME */
1458 	return ov7670_write(sd, REG_MVFP, v);
1459 }
1460 
1461 /*
1462  * GAIN is split between REG_GAIN and REG_VREF[7:6].  If one believes
1463  * the data sheet, the VREF parts should be the most significant, but
1464  * experience shows otherwise.  There seems to be little value in
1465  * messing with the VREF bits, so we leave them alone.
1466  */
ov7670_g_gain(struct v4l2_subdev * sd,__s32 * value)1467 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1468 {
1469 	int ret;
1470 	unsigned char gain;
1471 
1472 	ret = ov7670_read(sd, REG_GAIN, &gain);
1473 	if (ret)
1474 		return ret;
1475 	*value = gain;
1476 	return 0;
1477 }
1478 
ov7670_s_gain(struct v4l2_subdev * sd,int value)1479 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1480 {
1481 	int ret;
1482 	unsigned char com8;
1483 
1484 	ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1485 	if (ret)
1486 		return ret;
1487 	/* Have to turn off AGC as well */
1488 	ret = ov7670_read(sd, REG_COM8, &com8);
1489 	if (ret)
1490 		return ret;
1491 	return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1492 }
1493 
1494 /*
1495  * Tweak autogain.
1496  */
ov7670_s_autogain(struct v4l2_subdev * sd,int value)1497 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1498 {
1499 	int ret;
1500 	unsigned char com8;
1501 
1502 	ret = ov7670_read(sd, REG_COM8, &com8);
1503 	if (ret == 0) {
1504 		if (value)
1505 			com8 |= COM8_AGC;
1506 		else
1507 			com8 &= ~COM8_AGC;
1508 		ret = ov7670_write(sd, REG_COM8, com8);
1509 	}
1510 	return ret;
1511 }
1512 
ov7670_s_exp(struct v4l2_subdev * sd,int value)1513 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1514 {
1515 	int ret;
1516 	unsigned char com1, com8, aech, aechh;
1517 
1518 	ret = ov7670_read(sd, REG_COM1, &com1) +
1519 		ov7670_read(sd, REG_COM8, &com8) +
1520 		ov7670_read(sd, REG_AECHH, &aechh);
1521 	if (ret)
1522 		return ret;
1523 
1524 	com1 = (com1 & 0xfc) | (value & 0x03);
1525 	aech = (value >> 2) & 0xff;
1526 	aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1527 	ret = ov7670_write(sd, REG_COM1, com1) +
1528 		ov7670_write(sd, REG_AECH, aech) +
1529 		ov7670_write(sd, REG_AECHH, aechh);
1530 	/* Have to turn off AEC as well */
1531 	if (ret == 0)
1532 		ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1533 	return ret;
1534 }
1535 
1536 /*
1537  * Tweak autoexposure.
1538  */
ov7670_s_autoexp(struct v4l2_subdev * sd,enum v4l2_exposure_auto_type value)1539 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1540 		enum v4l2_exposure_auto_type value)
1541 {
1542 	int ret;
1543 	unsigned char com8;
1544 
1545 	ret = ov7670_read(sd, REG_COM8, &com8);
1546 	if (ret == 0) {
1547 		if (value == V4L2_EXPOSURE_AUTO)
1548 			com8 |= COM8_AEC;
1549 		else
1550 			com8 &= ~COM8_AEC;
1551 		ret = ov7670_write(sd, REG_COM8, com8);
1552 	}
1553 	return ret;
1554 }
1555 
1556 static const char * const ov7670_test_pattern_menu[] = {
1557 	"No test output",
1558 	"Shifting \"1\"",
1559 	"8-bar color bar",
1560 	"Fade to gray color bar",
1561 };
1562 
ov7670_s_test_pattern(struct v4l2_subdev * sd,int value)1563 static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
1564 {
1565 	int ret;
1566 
1567 	ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
1568 				value & BIT(0) ? TEST_PATTTERN_0 : 0);
1569 	if (ret)
1570 		return ret;
1571 
1572 	return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
1573 				value & BIT(1) ? TEST_PATTTERN_1 : 0);
1574 }
1575 
ov7670_g_volatile_ctrl(struct v4l2_ctrl * ctrl)1576 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1577 {
1578 	struct v4l2_subdev *sd = to_sd(ctrl);
1579 	struct ov7670_info *info = to_state(sd);
1580 
1581 	switch (ctrl->id) {
1582 	case V4L2_CID_AUTOGAIN:
1583 		return ov7670_g_gain(sd, &info->gain->val);
1584 	}
1585 	return -EINVAL;
1586 }
1587 
ov7670_s_ctrl(struct v4l2_ctrl * ctrl)1588 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1589 {
1590 	struct v4l2_subdev *sd = to_sd(ctrl);
1591 	struct ov7670_info *info = to_state(sd);
1592 
1593 	switch (ctrl->id) {
1594 	case V4L2_CID_BRIGHTNESS:
1595 		return ov7670_s_brightness(sd, ctrl->val);
1596 	case V4L2_CID_CONTRAST:
1597 		return ov7670_s_contrast(sd, ctrl->val);
1598 	case V4L2_CID_SATURATION:
1599 		return ov7670_s_sat_hue(sd,
1600 				info->saturation->val, info->hue->val);
1601 	case V4L2_CID_VFLIP:
1602 		return ov7670_s_vflip(sd, ctrl->val);
1603 	case V4L2_CID_HFLIP:
1604 		return ov7670_s_hflip(sd, ctrl->val);
1605 	case V4L2_CID_AUTOGAIN:
1606 		/* Only set manual gain if auto gain is not explicitly
1607 		   turned on. */
1608 		if (!ctrl->val) {
1609 			/* ov7670_s_gain turns off auto gain */
1610 			return ov7670_s_gain(sd, info->gain->val);
1611 		}
1612 		return ov7670_s_autogain(sd, ctrl->val);
1613 	case V4L2_CID_EXPOSURE_AUTO:
1614 		/* Only set manual exposure if auto exposure is not explicitly
1615 		   turned on. */
1616 		if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1617 			/* ov7670_s_exp turns off auto exposure */
1618 			return ov7670_s_exp(sd, info->exposure->val);
1619 		}
1620 		return ov7670_s_autoexp(sd, ctrl->val);
1621 	case V4L2_CID_TEST_PATTERN:
1622 		return ov7670_s_test_pattern(sd, ctrl->val);
1623 	}
1624 	return -EINVAL;
1625 }
1626 
1627 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1628 	.s_ctrl = ov7670_s_ctrl,
1629 	.g_volatile_ctrl = ov7670_g_volatile_ctrl,
1630 };
1631 
1632 #ifdef CONFIG_VIDEO_ADV_DEBUG
ov7670_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1633 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1634 {
1635 	unsigned char val = 0;
1636 	int ret;
1637 
1638 	ret = ov7670_read(sd, reg->reg & 0xff, &val);
1639 	reg->val = val;
1640 	reg->size = 1;
1641 	return ret;
1642 }
1643 
ov7670_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1644 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1645 {
1646 	ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1647 	return 0;
1648 }
1649 #endif
1650 
ov7670_power_on(struct v4l2_subdev * sd)1651 static void ov7670_power_on(struct v4l2_subdev *sd)
1652 {
1653 	struct ov7670_info *info = to_state(sd);
1654 
1655 	if (info->on)
1656 		return;
1657 
1658 	clk_prepare_enable(info->clk);
1659 
1660 	if (info->pwdn_gpio)
1661 		gpiod_set_value(info->pwdn_gpio, 0);
1662 	if (info->resetb_gpio) {
1663 		gpiod_set_value(info->resetb_gpio, 1);
1664 		usleep_range(500, 1000);
1665 		gpiod_set_value(info->resetb_gpio, 0);
1666 	}
1667 	if (info->pwdn_gpio || info->resetb_gpio || info->clk)
1668 		usleep_range(3000, 5000);
1669 
1670 	info->on = true;
1671 }
1672 
ov7670_power_off(struct v4l2_subdev * sd)1673 static void ov7670_power_off(struct v4l2_subdev *sd)
1674 {
1675 	struct ov7670_info *info = to_state(sd);
1676 
1677 	if (!info->on)
1678 		return;
1679 
1680 	clk_disable_unprepare(info->clk);
1681 
1682 	if (info->pwdn_gpio)
1683 		gpiod_set_value(info->pwdn_gpio, 1);
1684 
1685 	info->on = false;
1686 }
1687 
ov7670_s_power(struct v4l2_subdev * sd,int on)1688 static int ov7670_s_power(struct v4l2_subdev *sd, int on)
1689 {
1690 	struct ov7670_info *info = to_state(sd);
1691 
1692 	if (info->on == on)
1693 		return 0;
1694 
1695 	if (on) {
1696 		ov7670_power_on(sd);
1697 		ov7670_init(sd, 0);
1698 		ov7670_apply_fmt(sd);
1699 		ov7675_apply_framerate(sd);
1700 		v4l2_ctrl_handler_setup(&info->hdl);
1701 	} else {
1702 		ov7670_power_off(sd);
1703 	}
1704 
1705 	return 0;
1706 }
1707 
ov7670_get_default_format(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * format)1708 static void ov7670_get_default_format(struct v4l2_subdev *sd,
1709 				      struct v4l2_mbus_framefmt *format)
1710 {
1711 	struct ov7670_info *info = to_state(sd);
1712 
1713 	format->width = info->devtype->win_sizes[0].width;
1714 	format->height = info->devtype->win_sizes[0].height;
1715 	format->colorspace = info->fmt->colorspace;
1716 	format->code = info->fmt->mbus_code;
1717 	format->field = V4L2_FIELD_NONE;
1718 }
1719 
ov7670_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1720 static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1721 {
1722 	struct v4l2_mbus_framefmt *format =
1723 				v4l2_subdev_state_get_format(fh->state, 0);
1724 
1725 	ov7670_get_default_format(sd, format);
1726 
1727 	return 0;
1728 }
1729 
1730 /* ----------------------------------------------------------------------- */
1731 
1732 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1733 	.reset = ov7670_reset,
1734 	.init = ov7670_init,
1735 	.s_power = ov7670_s_power,
1736 	.log_status = v4l2_ctrl_subdev_log_status,
1737 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1738 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1739 #ifdef CONFIG_VIDEO_ADV_DEBUG
1740 	.g_register = ov7670_g_register,
1741 	.s_register = ov7670_s_register,
1742 #endif
1743 };
1744 
1745 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1746 	.enum_frame_interval = ov7670_enum_frame_interval,
1747 	.enum_frame_size = ov7670_enum_frame_size,
1748 	.enum_mbus_code = ov7670_enum_mbus_code,
1749 	.get_fmt = ov7670_get_fmt,
1750 	.set_fmt = ov7670_set_fmt,
1751 	.get_frame_interval = ov7670_get_frame_interval,
1752 	.set_frame_interval = ov7670_set_frame_interval,
1753 };
1754 
1755 static const struct v4l2_subdev_ops ov7670_ops = {
1756 	.core = &ov7670_core_ops,
1757 	.pad = &ov7670_pad_ops,
1758 };
1759 
1760 static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
1761 	.open = ov7670_open,
1762 };
1763 
1764 /* ----------------------------------------------------------------------- */
1765 
ov7670_init_gpio(struct i2c_client * client,struct ov7670_info * info)1766 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1767 {
1768 	info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1769 			GPIOD_OUT_LOW);
1770 	if (IS_ERR(info->pwdn_gpio)) {
1771 		dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1772 		return PTR_ERR(info->pwdn_gpio);
1773 	}
1774 
1775 	info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1776 			GPIOD_OUT_LOW);
1777 	if (IS_ERR(info->resetb_gpio)) {
1778 		dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1779 		return PTR_ERR(info->resetb_gpio);
1780 	}
1781 
1782 	usleep_range(3000, 5000);
1783 
1784 	return 0;
1785 }
1786 
1787 /*
1788  * ov7670_parse_dt() - Parse device tree to collect mbus configuration
1789  *			properties
1790  */
ov7670_parse_dt(struct device * dev,struct ov7670_info * info)1791 static int ov7670_parse_dt(struct device *dev,
1792 			   struct ov7670_info *info)
1793 {
1794 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1795 	struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1796 	struct fwnode_handle *ep;
1797 	int ret;
1798 
1799 	if (!fwnode)
1800 		return -EINVAL;
1801 
1802 	info->pclk_hb_disable = false;
1803 	if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
1804 		info->pclk_hb_disable = true;
1805 
1806 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1807 	if (!ep)
1808 		return -EINVAL;
1809 
1810 	ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
1811 	fwnode_handle_put(ep);
1812 	if (ret)
1813 		return ret;
1814 
1815 	if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
1816 		dev_err(dev, "Unsupported media bus type\n");
1817 		return -EINVAL;
1818 	}
1819 	info->mbus_config = bus_cfg.bus.parallel.flags;
1820 
1821 	return 0;
1822 }
1823 
ov7670_probe(struct i2c_client * client)1824 static int ov7670_probe(struct i2c_client *client)
1825 {
1826 	struct v4l2_fract tpf;
1827 	struct v4l2_subdev *sd;
1828 	struct ov7670_info *info;
1829 	int ret;
1830 
1831 	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1832 	if (info == NULL)
1833 		return -ENOMEM;
1834 	sd = &info->sd;
1835 	v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1836 
1837 	sd->internal_ops = &ov7670_subdev_internal_ops;
1838 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1839 
1840 	info->clock_speed = 30; /* default: a guess */
1841 
1842 	if (dev_fwnode(&client->dev)) {
1843 		ret = ov7670_parse_dt(&client->dev, info);
1844 		if (ret)
1845 			return ret;
1846 
1847 	} else if (client->dev.platform_data) {
1848 		struct ov7670_config *config = client->dev.platform_data;
1849 
1850 		/*
1851 		 * Must apply configuration before initializing device, because it
1852 		 * selects I/O method.
1853 		 */
1854 		info->min_width = config->min_width;
1855 		info->min_height = config->min_height;
1856 		info->use_smbus = config->use_smbus;
1857 
1858 		if (config->clock_speed)
1859 			info->clock_speed = config->clock_speed;
1860 
1861 		if (config->pll_bypass)
1862 			info->pll_bypass = true;
1863 
1864 		if (config->pclk_hb_disable)
1865 			info->pclk_hb_disable = true;
1866 	}
1867 
1868 	info->clk = devm_clk_get_optional(&client->dev, "xclk");
1869 	if (IS_ERR(info->clk))
1870 		return PTR_ERR(info->clk);
1871 
1872 	ret = ov7670_init_gpio(client, info);
1873 	if (ret)
1874 		return ret;
1875 
1876 	ov7670_power_on(sd);
1877 
1878 	if (info->clk) {
1879 		info->clock_speed = clk_get_rate(info->clk) / 1000000;
1880 		if (info->clock_speed < 10 || info->clock_speed > 48) {
1881 			ret = -EINVAL;
1882 			goto power_off;
1883 		}
1884 	}
1885 
1886 	/* Make sure it's an ov7670 */
1887 	ret = ov7670_detect(sd);
1888 	if (ret) {
1889 		v4l_dbg(1, debug, client,
1890 			"chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1891 			client->addr << 1, client->adapter->name);
1892 		goto power_off;
1893 	}
1894 	v4l_info(client, "chip found @ 0x%02x (%s)\n",
1895 			client->addr << 1, client->adapter->name);
1896 
1897 	info->devtype = i2c_get_match_data(client);
1898 	info->fmt = &ov7670_formats[0];
1899 	info->wsize = &info->devtype->win_sizes[0];
1900 
1901 	ov7670_get_default_format(sd, &info->format);
1902 
1903 	info->clkrc = 0;
1904 
1905 	/* Set default frame rate to 30 fps */
1906 	tpf.numerator = 1;
1907 	tpf.denominator = 30;
1908 	info->devtype->set_framerate(sd, &tpf);
1909 
1910 	v4l2_ctrl_handler_init(&info->hdl, 10);
1911 	v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1912 			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1913 	v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1914 			V4L2_CID_CONTRAST, 0, 127, 1, 64);
1915 	v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1916 			V4L2_CID_VFLIP, 0, 1, 1, 0);
1917 	v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1918 			V4L2_CID_HFLIP, 0, 1, 1, 0);
1919 	info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1920 			V4L2_CID_SATURATION, 0, 256, 1, 128);
1921 	info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1922 			V4L2_CID_HUE, -180, 180, 5, 0);
1923 	info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1924 			V4L2_CID_GAIN, 0, 255, 1, 128);
1925 	info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1926 			V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1927 	info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1928 			V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1929 	info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1930 			V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1931 			V4L2_EXPOSURE_AUTO);
1932 	v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
1933 			V4L2_CID_TEST_PATTERN,
1934 			ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
1935 			ov7670_test_pattern_menu);
1936 	sd->ctrl_handler = &info->hdl;
1937 	if (info->hdl.error) {
1938 		ret = info->hdl.error;
1939 
1940 		goto hdl_free;
1941 	}
1942 	/*
1943 	 * We have checked empirically that hw allows to read back the gain
1944 	 * value chosen by auto gain but that's not the case for auto exposure.
1945 	 */
1946 	v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1947 	v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1948 			       V4L2_EXPOSURE_MANUAL, false);
1949 	v4l2_ctrl_cluster(2, &info->saturation);
1950 
1951 	info->pad.flags = MEDIA_PAD_FL_SOURCE;
1952 	info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1953 	ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
1954 	if (ret < 0)
1955 		goto hdl_free;
1956 
1957 	v4l2_ctrl_handler_setup(&info->hdl);
1958 
1959 	ret = v4l2_async_register_subdev(&info->sd);
1960 	if (ret < 0)
1961 		goto entity_cleanup;
1962 
1963 	ov7670_power_off(sd);
1964 	return 0;
1965 
1966 entity_cleanup:
1967 	media_entity_cleanup(&info->sd.entity);
1968 hdl_free:
1969 	v4l2_ctrl_handler_free(&info->hdl);
1970 power_off:
1971 	ov7670_power_off(sd);
1972 	return ret;
1973 }
1974 
ov7670_remove(struct i2c_client * client)1975 static void ov7670_remove(struct i2c_client *client)
1976 {
1977 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1978 	struct ov7670_info *info = to_state(sd);
1979 
1980 	v4l2_async_unregister_subdev(sd);
1981 	v4l2_ctrl_handler_free(&info->hdl);
1982 	media_entity_cleanup(&info->sd.entity);
1983 }
1984 
1985 static const struct ov7670_devtype ov7670_devdata = {
1986 	.win_sizes = ov7670_win_sizes,
1987 	.n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1988 	.set_framerate = ov7670_set_framerate_legacy,
1989 	.get_framerate = ov7670_get_framerate_legacy,
1990 };
1991 
1992 static const struct ov7670_devtype ov7675_devdata = {
1993 	.win_sizes = ov7675_win_sizes,
1994 	.n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1995 	.set_framerate = ov7675_set_framerate,
1996 	.get_framerate = ov7675_get_framerate,
1997 };
1998 
1999 static const struct i2c_device_id ov7670_id[] = {
2000 	{ "ov7670", (kernel_ulong_t)&ov7670_devdata },
2001 	{ "ov7675", (kernel_ulong_t)&ov7675_devdata },
2002 	{ /* sentinel */ }
2003 };
2004 MODULE_DEVICE_TABLE(i2c, ov7670_id);
2005 
2006 static const struct of_device_id ov7670_of_match[] = {
2007 	{ .compatible = "ovti,ov7670", &ov7670_devdata },
2008 	{ /* sentinel */ }
2009 };
2010 MODULE_DEVICE_TABLE(of, ov7670_of_match);
2011 
2012 static struct i2c_driver ov7670_driver = {
2013 	.driver = {
2014 		.name	= "ov7670",
2015 		.of_match_table = ov7670_of_match,
2016 	},
2017 	.probe		= ov7670_probe,
2018 	.remove		= ov7670_remove,
2019 	.id_table	= ov7670_id,
2020 };
2021 
2022 module_i2c_driver(ov7670_driver);
2023