1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Renesas R-Car CAN device driver 3 * 4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/types.h> 13 #include <linux/interrupt.h> 14 #include <linux/errno.h> 15 #include <linux/ethtool.h> 16 #include <linux/netdevice.h> 17 #include <linux/platform_device.h> 18 #include <linux/can/dev.h> 19 #include <linux/clk.h> 20 #include <linux/of.h> 21 #include <linux/pm_runtime.h> 22 23 #define RCAR_CAN_DRV_NAME "rcar_can" 24 25 /* Clock Select Register settings */ 26 enum CLKR { 27 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ 28 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ 29 CLKR_CLKEXT = 3, /* Externally input clock */ 30 }; 31 32 #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ 33 BIT(CLKR_CLKEXT)) 34 35 /* Mailbox configuration: 36 * mailbox 60 - 63 - Rx FIFO mailboxes 37 * mailbox 56 - 59 - Tx FIFO mailboxes 38 * non-FIFO mailboxes are not used 39 */ 40 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 41 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 42 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 43 #define RCAR_CAN_FIFO_DEPTH 4 44 45 /* Mailbox registers structure */ 46 struct rcar_can_mbox_regs { 47 u32 id; /* IDE and RTR bits, SID and EID */ 48 u8 stub; /* Not used */ 49 u8 dlc; /* Data Length Code - bits [0..3] */ 50 u8 data[8]; /* Data Bytes */ 51 u8 tsh; /* Time Stamp Higher Byte */ 52 u8 tsl; /* Time Stamp Lower Byte */ 53 }; 54 55 struct rcar_can_regs { 56 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 57 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 58 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 59 u32 mkivlr1; /* Mask Invalid Register 1 */ 60 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 61 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 62 u32 mkivlr0; /* Mask Invalid Register 0*/ 63 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 64 u8 pad_440[0x3c0]; 65 u8 mctl[64]; /* Message Control Registers */ 66 u16 ctlr; /* Control Register */ 67 u16 str; /* Status register */ 68 u8 bcr[3]; /* Bit Configuration Register */ 69 u8 clkr; /* Clock Select Register */ 70 u8 rfcr; /* Receive FIFO Control Register */ 71 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 72 u8 tfcr; /* Transmit FIFO Control Register */ 73 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 74 u8 eier; /* Error Interrupt Enable Register */ 75 u8 eifr; /* Error Interrupt Factor Judge Register */ 76 u8 recr; /* Receive Error Count Register */ 77 u8 tecr; /* Transmit Error Count Register */ 78 u8 ecsr; /* Error Code Store Register */ 79 u8 cssr; /* Channel Search Support Register */ 80 u8 mssr; /* Mailbox Search Status Register */ 81 u8 msmr; /* Mailbox Search Mode Register */ 82 u16 tsr; /* Time Stamp Register */ 83 u8 afsr; /* Acceptance Filter Support Register */ 84 u8 pad_857; 85 u8 tcr; /* Test Control Register */ 86 u8 pad_859[7]; 87 u8 ier; /* Interrupt Enable Register */ 88 u8 isr; /* Interrupt Status Register */ 89 u8 pad_862; 90 u8 mbsmr; /* Mailbox Search Mask Register */ 91 }; 92 93 struct rcar_can_priv { 94 struct can_priv can; /* Must be the first member! */ 95 struct net_device *ndev; 96 struct napi_struct napi; 97 struct rcar_can_regs __iomem *regs; 98 struct clk *can_clk; 99 u32 tx_head; 100 u32 tx_tail; 101 u8 clock_select; 102 u8 ier; 103 }; 104 105 static const struct can_bittiming_const rcar_can_bittiming_const = { 106 .name = RCAR_CAN_DRV_NAME, 107 .tseg1_min = 4, 108 .tseg1_max = 16, 109 .tseg2_min = 2, 110 .tseg2_max = 8, 111 .sjw_max = 4, 112 .brp_min = 1, 113 .brp_max = 1024, 114 .brp_inc = 1, 115 }; 116 117 /* Control Register bits */ 118 #define RCAR_CAN_CTLR_BOM GENMASK(12, 11) /* Bus-Off Recovery Mode Bits */ 119 #define RCAR_CAN_CTLR_BOM_ENT 1 /* Entry to halt mode */ 120 /* at bus-off entry */ 121 #define RCAR_CAN_CTLR_SLPM BIT(10) /* Sleep Mode */ 122 #define RCAR_CAN_CTLR_CANM GENMASK(9, 8) /* Operating Mode Select Bit */ 123 #define RCAR_CAN_CTLR_CANM_OPER 0 /* Operation Mode */ 124 #define RCAR_CAN_CTLR_CANM_RESET 1 /* Reset Mode */ 125 #define RCAR_CAN_CTLR_CANM_HALT 2 /* Halt Mode */ 126 #define RCAR_CAN_CTLR_CANM_FORCE_RESET 3 /* Reset Mode (forcible) */ 127 #define RCAR_CAN_CTLR_MLM BIT(3) /* Message Lost Mode Select */ 128 #define RCAR_CAN_CTLR_IDFM GENMASK(2, 1) /* ID Format Mode Select Bits */ 129 #define RCAR_CAN_CTLR_IDFM_STD 0 /* Standard ID mode */ 130 #define RCAR_CAN_CTLR_IDFM_EXT 1 /* Extended ID mode */ 131 #define RCAR_CAN_CTLR_IDFM_MIXED 2 /* Mixed ID mode */ 132 #define RCAR_CAN_CTLR_MBM BIT(0) /* Mailbox Mode select */ 133 134 /* Status Register bits */ 135 #define RCAR_CAN_STR_RSTST BIT(8) /* Reset Status Bit */ 136 137 /* FIFO Received ID Compare Registers 0 and 1 bits */ 138 #define RCAR_CAN_FIDCR_IDE BIT(31) /* ID Extension Bit */ 139 #define RCAR_CAN_FIDCR_RTR BIT(30) /* Remote Transmission Request Bit */ 140 141 /* Receive FIFO Control Register bits */ 142 #define RCAR_CAN_RFCR_RFEST BIT(7) /* Receive FIFO Empty Status Flag */ 143 #define RCAR_CAN_RFCR_RFE BIT(0) /* Receive FIFO Enable */ 144 145 /* Transmit FIFO Control Register bits */ 146 #define RCAR_CAN_TFCR_TFUST GENMASK(3, 1) /* Transmit FIFO Unsent Message */ 147 /* Number Status Bits */ 148 #define RCAR_CAN_TFCR_TFE BIT(0) /* Transmit FIFO Enable */ 149 150 #define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 151 /* for Rx mailboxes 0-31 */ 152 #define RCAR_CAN_N_RX_MKREGS2 8 153 154 /* Bit Configuration Register settings */ 155 #define RCAR_CAN_BCR_TSEG1 GENMASK(23, 20) 156 #define RCAR_CAN_BCR_BRP GENMASK(17, 8) 157 #define RCAR_CAN_BCR_SJW GENMASK(5, 4) 158 #define RCAR_CAN_BCR_TSEG2 GENMASK(2, 0) 159 160 /* Mailbox and Mask Registers bits */ 161 #define RCAR_CAN_IDE BIT(31) /* ID Extension */ 162 #define RCAR_CAN_RTR BIT(30) /* Remote Transmission Request */ 163 #define RCAR_CAN_SID GENMASK(28, 18) /* Standard ID */ 164 #define RCAR_CAN_EID GENMASK(28, 0) /* Extended ID */ 165 166 /* Mailbox Interrupt Enable Register 1 bits */ 167 #define RCAR_CAN_MIER1_RXFIE BIT(28) /* Receive FIFO Interrupt Enable */ 168 #define RCAR_CAN_MIER1_TXFIE BIT(24) /* Transmit FIFO Interrupt Enable */ 169 170 /* Interrupt Enable Register bits */ 171 #define RCAR_CAN_IER_ERSIE BIT(5) /* Error (ERS) Interrupt Enable Bit */ 172 #define RCAR_CAN_IER_RXFIE BIT(4) /* Reception FIFO Interrupt */ 173 /* Enable Bit */ 174 #define RCAR_CAN_IER_TXFIE BIT(3) /* Transmission FIFO Interrupt */ 175 /* Enable Bit */ 176 /* Interrupt Status Register bits */ 177 #define RCAR_CAN_ISR_ERSF BIT(5) /* Error (ERS) Interrupt Status Bit */ 178 #define RCAR_CAN_ISR_RXFF BIT(4) /* Reception FIFO Interrupt */ 179 /* Status Bit */ 180 #define RCAR_CAN_ISR_TXFF BIT(3) /* Transmission FIFO Interrupt */ 181 /* Status Bit */ 182 183 /* Error Interrupt Enable Register bits */ 184 #define RCAR_CAN_EIER_BLIE BIT(7) /* Bus Lock Interrupt Enable */ 185 #define RCAR_CAN_EIER_OLIE BIT(6) /* Overload Frame Transmit */ 186 /* Interrupt Enable */ 187 #define RCAR_CAN_EIER_ORIE BIT(5) /* Receive Overrun Interrupt Enable */ 188 #define RCAR_CAN_EIER_BORIE BIT(4) /* Bus-Off Recovery Interrupt Enable */ 189 #define RCAR_CAN_EIER_BOEIE BIT(3) /* Bus-Off Entry Interrupt Enable */ 190 #define RCAR_CAN_EIER_EPIE BIT(2) /* Error Passive Interrupt Enable */ 191 #define RCAR_CAN_EIER_EWIE BIT(1) /* Error Warning Interrupt Enable */ 192 #define RCAR_CAN_EIER_BEIE BIT(0) /* Bus Error Interrupt Enable */ 193 194 /* Error Interrupt Factor Judge Register bits */ 195 #define RCAR_CAN_EIFR_BLIF BIT(7) /* Bus Lock Detect Flag */ 196 #define RCAR_CAN_EIFR_OLIF BIT(6) /* Overload Frame Transmission */ 197 /* Detect Flag */ 198 #define RCAR_CAN_EIFR_ORIF BIT(5) /* Receive Overrun Detect Flag */ 199 #define RCAR_CAN_EIFR_BORIF BIT(4) /* Bus-Off Recovery Detect Flag */ 200 #define RCAR_CAN_EIFR_BOEIF BIT(3) /* Bus-Off Entry Detect Flag */ 201 #define RCAR_CAN_EIFR_EPIF BIT(2) /* Error Passive Detect Flag */ 202 #define RCAR_CAN_EIFR_EWIF BIT(1) /* Error Warning Detect Flag */ 203 #define RCAR_CAN_EIFR_BEIF BIT(0) /* Bus Error Detect Flag */ 204 205 /* Error Code Store Register bits */ 206 #define RCAR_CAN_ECSR_EDPM BIT(7) /* Error Display Mode Select Bit */ 207 #define RCAR_CAN_ECSR_ADEF BIT(6) /* ACK Delimiter Error Flag */ 208 #define RCAR_CAN_ECSR_BE0F BIT(5) /* Bit Error (dominant) Flag */ 209 #define RCAR_CAN_ECSR_BE1F BIT(4) /* Bit Error (recessive) Flag */ 210 #define RCAR_CAN_ECSR_CEF BIT(3) /* CRC Error Flag */ 211 #define RCAR_CAN_ECSR_AEF BIT(2) /* ACK Error Flag */ 212 #define RCAR_CAN_ECSR_FEF BIT(1) /* Form Error Flag */ 213 #define RCAR_CAN_ECSR_SEF BIT(0) /* Stuff Error Flag */ 214 215 #define RCAR_CAN_NAPI_WEIGHT 4 216 #define MAX_STR_READS 0x100 217 218 static void tx_failure_cleanup(struct net_device *ndev) 219 { 220 int i; 221 222 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 223 can_free_echo_skb(ndev, i, NULL); 224 } 225 226 static void rcar_can_error(struct net_device *ndev) 227 { 228 struct rcar_can_priv *priv = netdev_priv(ndev); 229 struct can_frame *cf; 230 struct sk_buff *skb; 231 u8 eifr, txerr = 0, rxerr = 0; 232 233 /* Propagate the error condition to the CAN stack */ 234 skb = alloc_can_err_skb(ndev, &cf); 235 236 eifr = readb(&priv->regs->eifr); 237 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 238 txerr = readb(&priv->regs->tecr); 239 rxerr = readb(&priv->regs->recr); 240 if (skb) 241 cf->can_id |= CAN_ERR_CRTL; 242 } 243 if (eifr & RCAR_CAN_EIFR_BEIF) { 244 int rx_errors = 0, tx_errors = 0; 245 u8 ecsr; 246 247 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 248 if (skb) 249 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 250 251 ecsr = readb(&priv->regs->ecsr); 252 if (ecsr & RCAR_CAN_ECSR_ADEF) { 253 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 254 tx_errors++; 255 writeb((u8)~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 256 if (skb) 257 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; 258 } 259 if (ecsr & RCAR_CAN_ECSR_BE0F) { 260 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 261 tx_errors++; 262 writeb((u8)~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 263 if (skb) 264 cf->data[2] |= CAN_ERR_PROT_BIT0; 265 } 266 if (ecsr & RCAR_CAN_ECSR_BE1F) { 267 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 268 tx_errors++; 269 writeb((u8)~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 270 if (skb) 271 cf->data[2] |= CAN_ERR_PROT_BIT1; 272 } 273 if (ecsr & RCAR_CAN_ECSR_CEF) { 274 netdev_dbg(priv->ndev, "CRC Error\n"); 275 rx_errors++; 276 writeb((u8)~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 277 if (skb) 278 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 279 } 280 if (ecsr & RCAR_CAN_ECSR_AEF) { 281 netdev_dbg(priv->ndev, "ACK Error\n"); 282 tx_errors++; 283 writeb((u8)~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 284 if (skb) { 285 cf->can_id |= CAN_ERR_ACK; 286 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 287 } 288 } 289 if (ecsr & RCAR_CAN_ECSR_FEF) { 290 netdev_dbg(priv->ndev, "Form Error\n"); 291 rx_errors++; 292 writeb((u8)~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 293 if (skb) 294 cf->data[2] |= CAN_ERR_PROT_FORM; 295 } 296 if (ecsr & RCAR_CAN_ECSR_SEF) { 297 netdev_dbg(priv->ndev, "Stuff Error\n"); 298 rx_errors++; 299 writeb((u8)~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 300 if (skb) 301 cf->data[2] |= CAN_ERR_PROT_STUFF; 302 } 303 304 priv->can.can_stats.bus_error++; 305 ndev->stats.rx_errors += rx_errors; 306 ndev->stats.tx_errors += tx_errors; 307 writeb((u8)~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 308 } 309 if (eifr & RCAR_CAN_EIFR_EWIF) { 310 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 311 priv->can.state = CAN_STATE_ERROR_WARNING; 312 priv->can.can_stats.error_warning++; 313 /* Clear interrupt condition */ 314 writeb((u8)~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 315 if (skb) 316 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 317 CAN_ERR_CRTL_RX_WARNING; 318 } 319 if (eifr & RCAR_CAN_EIFR_EPIF) { 320 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 321 priv->can.state = CAN_STATE_ERROR_PASSIVE; 322 priv->can.can_stats.error_passive++; 323 /* Clear interrupt condition */ 324 writeb((u8)~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 325 if (skb) 326 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 327 CAN_ERR_CRTL_RX_PASSIVE; 328 } 329 if (eifr & RCAR_CAN_EIFR_BOEIF) { 330 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 331 tx_failure_cleanup(ndev); 332 priv->ier = RCAR_CAN_IER_ERSIE; 333 writeb(priv->ier, &priv->regs->ier); 334 priv->can.state = CAN_STATE_BUS_OFF; 335 /* Clear interrupt condition */ 336 writeb((u8)~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 337 priv->can.can_stats.bus_off++; 338 can_bus_off(ndev); 339 if (skb) 340 cf->can_id |= CAN_ERR_BUSOFF; 341 } else if (skb) { 342 cf->can_id |= CAN_ERR_CNT; 343 cf->data[6] = txerr; 344 cf->data[7] = rxerr; 345 } 346 if (eifr & RCAR_CAN_EIFR_ORIF) { 347 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 348 ndev->stats.rx_over_errors++; 349 ndev->stats.rx_errors++; 350 writeb((u8)~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 351 if (skb) { 352 cf->can_id |= CAN_ERR_CRTL; 353 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 354 } 355 } 356 if (eifr & RCAR_CAN_EIFR_OLIF) { 357 netdev_dbg(priv->ndev, 358 "Overload Frame Transmission error interrupt\n"); 359 ndev->stats.rx_over_errors++; 360 ndev->stats.rx_errors++; 361 writeb((u8)~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 362 if (skb) { 363 cf->can_id |= CAN_ERR_PROT; 364 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 365 } 366 } 367 368 if (skb) 369 netif_rx(skb); 370 } 371 372 static void rcar_can_tx_done(struct net_device *ndev) 373 { 374 struct rcar_can_priv *priv = netdev_priv(ndev); 375 struct net_device_stats *stats = &ndev->stats; 376 u8 isr; 377 378 while (1) { 379 u8 unsent = FIELD_GET(RCAR_CAN_TFCR_TFUST, 380 readb(&priv->regs->tfcr)); 381 382 if (priv->tx_head - priv->tx_tail <= unsent) 383 break; 384 stats->tx_packets++; 385 stats->tx_bytes += 386 can_get_echo_skb(ndev, 387 priv->tx_tail % RCAR_CAN_FIFO_DEPTH, 388 NULL); 389 390 priv->tx_tail++; 391 netif_wake_queue(ndev); 392 } 393 /* Clear interrupt */ 394 isr = readb(&priv->regs->isr); 395 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 396 } 397 398 static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 399 { 400 struct net_device *ndev = dev_id; 401 struct rcar_can_priv *priv = netdev_priv(ndev); 402 u8 isr; 403 404 isr = readb(&priv->regs->isr); 405 if (!(isr & priv->ier)) 406 return IRQ_NONE; 407 408 if (isr & RCAR_CAN_ISR_ERSF) 409 rcar_can_error(ndev); 410 411 if (isr & RCAR_CAN_ISR_TXFF) 412 rcar_can_tx_done(ndev); 413 414 if (isr & RCAR_CAN_ISR_RXFF) { 415 if (napi_schedule_prep(&priv->napi)) { 416 /* Disable Rx FIFO interrupts */ 417 priv->ier &= ~RCAR_CAN_IER_RXFIE; 418 writeb(priv->ier, &priv->regs->ier); 419 __napi_schedule(&priv->napi); 420 } 421 } 422 423 return IRQ_HANDLED; 424 } 425 426 static void rcar_can_set_bittiming(struct net_device *ndev) 427 { 428 struct rcar_can_priv *priv = netdev_priv(ndev); 429 struct can_bittiming *bt = &priv->can.bittiming; 430 u32 bcr; 431 432 bcr = FIELD_PREP(RCAR_CAN_BCR_TSEG1, bt->phase_seg1 + bt->prop_seg - 1) | 433 FIELD_PREP(RCAR_CAN_BCR_BRP, bt->brp - 1) | 434 FIELD_PREP(RCAR_CAN_BCR_SJW, bt->sjw - 1) | 435 FIELD_PREP(RCAR_CAN_BCR_TSEG2, bt->phase_seg2 - 1); 436 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 437 * All the registers are big-endian but they get byte-swapped on 32-bit 438 * read/write (but not on 8-bit, contrary to the manuals)... 439 */ 440 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 441 } 442 443 static void rcar_can_start(struct net_device *ndev) 444 { 445 struct rcar_can_priv *priv = netdev_priv(ndev); 446 u16 ctlr; 447 int i; 448 449 /* Set controller to known mode: 450 * - FIFO mailbox mode 451 * - accept all messages 452 * - overrun mode 453 * CAN is in sleep mode after MCU hardware or software reset. 454 */ 455 ctlr = readw(&priv->regs->ctlr); 456 ctlr &= ~RCAR_CAN_CTLR_SLPM; 457 writew(ctlr, &priv->regs->ctlr); 458 /* Go to reset mode */ 459 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_CANM, RCAR_CAN_CTLR_CANM_FORCE_RESET); 460 writew(ctlr, &priv->regs->ctlr); 461 for (i = 0; i < MAX_STR_READS; i++) { 462 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 463 break; 464 } 465 rcar_can_set_bittiming(ndev); 466 /* Select mixed ID mode */ 467 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_IDFM, RCAR_CAN_CTLR_IDFM_MIXED); 468 /* Entry to halt mode automatically at bus-off */ 469 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_BOM, RCAR_CAN_CTLR_BOM_ENT); 470 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 471 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 472 writew(ctlr, &priv->regs->ctlr); 473 474 /* Accept all SID and EID */ 475 writel(0, &priv->regs->mkr_2_9[6]); 476 writel(0, &priv->regs->mkr_2_9[7]); 477 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 478 writel(0, &priv->regs->mkivlr1); 479 /* Accept all frames */ 480 writel(0, &priv->regs->fidcr[0]); 481 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 482 /* Enable and configure FIFO mailbox interrupts */ 483 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 484 485 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 486 RCAR_CAN_IER_TXFIE; 487 writeb(priv->ier, &priv->regs->ier); 488 489 /* Accumulate error codes */ 490 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 491 /* Enable error interrupts */ 492 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 493 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 494 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 495 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 496 priv->can.state = CAN_STATE_ERROR_ACTIVE; 497 498 /* Go to operation mode */ 499 ctlr &= ~RCAR_CAN_CTLR_CANM; 500 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_CANM, RCAR_CAN_CTLR_CANM_OPER); 501 writew(ctlr, &priv->regs->ctlr); 502 for (i = 0; i < MAX_STR_READS; i++) { 503 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 504 break; 505 } 506 /* Enable Rx and Tx FIFO */ 507 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 508 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 509 } 510 511 static int rcar_can_open(struct net_device *ndev) 512 { 513 struct rcar_can_priv *priv = netdev_priv(ndev); 514 int err; 515 516 err = pm_runtime_resume_and_get(ndev->dev.parent); 517 if (err) { 518 netdev_err(ndev, "pm_runtime_resume_and_get() failed %pe\n", 519 ERR_PTR(err)); 520 goto out; 521 } 522 err = clk_prepare_enable(priv->can_clk); 523 if (err) { 524 netdev_err(ndev, "failed to enable CAN clock: %pe\n", 525 ERR_PTR(err)); 526 goto out_rpm; 527 } 528 err = open_candev(ndev); 529 if (err) { 530 netdev_err(ndev, "open_candev() failed %pe\n", ERR_PTR(err)); 531 goto out_can_clock; 532 } 533 napi_enable(&priv->napi); 534 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 535 if (err) { 536 netdev_err(ndev, "request_irq(%d) failed %pe\n", ndev->irq, 537 ERR_PTR(err)); 538 goto out_close; 539 } 540 rcar_can_start(ndev); 541 netif_start_queue(ndev); 542 return 0; 543 out_close: 544 napi_disable(&priv->napi); 545 close_candev(ndev); 546 out_can_clock: 547 clk_disable_unprepare(priv->can_clk); 548 out_rpm: 549 pm_runtime_put(ndev->dev.parent); 550 out: 551 return err; 552 } 553 554 static void rcar_can_stop(struct net_device *ndev) 555 { 556 struct rcar_can_priv *priv = netdev_priv(ndev); 557 u16 ctlr; 558 int i; 559 560 /* Go to (force) reset mode */ 561 ctlr = readw(&priv->regs->ctlr); 562 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_CANM, RCAR_CAN_CTLR_CANM_FORCE_RESET); 563 writew(ctlr, &priv->regs->ctlr); 564 for (i = 0; i < MAX_STR_READS; i++) { 565 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 566 break; 567 } 568 writel(0, &priv->regs->mier0); 569 writel(0, &priv->regs->mier1); 570 writeb(0, &priv->regs->ier); 571 writeb(0, &priv->regs->eier); 572 /* Go to sleep mode */ 573 ctlr |= RCAR_CAN_CTLR_SLPM; 574 writew(ctlr, &priv->regs->ctlr); 575 priv->can.state = CAN_STATE_STOPPED; 576 } 577 578 static int rcar_can_close(struct net_device *ndev) 579 { 580 struct rcar_can_priv *priv = netdev_priv(ndev); 581 582 netif_stop_queue(ndev); 583 rcar_can_stop(ndev); 584 free_irq(ndev->irq, ndev); 585 napi_disable(&priv->napi); 586 clk_disable_unprepare(priv->can_clk); 587 pm_runtime_put(ndev->dev.parent); 588 close_candev(ndev); 589 return 0; 590 } 591 592 static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 593 struct net_device *ndev) 594 { 595 struct rcar_can_priv *priv = netdev_priv(ndev); 596 struct can_frame *cf = (struct can_frame *)skb->data; 597 u32 data, i; 598 599 if (can_dev_dropped_skb(ndev, skb)) 600 return NETDEV_TX_OK; 601 602 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 603 data = FIELD_PREP(RCAR_CAN_EID, cf->can_id & CAN_EFF_MASK) | 604 RCAR_CAN_IDE; 605 else /* Standard frame format */ 606 data = FIELD_PREP(RCAR_CAN_SID, cf->can_id & CAN_SFF_MASK); 607 608 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 609 data |= RCAR_CAN_RTR; 610 } else { 611 for (i = 0; i < cf->len; i++) 612 writeb(cf->data[i], 613 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 614 } 615 616 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 617 618 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 619 620 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0); 621 priv->tx_head++; 622 /* Start Tx: write 0xff to the TFPCR register to increment 623 * the CPU-side pointer for the transmit FIFO to the next 624 * mailbox location 625 */ 626 writeb(0xff, &priv->regs->tfpcr); 627 /* Stop the queue if we've filled all FIFO entries */ 628 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 629 netif_stop_queue(ndev); 630 631 return NETDEV_TX_OK; 632 } 633 634 static const struct net_device_ops rcar_can_netdev_ops = { 635 .ndo_open = rcar_can_open, 636 .ndo_stop = rcar_can_close, 637 .ndo_start_xmit = rcar_can_start_xmit, 638 }; 639 640 static const struct ethtool_ops rcar_can_ethtool_ops = { 641 .get_ts_info = ethtool_op_get_ts_info, 642 }; 643 644 static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 645 { 646 struct net_device_stats *stats = &priv->ndev->stats; 647 struct can_frame *cf; 648 struct sk_buff *skb; 649 u32 data; 650 u8 dlc; 651 652 skb = alloc_can_skb(priv->ndev, &cf); 653 if (!skb) { 654 stats->rx_dropped++; 655 return; 656 } 657 658 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 659 if (data & RCAR_CAN_IDE) 660 cf->can_id = FIELD_GET(RCAR_CAN_EID, data) | CAN_EFF_FLAG; 661 else 662 cf->can_id = FIELD_GET(RCAR_CAN_SID, data); 663 664 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 665 cf->len = can_cc_dlc2len(dlc); 666 if (data & RCAR_CAN_RTR) { 667 cf->can_id |= CAN_RTR_FLAG; 668 } else { 669 for (dlc = 0; dlc < cf->len; dlc++) 670 cf->data[dlc] = 671 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 672 673 stats->rx_bytes += cf->len; 674 } 675 stats->rx_packets++; 676 677 netif_receive_skb(skb); 678 } 679 680 static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 681 { 682 struct rcar_can_priv *priv = container_of(napi, 683 struct rcar_can_priv, napi); 684 int num_pkts; 685 686 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 687 u8 rfcr, isr; 688 689 isr = readb(&priv->regs->isr); 690 /* Clear interrupt bit */ 691 if (isr & RCAR_CAN_ISR_RXFF) 692 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 693 rfcr = readb(&priv->regs->rfcr); 694 if (rfcr & RCAR_CAN_RFCR_RFEST) 695 break; 696 rcar_can_rx_pkt(priv); 697 /* Write 0xff to the RFPCR register to increment 698 * the CPU-side pointer for the receive FIFO 699 * to the next mailbox location 700 */ 701 writeb(0xff, &priv->regs->rfpcr); 702 } 703 /* All packets processed */ 704 if (num_pkts < quota) { 705 napi_complete_done(napi, num_pkts); 706 priv->ier |= RCAR_CAN_IER_RXFIE; 707 writeb(priv->ier, &priv->regs->ier); 708 } 709 return num_pkts; 710 } 711 712 static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 713 { 714 switch (mode) { 715 case CAN_MODE_START: 716 rcar_can_start(ndev); 717 netif_wake_queue(ndev); 718 return 0; 719 default: 720 return -EOPNOTSUPP; 721 } 722 } 723 724 static int rcar_can_get_berr_counter(const struct net_device *ndev, 725 struct can_berr_counter *bec) 726 { 727 struct rcar_can_priv *priv = netdev_priv(ndev); 728 int err; 729 730 err = pm_runtime_resume_and_get(ndev->dev.parent); 731 if (err) 732 return err; 733 734 bec->txerr = readb(&priv->regs->tecr); 735 bec->rxerr = readb(&priv->regs->recr); 736 737 pm_runtime_put(ndev->dev.parent); 738 739 return 0; 740 } 741 742 static const char * const clock_names[] = { 743 [CLKR_CLKP1] = "clkp1", 744 [CLKR_CLKP2] = "clkp2", 745 [CLKR_CLKEXT] = "can_clk", 746 }; 747 748 static int rcar_can_probe(struct platform_device *pdev) 749 { 750 struct device *dev = &pdev->dev; 751 struct rcar_can_priv *priv; 752 struct net_device *ndev; 753 void __iomem *addr; 754 u32 clock_select = CLKR_CLKP1; 755 int err = -ENODEV; 756 int irq; 757 758 of_property_read_u32(dev->of_node, "renesas,can-clock-select", 759 &clock_select); 760 761 irq = platform_get_irq(pdev, 0); 762 if (irq < 0) { 763 err = irq; 764 goto fail; 765 } 766 767 addr = devm_platform_ioremap_resource(pdev, 0); 768 if (IS_ERR(addr)) { 769 err = PTR_ERR(addr); 770 goto fail; 771 } 772 773 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 774 if (!ndev) { 775 err = -ENOMEM; 776 goto fail; 777 } 778 779 priv = netdev_priv(ndev); 780 781 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) { 782 err = -EINVAL; 783 dev_err(dev, "invalid CAN clock selected\n"); 784 goto fail_clk; 785 } 786 priv->can_clk = devm_clk_get(dev, clock_names[clock_select]); 787 if (IS_ERR(priv->can_clk)) { 788 dev_err(dev, "cannot get CAN clock: %pe\n", priv->can_clk); 789 err = PTR_ERR(priv->can_clk); 790 goto fail_clk; 791 } 792 793 ndev->netdev_ops = &rcar_can_netdev_ops; 794 ndev->ethtool_ops = &rcar_can_ethtool_ops; 795 ndev->irq = irq; 796 ndev->flags |= IFF_ECHO; 797 priv->ndev = ndev; 798 priv->regs = addr; 799 priv->clock_select = clock_select; 800 priv->can.clock.freq = clk_get_rate(priv->can_clk); 801 priv->can.bittiming_const = &rcar_can_bittiming_const; 802 priv->can.do_set_mode = rcar_can_do_set_mode; 803 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 804 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 805 platform_set_drvdata(pdev, ndev); 806 SET_NETDEV_DEV(ndev, dev); 807 808 netif_napi_add_weight(ndev, &priv->napi, rcar_can_rx_poll, 809 RCAR_CAN_NAPI_WEIGHT); 810 811 pm_runtime_enable(dev); 812 813 err = register_candev(ndev); 814 if (err) { 815 dev_err(dev, "register_candev() failed %pe\n", ERR_PTR(err)); 816 goto fail_rpm; 817 } 818 819 dev_info(dev, "device registered (IRQ%d)\n", ndev->irq); 820 821 return 0; 822 fail_rpm: 823 pm_runtime_disable(dev); 824 netif_napi_del(&priv->napi); 825 fail_clk: 826 free_candev(ndev); 827 fail: 828 return err; 829 } 830 831 static void rcar_can_remove(struct platform_device *pdev) 832 { 833 struct net_device *ndev = platform_get_drvdata(pdev); 834 struct rcar_can_priv *priv = netdev_priv(ndev); 835 836 unregister_candev(ndev); 837 pm_runtime_disable(&pdev->dev); 838 netif_napi_del(&priv->napi); 839 free_candev(ndev); 840 } 841 842 static int rcar_can_suspend(struct device *dev) 843 { 844 struct net_device *ndev = dev_get_drvdata(dev); 845 struct rcar_can_priv *priv = netdev_priv(ndev); 846 u16 ctlr; 847 848 if (!netif_running(ndev)) 849 return 0; 850 851 netif_stop_queue(ndev); 852 netif_device_detach(ndev); 853 854 ctlr = readw(&priv->regs->ctlr); 855 ctlr |= FIELD_PREP(RCAR_CAN_CTLR_CANM, RCAR_CAN_CTLR_CANM_HALT); 856 writew(ctlr, &priv->regs->ctlr); 857 ctlr |= RCAR_CAN_CTLR_SLPM; 858 writew(ctlr, &priv->regs->ctlr); 859 priv->can.state = CAN_STATE_SLEEPING; 860 861 pm_runtime_put(dev); 862 return 0; 863 } 864 865 static int rcar_can_resume(struct device *dev) 866 { 867 struct net_device *ndev = dev_get_drvdata(dev); 868 int err; 869 870 if (!netif_running(ndev)) 871 return 0; 872 873 err = pm_runtime_resume_and_get(dev); 874 if (err) { 875 netdev_err(ndev, "pm_runtime_resume_and_get() failed %pe\n", 876 ERR_PTR(err)); 877 return err; 878 } 879 880 rcar_can_start(ndev); 881 882 netif_device_attach(ndev); 883 netif_start_queue(ndev); 884 885 return 0; 886 } 887 888 static DEFINE_SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, 889 rcar_can_resume); 890 891 static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 892 { .compatible = "renesas,can-r8a7778" }, 893 { .compatible = "renesas,can-r8a7779" }, 894 { .compatible = "renesas,can-r8a7790" }, 895 { .compatible = "renesas,can-r8a7791" }, 896 { .compatible = "renesas,rcar-gen1-can" }, 897 { .compatible = "renesas,rcar-gen2-can" }, 898 { .compatible = "renesas,rcar-gen3-can" }, 899 { } 900 }; 901 MODULE_DEVICE_TABLE(of, rcar_can_of_table); 902 903 static struct platform_driver rcar_can_driver = { 904 .driver = { 905 .name = RCAR_CAN_DRV_NAME, 906 .of_match_table = of_match_ptr(rcar_can_of_table), 907 .pm = pm_sleep_ptr(&rcar_can_pm_ops), 908 }, 909 .probe = rcar_can_probe, 910 .remove = rcar_can_remove, 911 }; 912 913 module_platform_driver(rcar_can_driver); 914 915 MODULE_AUTHOR("Cogent Embedded, Inc."); 916 MODULE_LICENSE("GPL"); 917 MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 918 MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 919