1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 #include <linux/xarray.h> 48 49 #include <drm/ttm/ttm_bo.h> 50 #include <drm/ttm/ttm_placement.h> 51 52 #include <drm/amdgpu_drm.h> 53 #include <drm/drm_gem.h> 54 #include <drm/drm_ioctl.h> 55 56 #include <kgd_kfd_interface.h> 57 #include "dm_pp_interface.h" 58 #include "kgd_pp_interface.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_utils.h" 62 #include "amdgpu_mode.h" 63 #include "amdgpu_ih.h" 64 #include "amdgpu_irq.h" 65 #include "amdgpu_ucode.h" 66 #include "amdgpu_ttm.h" 67 #include "amdgpu_psp.h" 68 #include "amdgpu_gds.h" 69 #include "amdgpu_sync.h" 70 #include "amdgpu_ring.h" 71 #include "amdgpu_vm.h" 72 #include "amdgpu_dpm.h" 73 #include "amdgpu_acp.h" 74 #include "amdgpu_uvd.h" 75 #include "amdgpu_vce.h" 76 #include "amdgpu_vcn.h" 77 #include "amdgpu_jpeg.h" 78 #include "amdgpu_vpe.h" 79 #include "amdgpu_umsch_mm.h" 80 #include "amdgpu_gmc.h" 81 #include "amdgpu_gfx.h" 82 #include "amdgpu_sdma.h" 83 #include "amdgpu_lsdma.h" 84 #include "amdgpu_nbio.h" 85 #include "amdgpu_reg_access.h" 86 #include "amdgpu_hdp.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_mes_ctx.h" 91 #include "amdgpu_gart.h" 92 #include "amdgpu_debugfs.h" 93 #include "amdgpu_job.h" 94 #include "amdgpu_bo_list.h" 95 #include "amdgpu_gem.h" 96 #include "amdgpu_doorbell.h" 97 #include "amdgpu_amdkfd.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_umc.h" 100 #include "amdgpu_mmhub.h" 101 #include "amdgpu_gfxhub.h" 102 #include "amdgpu_df.h" 103 #include "amdgpu_smuio.h" 104 #include "amdgpu_fdinfo.h" 105 #include "amdgpu_mca.h" 106 #include "amdgpu_ras.h" 107 #include "amdgpu_lockdep.h" 108 #include "amdgpu_cper.h" 109 #include "amdgpu_xcp.h" 110 #include "amdgpu_seq64.h" 111 #include "amdgpu_reg_state.h" 112 #include "amdgpu_userq.h" 113 #include "amdgpu_eviction_fence.h" 114 #include "amdgpu_wb.h" 115 #include "amdgpu_ip.h" 116 #include "amdgpu_mes.h" 117 #include "amdgpu_sa.h" 118 #include "amdgpu_acpi.h" 119 #if defined(CONFIG_DRM_AMD_ISP) 120 #include "amdgpu_isp.h" 121 #endif 122 123 #define MAX_GPU_INSTANCE 64 124 125 #define GFX_SLICE_PERIOD_MS 250 126 127 struct amdgpu_gpu_instance { 128 struct amdgpu_device *adev; 129 int mgpu_fan_enabled; 130 }; 131 132 struct amdgpu_mgpu_info { 133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 134 struct mutex mutex; 135 uint32_t num_gpu; 136 uint32_t num_dgpu; 137 uint32_t num_apu; 138 }; 139 140 struct amdgpu_hwip_reg_entry { 141 u32 hwip; 142 u32 inst; 143 u32 seg; 144 u32 reg_offset; 145 const char *reg_name; 146 }; 147 148 struct amdgpu_watchdog_timer { 149 bool timeout_fatal_disable; 150 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 151 }; 152 153 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 154 155 /* 156 * Modules parameters. 157 */ 158 extern int amdgpu_modeset; 159 extern int amdgpu_iommu_perfopt; 160 extern unsigned int amdgpu_vram_limit; 161 extern int amdgpu_vis_vram_limit; 162 extern int amdgpu_gart_size; 163 extern int amdgpu_gtt_size; 164 extern int amdgpu_moverate; 165 extern int amdgpu_audio; 166 extern int amdgpu_disp_priority; 167 extern int amdgpu_hw_i2c; 168 extern int amdgpu_pcie_gen2; 169 extern int amdgpu_msi; 170 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 171 extern int amdgpu_dpm; 172 extern int amdgpu_fw_load_type; 173 extern int amdgpu_aspm; 174 extern int amdgpu_runtime_pm; 175 extern uint amdgpu_ip_block_mask; 176 extern int amdgpu_bapm; 177 extern int amdgpu_deep_color; 178 extern int amdgpu_vm_size; 179 extern int amdgpu_vm_block_size; 180 extern int amdgpu_vm_fragment_size; 181 extern int amdgpu_vm_fault_stop; 182 extern int amdgpu_vm_debug; 183 extern int amdgpu_vm_update_mode; 184 extern int amdgpu_exp_hw_support; 185 extern int amdgpu_dc; 186 extern int amdgpu_sched_jobs; 187 extern int amdgpu_sched_hw_submission; 188 extern uint amdgpu_pcie_gen_cap; 189 extern uint amdgpu_pcie_lane_cap; 190 extern u64 amdgpu_cg_mask; 191 extern uint amdgpu_pg_mask; 192 extern uint amdgpu_sdma_phase_quantum; 193 extern char *amdgpu_disable_cu; 194 extern char *amdgpu_virtual_display; 195 extern uint amdgpu_pp_feature_mask; 196 extern uint amdgpu_force_long_training; 197 extern int amdgpu_lbpw; 198 extern int amdgpu_compute_multipipe; 199 extern int amdgpu_gpu_recovery; 200 extern int amdgpu_emu_mode; 201 extern uint amdgpu_smu_memory_pool_size; 202 extern int amdgpu_smu_pptable_id; 203 extern uint amdgpu_dc_feature_mask; 204 extern uint amdgpu_freesync_vid_mode; 205 extern uint amdgpu_dc_debug_mask; 206 extern uint amdgpu_dc_visual_confirm; 207 extern int amdgpu_dm_abm_level; 208 extern int amdgpu_backlight; 209 extern int amdgpu_damage_clips; 210 extern struct amdgpu_mgpu_info mgpu_info; 211 extern int amdgpu_ras_enable; 212 extern uint amdgpu_ras_mask; 213 extern int amdgpu_bad_page_threshold; 214 extern bool amdgpu_ignore_bad_page_threshold; 215 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 216 extern int amdgpu_async_gfx_ring; 217 extern int amdgpu_mcbp; 218 extern int amdgpu_discovery; 219 extern int amdgpu_mes_log_enable; 220 extern int amdgpu_uni_mes; 221 extern int amdgpu_noretry; 222 extern int amdgpu_force_asic_type; 223 extern int amdgpu_smartshift_bias; 224 extern int amdgpu_use_xgmi_p2p; 225 extern int amdgpu_mtype_local; 226 extern int amdgpu_enforce_isolation; 227 extern uint amdgpu_debug_mask; 228 #ifdef CONFIG_HSA_AMD 229 extern int sched_policy; 230 extern bool debug_evictions; 231 extern bool no_system_mem_limit; 232 extern int halt_if_hws_hang; 233 extern uint amdgpu_svm_default_granularity; 234 #else 235 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 236 static const bool __maybe_unused debug_evictions; /* = false */ 237 static const bool __maybe_unused no_system_mem_limit; 238 static const int __maybe_unused halt_if_hws_hang; 239 #endif 240 #ifdef CONFIG_HSA_AMD_P2P 241 extern bool pcie_p2p; 242 #endif 243 244 extern int amdgpu_tmz; 245 extern int amdgpu_reset_method; 246 247 #ifdef CONFIG_DRM_AMDGPU_SI 248 extern int amdgpu_si_support; 249 #endif 250 #ifdef CONFIG_DRM_AMDGPU_CIK 251 extern int amdgpu_cik_support; 252 #endif 253 extern int amdgpu_num_kcq; 254 255 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 256 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 257 extern int amdgpu_vcnfw_log; 258 extern int amdgpu_sg_display; 259 extern int amdgpu_umsch_mm; 260 extern int amdgpu_seamless; 261 extern int amdgpu_umsch_mm_fwlog; 262 263 extern int amdgpu_user_partt_mode; 264 extern int amdgpu_agp; 265 extern int amdgpu_rebar; 266 267 extern int amdgpu_wbrf; 268 extern int amdgpu_user_queue; 269 extern int amdgpu_ptl; 270 271 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 272 273 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 274 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 275 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 276 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 277 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 278 #define AMDGPUFB_CONN_LIMIT 4 279 #define AMDGPU_BIOS_NUM_SCRATCH 16 280 281 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 282 283 /* hard reset data */ 284 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 285 286 /* reset flags */ 287 #define AMDGPU_RESET_GFX (1 << 0) 288 #define AMDGPU_RESET_COMPUTE (1 << 1) 289 #define AMDGPU_RESET_DMA (1 << 2) 290 #define AMDGPU_RESET_CP (1 << 3) 291 #define AMDGPU_RESET_GRBM (1 << 4) 292 #define AMDGPU_RESET_DMA1 (1 << 5) 293 #define AMDGPU_RESET_RLC (1 << 6) 294 #define AMDGPU_RESET_SEM (1 << 7) 295 #define AMDGPU_RESET_IH (1 << 8) 296 #define AMDGPU_RESET_VMC (1 << 9) 297 #define AMDGPU_RESET_MC (1 << 10) 298 #define AMDGPU_RESET_DISPLAY (1 << 11) 299 #define AMDGPU_RESET_UVD (1 << 12) 300 #define AMDGPU_RESET_VCE (1 << 13) 301 #define AMDGPU_RESET_VCE1 (1 << 14) 302 303 /* reset mask */ 304 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 305 #define AMDGPU_RESET_TYPE_SOFT_RECOVERY (1 << 1) /* soft recovery, eg. kill shaders */ 306 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 307 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 308 #define AMDGPU_RESET_TYPE_IP_BLOCK_SOFT_RESET (1 << 4) /* soft-resets an IP block */ 309 310 /* max cursor sizes (in pixels) */ 311 #define CIK_CURSOR_WIDTH 128 312 #define CIK_CURSOR_HEIGHT 128 313 314 /* smart shift bias level limits */ 315 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 316 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 317 318 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 319 #define AMDGPU_SWCTF_EXTRA_DELAY 50 320 321 struct amdgpu_xcp_mgr; 322 struct amdgpu_device; 323 struct amdgpu_irq_src; 324 struct amdgpu_fpriv; 325 struct amdgpu_bo_va_mapping; 326 struct kfd_vm_fault_info; 327 struct amdgpu_hive_info; 328 struct amdgpu_reset_context; 329 struct amdgpu_reset_control; 330 struct amdgpu_coredump_info; 331 struct amdgpu_video_codecs; 332 333 enum amdgpu_cp_irq { 334 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 335 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 344 345 AMDGPU_CP_IRQ_LAST 346 }; 347 348 enum amdgpu_thermal_irq { 349 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 350 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 351 352 AMDGPU_THERMAL_IRQ_LAST 353 }; 354 355 enum amdgpu_kiq_irq { 356 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 357 AMDGPU_CP_KIQ_IRQ_LAST 358 }; 359 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 360 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 361 #define MAX_KIQ_REG_TRY 1000 362 363 /* 364 * BIOS. 365 */ 366 bool amdgpu_get_bios(struct amdgpu_device *adev); 367 bool amdgpu_read_bios(struct amdgpu_device *adev); 368 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 369 u8 *bios, u32 length_bytes); 370 void amdgpu_bios_release(struct amdgpu_device *adev); 371 /* 372 * Clocks 373 */ 374 375 #define AMDGPU_MAX_PPLL 3 376 377 struct amdgpu_clock { 378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 379 struct amdgpu_pll spll; 380 struct amdgpu_pll mpll; 381 /* 10 Khz units */ 382 uint32_t default_mclk; 383 uint32_t default_sclk; 384 uint32_t default_dispclk; 385 uint32_t dp_extclk; 386 uint32_t max_pixel_clock; 387 }; 388 389 /* 390 * IRQS. 391 */ 392 393 struct amdgpu_flip_work { 394 struct delayed_work flip_work; 395 struct work_struct unpin_work; 396 struct amdgpu_device *adev; 397 int crtc_id; 398 u32 target_vblank; 399 uint64_t base; 400 struct drm_pending_vblank_event *event; 401 struct amdgpu_bo *old_abo; 402 unsigned shared_count; 403 struct dma_fence **shared; 404 struct dma_fence_cb cb; 405 bool async; 406 }; 407 408 /* 409 * file private structure 410 */ 411 412 struct amdgpu_fpriv { 413 struct amdgpu_vm vm; 414 struct amdgpu_bo_va *prt_va; 415 struct amdgpu_bo_va *csa_va; 416 struct amdgpu_bo_va *seq64_va; 417 struct xarray bo_list_handles; 418 struct amdgpu_ctx_mgr ctx_mgr; 419 struct amdgpu_userq_mgr userq_mgr; 420 421 /* Eviction fence infra */ 422 struct amdgpu_eviction_fence_mgr evf_mgr; 423 424 /** GPU partition selection */ 425 uint32_t xcp_id; 426 }; 427 428 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 429 430 /* 431 * Benchmarking 432 */ 433 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 434 435 /* 436 * ASIC specific functions. 437 */ 438 struct amdgpu_asic_funcs { 439 bool (*read_disabled_bios)(struct amdgpu_device *adev); 440 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 441 u8 *bios, u32 length_bytes); 442 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 443 u32 sh_num, u32 reg_offset, u32 *value); 444 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 445 int (*reset)(struct amdgpu_device *adev); 446 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 447 /* get the reference clock */ 448 u32 (*get_xclk)(struct amdgpu_device *adev); 449 /* MM block clocks */ 450 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 451 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 452 /* static power management */ 453 int (*get_pcie_lanes)(struct amdgpu_device *adev); 454 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 455 /* get config memsize register */ 456 u32 (*get_config_memsize)(struct amdgpu_device *adev); 457 /* flush hdp write queue */ 458 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 459 /* invalidate hdp read cache */ 460 void (*invalidate_hdp)(struct amdgpu_device *adev, 461 struct amdgpu_ring *ring); 462 /* initialize doorbell layout for specific asic*/ 463 void (*init_doorbell_index)(struct amdgpu_device *adev); 464 /* PCIe bandwidth usage */ 465 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 466 uint64_t *count1); 467 /* do we need to reset the asic at init time (e.g., kexec) */ 468 bool (*need_reset_on_init)(struct amdgpu_device *adev); 469 /* PCIe replay counter */ 470 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 471 /* device supports BACO */ 472 int (*supports_baco)(struct amdgpu_device *adev); 473 /* pre asic_init quirks */ 474 void (*pre_asic_init)(struct amdgpu_device *adev); 475 /* enter/exit umd stable pstate */ 476 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 477 /* query video codecs */ 478 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 479 const struct amdgpu_video_codecs **codecs); 480 /* encode "> 32bits" smn addressing */ 481 u64 (*encode_ext_smn_addressing)(int ext_id); 482 483 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 484 enum amdgpu_reg_state reg_state, void *buf, 485 size_t max_size); 486 }; 487 488 /* 489 * IOCTL. 490 */ 491 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 492 struct drm_file *filp); 493 494 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 495 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 496 struct drm_file *filp); 497 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 498 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 499 struct drm_file *filp); 500 501 /* VRAM scratch page for HDP bug, default vram page */ 502 struct amdgpu_mem_scratch { 503 struct amdgpu_bo *robj; 504 uint32_t *ptr; 505 u64 gpu_addr; 506 }; 507 508 /* 509 * CGS 510 */ 511 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 512 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 513 514 /* 515 * Core structure, functions and helpers. 516 */ 517 struct amdgpu_mmio_remap { 518 u32 reg_offset; 519 resource_size_t bus_addr; 520 struct amdgpu_bo *bo; 521 }; 522 523 enum amdgpu_uid_type { 524 AMDGPU_UID_TYPE_XCD, 525 AMDGPU_UID_TYPE_AID, 526 AMDGPU_UID_TYPE_SOC, 527 AMDGPU_UID_TYPE_MID, 528 AMDGPU_UID_TYPE_MAX 529 }; 530 531 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 532 533 struct amdgpu_uid { 534 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 535 struct amdgpu_device *adev; 536 }; 537 538 struct amd_powerplay { 539 void *pp_handle; 540 const struct amd_pm_funcs *pp_funcs; 541 }; 542 543 /* polaris10 kickers */ 544 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 545 ((rid == 0xE3) || \ 546 (rid == 0xE4) || \ 547 (rid == 0xE5) || \ 548 (rid == 0xE7) || \ 549 (rid == 0xEF))) || \ 550 ((did == 0x6FDF) && \ 551 ((rid == 0xE7) || \ 552 (rid == 0xEF) || \ 553 (rid == 0xFF)))) 554 555 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 556 ((rid == 0xE1) || \ 557 (rid == 0xF7))) 558 559 /* polaris11 kickers */ 560 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 561 ((rid == 0xE0) || \ 562 (rid == 0xE5))) || \ 563 ((did == 0x67FF) && \ 564 ((rid == 0xCF) || \ 565 (rid == 0xEF) || \ 566 (rid == 0xFF)))) 567 568 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 569 ((rid == 0xE2))) 570 571 /* polaris12 kickers */ 572 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 573 ((rid == 0xC0) || \ 574 (rid == 0xC1) || \ 575 (rid == 0xC3) || \ 576 (rid == 0xC7))) || \ 577 ((did == 0x6981) && \ 578 ((rid == 0x00) || \ 579 (rid == 0x01) || \ 580 (rid == 0x10)))) 581 582 struct amdgpu_pcie_reset_ctx { 583 bool in_link_reset; 584 bool occurs_dpc; 585 bool audio_suspended; 586 struct pci_dev *swus; 587 struct pci_saved_state *swus_pcistate; 588 struct pci_saved_state *swds_pcistate; 589 }; 590 591 /* 592 * Custom Init levels could be defined for different situations where a full 593 * initialization of all hardware blocks are not expected. Sample cases are 594 * custom init sequences after resume after S0i3/S3, reset on initialization, 595 * partial reset of blocks etc. Presently, this defines only two levels. Levels 596 * are described in corresponding struct definitions - amdgpu_init_default, 597 * amdgpu_init_minimal_xgmi. 598 */ 599 enum amdgpu_init_lvl_id { 600 AMDGPU_INIT_LEVEL_DEFAULT, 601 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 602 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 603 }; 604 605 struct amdgpu_init_level { 606 enum amdgpu_init_lvl_id level; 607 uint32_t hwini_ip_block_mask; 608 }; 609 610 #define AMDGPU_RESET_MAGIC_NUM 64 611 #define AMDGPU_MAX_DF_PERFMONS 4 612 struct amdgpu_reset_domain; 613 struct amdgpu_fru_info; 614 615 enum amdgpu_enforce_isolation_mode { 616 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 617 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 618 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 619 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 620 }; 621 622 struct amdgpu_device { 623 struct device *dev; 624 struct pci_dev *pdev; 625 /* The two ends of the physical PCIe link outside the device. */ 626 struct pci_dev *link_dev; 627 struct pci_dev *link_partner; 628 struct drm_device ddev; 629 630 #ifdef CONFIG_DRM_AMD_ACP 631 struct amdgpu_acp acp; 632 #endif 633 struct amdgpu_hive_info *hive; 634 struct amdgpu_xcp_mgr *xcp_mgr; 635 /* ASIC */ 636 enum amd_asic_type asic_type; 637 uint32_t family; 638 uint32_t rev_id; 639 uint32_t external_rev_id; 640 unsigned long flags; 641 unsigned long apu_flags; 642 int usec_timeout; 643 const struct amdgpu_asic_funcs *asic_funcs; 644 bool shutdown; 645 bool need_swiotlb; 646 bool accel_working; 647 struct notifier_block acpi_nb; 648 struct notifier_block pm_nb; 649 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 650 struct debugfs_blob_wrapper debugfs_vbios_blob; 651 struct mutex srbm_mutex; 652 /* GRBM index mutex. Protects concurrent access to GRBM index */ 653 struct mutex grbm_idx_mutex; 654 struct dev_pm_domain vga_pm_domain; 655 bool have_disp_power_ref; 656 bool have_atomics_support; 657 bool is_sw_smu; 658 659 /* BIOS */ 660 bool is_atom_fw; 661 uint8_t *bios; 662 uint32_t bios_size; 663 uint32_t bios_scratch_reg_offset; 664 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 665 666 /* Register/doorbell mmio */ 667 resource_size_t rmmio_base; 668 resource_size_t rmmio_size; 669 void __iomem *rmmio; 670 /* protects concurrent MM_INDEX/DATA based register access */ 671 spinlock_t mmio_idx_lock; 672 struct amdgpu_mmio_remap rmmio_remap; 673 /* Indirect register access blocks */ 674 struct amdgpu_reg_access reg; 675 struct amdgpu_doorbell doorbell; 676 677 /* clock/pll info */ 678 struct amdgpu_clock clock; 679 680 /* MC */ 681 struct amdgpu_gmc gmc; 682 struct amdgpu_gart gart; 683 dma_addr_t dummy_page_addr; 684 struct amdgpu_vm_manager vm_manager; 685 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 686 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 687 688 /* memory management */ 689 struct amdgpu_mman mman; 690 struct amdgpu_mem_scratch mem_scratch; 691 struct amdgpu_wb wb; 692 atomic64_t num_bytes_moved; 693 atomic64_t num_evictions; 694 atomic64_t num_vram_cpu_page_faults; 695 atomic_t gpu_reset_counter; 696 atomic_t vram_lost_counter; 697 698 /* data for buffer migration throttling */ 699 struct { 700 spinlock_t lock; 701 s64 last_update_us; 702 s64 accum_us; /* accumulated microseconds */ 703 s64 accum_us_vis; /* for visible VRAM */ 704 u32 log2_max_MBps; 705 } mm_stats; 706 707 /* discovery*/ 708 struct amdgpu_discovery_info discovery; 709 710 /* display */ 711 bool enable_virtual_display; 712 struct amdgpu_vkms_output *amdgpu_vkms_output; 713 struct amdgpu_mode_info mode_info; 714 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 715 struct delayed_work hotplug_work; 716 struct amdgpu_irq_src crtc_irq; 717 struct amdgpu_irq_src vline0_irq; 718 struct amdgpu_irq_src vupdate_irq; 719 struct amdgpu_irq_src pageflip_irq; 720 struct amdgpu_irq_src hpd_irq; 721 struct amdgpu_irq_src dmub_trace_irq; 722 struct amdgpu_irq_src dmub_outbox_irq; 723 724 /* rings */ 725 u64 fence_context; 726 unsigned num_rings; 727 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 728 struct dma_fence __rcu *gang_submit; 729 bool ib_pool_ready; 730 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 731 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 732 733 /* interrupts */ 734 struct amdgpu_irq irq; 735 736 /* powerplay */ 737 struct amd_powerplay powerplay; 738 struct amdgpu_pm pm; 739 u64 cg_flags; 740 u32 pg_flags; 741 742 /* nbio */ 743 struct amdgpu_nbio nbio; 744 745 /* hdp */ 746 struct amdgpu_hdp hdp; 747 748 /* smuio */ 749 struct amdgpu_smuio smuio; 750 751 /* mmhub */ 752 struct amdgpu_mmhub mmhub; 753 754 /* gfxhub */ 755 struct amdgpu_gfxhub gfxhub; 756 757 /* gfx */ 758 struct amdgpu_gfx gfx; 759 760 /* sdma */ 761 struct amdgpu_sdma sdma; 762 763 /* lsdma */ 764 struct amdgpu_lsdma lsdma; 765 766 /* uvd */ 767 struct amdgpu_uvd uvd; 768 769 /* vce */ 770 struct amdgpu_vce vce; 771 772 /* vcn */ 773 struct amdgpu_vcn vcn; 774 775 /* jpeg */ 776 struct amdgpu_jpeg jpeg; 777 778 /* vpe */ 779 struct amdgpu_vpe vpe; 780 781 /* umsch */ 782 struct amdgpu_umsch_mm umsch_mm; 783 bool enable_umsch_mm; 784 785 /* firmwares */ 786 struct amdgpu_firmware firmware; 787 788 /* PSP */ 789 struct psp_context psp; 790 791 /* GDS */ 792 struct amdgpu_gds gds; 793 794 /* for userq and VM fences */ 795 struct amdgpu_seq64 seq64; 796 797 /* UMC */ 798 struct amdgpu_umc umc; 799 800 /* display related functionality */ 801 struct amdgpu_display_manager dm; 802 803 #if defined(CONFIG_DRM_AMD_ISP) 804 /* isp */ 805 struct amdgpu_isp isp; 806 #endif 807 808 /* mes */ 809 bool enable_mes; 810 bool enable_mes_kiq; 811 bool enable_uni_mes; 812 struct amdgpu_mes mes; 813 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 814 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 815 816 /** 817 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 818 * Key: doorbell_index (unique global identifier for the queue) 819 * Value: struct amdgpu_usermode_queue 820 */ 821 struct xarray userq_doorbell_xa; 822 823 /* df */ 824 struct amdgpu_df df; 825 826 /* MCA */ 827 struct amdgpu_mca mca; 828 829 /* CPER */ 830 struct amdgpu_cper cper; 831 832 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 833 uint32_t harvest_ip_mask; 834 int num_ip_blocks; 835 struct mutex mn_lock; 836 DECLARE_HASHTABLE(mn_hash, 7); 837 838 /* tracking pinned memory */ 839 atomic64_t vram_pin_size; 840 atomic64_t visible_pin_size; 841 atomic64_t gart_pin_size; 842 843 /* soc15 register offset based on ip, instance and segment */ 844 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 845 struct amdgpu_ip_map_info ip_map; 846 847 /* delayed work_func for deferring clockgating during resume */ 848 struct delayed_work delayed_init_work; 849 850 struct amdgpu_virt virt; 851 852 /* record hw reset is performed */ 853 bool has_hw_reset; 854 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 855 856 /* s3/s4 mask */ 857 bool in_suspend; 858 bool in_s3; 859 bool in_s4; 860 bool in_s0ix; 861 suspend_state_t last_suspend_state; 862 863 enum pp_mp1_state mp1_state; 864 struct amdgpu_doorbell_index doorbell_index; 865 866 struct mutex notifier_lock; 867 868 int asic_reset_res; 869 struct work_struct xgmi_reset_work; 870 struct list_head reset_list; 871 872 long gfx_timeout; 873 long sdma_timeout; 874 long video_timeout; 875 long compute_timeout; 876 long psp_timeout; 877 878 uint64_t unique_id; 879 uint8_t unitid; 880 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 881 882 /* enable runtime pm on the device */ 883 bool in_runpm; 884 bool has_pr3; 885 886 bool ucode_sysfs_en; 887 888 struct amdgpu_fru_info *fru_info; 889 atomic_t throttling_logging_enabled; 890 struct ratelimit_state throttling_logging_rs; 891 uint32_t ras_hw_enabled; 892 uint32_t ras_enabled; 893 bool ras_default_ecc_enabled; 894 895 bool no_hw_access; 896 struct pci_saved_state *pci_state; 897 pci_channel_state_t pci_channel_state; 898 899 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 900 901 /* Track auto wait count on s_barrier settings */ 902 bool barrier_has_auto_waitcnt; 903 904 struct amdgpu_reset_control *reset_cntl; 905 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 906 907 bool ram_is_direct_mapped; 908 909 struct list_head ras_list; 910 911 struct amdgpu_reset_domain *reset_domain; 912 913 #ifdef CONFIG_DEV_COREDUMP 914 struct amdgpu_coredump_info *coredump; 915 struct work_struct coredump_work; 916 #endif 917 918 struct mutex benchmark_mutex; 919 920 bool scpm_enabled; 921 uint32_t scpm_status; 922 923 struct work_struct reset_work; 924 925 bool dc_enabled; 926 /* Mask of active clusters */ 927 uint32_t aid_mask; 928 929 /* Debug */ 930 bool debug_vm; 931 bool debug_largebar; 932 bool debug_disable_soft_recovery; 933 bool debug_use_vram_fw_buf; 934 bool debug_exp_resets; 935 bool debug_disable_gpu_ring_reset; 936 bool debug_vm_userptr; 937 bool debug_disable_ce_logs; 938 bool debug_enable_ce_cs; 939 bool debug_hibernation_thaw_resume_gpu; 940 bool debug_disable_ip_block_soft_reset; 941 942 /* Protection for the following isolation structure */ 943 struct mutex enforce_isolation_mutex; 944 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 945 struct amdgpu_isolation { 946 void *owner; 947 struct dma_fence *spearhead; 948 struct amdgpu_sync active; 949 struct amdgpu_sync prev; 950 } isolation[MAX_XCP]; 951 952 struct amdgpu_init_level *init_lvl; 953 954 /* This flag is used to determine how VRAM allocations are handled for APUs 955 * in KFD: VRAM or GTT. 956 */ 957 bool apu_prefer_gtt; 958 959 bool userq_halt_for_enforce_isolation; 960 struct amdgpu_uid *uid_info; 961 962 struct amdgpu_uma_carveout_info uma_info; 963 964 /* KFD 965 * Must be last --ends in a flexible-array member. 966 */ 967 struct amdgpu_kfd_dev kfd; 968 }; 969 970 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 971 uint8_t ip, uint8_t inst) 972 { 973 /* This considers only major/minor/rev and ignores 974 * subrevision/variant fields. 975 */ 976 return adev->ip_versions[ip][inst] & ~0xFFU; 977 } 978 979 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 980 uint8_t ip, uint8_t inst) 981 { 982 /* This returns full version - major/minor/rev/variant/subrevision */ 983 return adev->ip_versions[ip][inst]; 984 } 985 986 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 987 { 988 return container_of(ddev, struct amdgpu_device, ddev); 989 } 990 991 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 992 { 993 return &adev->ddev; 994 } 995 996 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 997 { 998 return container_of(bdev, struct amdgpu_device, mman.bdev); 999 } 1000 1001 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1002 { 1003 return !!adev->aid_mask; 1004 } 1005 1006 int amdgpu_device_init(struct amdgpu_device *adev, 1007 uint32_t flags); 1008 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1009 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1010 1011 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1012 1013 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1014 void *buf, size_t size, bool write); 1015 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1016 void *buf, size_t size, bool write); 1017 1018 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1019 void *buf, size_t size, bool write); 1020 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1021 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1022 enum amd_asic_type asic_type); 1023 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1024 1025 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1026 1027 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1028 struct amdgpu_reset_context *reset_context); 1029 1030 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1031 struct amdgpu_reset_context *reset_context); 1032 1033 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1034 1035 int emu_soc_asic_init(struct amdgpu_device *adev); 1036 1037 /* 1038 * Registers read & write functions. 1039 */ 1040 #define AMDGPU_REGS_NO_KIQ (1<<1) 1041 #define AMDGPU_REGS_RLC (1<<2) 1042 1043 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1044 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1045 1046 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1047 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1048 1049 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1050 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1051 1052 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1053 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1054 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1055 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1056 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1057 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1058 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1059 #define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) 1060 #define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) 1061 #define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) 1062 #define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) 1063 #define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) 1064 #define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) 1065 #define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) 1066 #define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) 1067 #define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) 1068 #define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) 1069 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1070 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1071 #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1072 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1073 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1074 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1075 #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1076 #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1077 #define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) 1078 #define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) 1079 #define RREG32_AUDIO_ENDPT(block, reg) \ 1080 amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) 1081 #define WREG32_AUDIO_ENDPT(block, reg, v) \ 1082 amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) 1083 #define WREG32_P(reg, val, mask) \ 1084 do { \ 1085 uint32_t tmp_ = RREG32(reg); \ 1086 tmp_ &= (mask); \ 1087 tmp_ |= ((val) & ~(mask)); \ 1088 WREG32(reg, tmp_); \ 1089 } while (0) 1090 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1091 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1092 #define WREG32_PLL_P(reg, val, mask) \ 1093 do { \ 1094 uint32_t tmp_ = RREG32_PLL(reg); \ 1095 tmp_ &= (mask); \ 1096 tmp_ |= ((val) & ~(mask)); \ 1097 WREG32_PLL(reg, tmp_); \ 1098 } while (0) 1099 1100 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1101 do { \ 1102 u32 tmp = RREG32_SMC(_Reg); \ 1103 tmp &= (_Mask); \ 1104 tmp |= ((_Val) & ~(_Mask)); \ 1105 WREG32_SMC(_Reg, tmp); \ 1106 } while (0) 1107 1108 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1109 1110 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1111 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1112 1113 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1114 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1115 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1116 1117 #define REG_GET_FIELD(value, reg, field) \ 1118 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1119 1120 #define WREG32_FIELD(reg, field, val) \ 1121 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1122 1123 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1124 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1125 1126 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1127 /* 1128 * BIOS helpers. 1129 */ 1130 #define RBIOS8(i) (adev->bios[i]) 1131 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1132 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1133 1134 #include "amdgpu_reset.h" 1135 1136 /* 1137 * ASICs macro. 1138 */ 1139 #define amdgpu_asic_set_vga_state(adev, state) \ 1140 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1141 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1142 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1143 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1144 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1145 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1146 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1147 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1148 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1149 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1150 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1151 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1152 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1153 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1154 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1155 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1156 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1157 #define amdgpu_asic_supports_baco(adev) \ 1158 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1159 #define amdgpu_asic_pre_asic_init(adev) \ 1160 { \ 1161 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1162 (adev)->asic_funcs->pre_asic_init((adev)); \ 1163 } 1164 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1165 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1166 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1167 1168 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1169 1170 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1171 #define for_each_inst(i, inst_mask) \ 1172 for (i = ffs(inst_mask); i-- != 0; \ 1173 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1174 1175 /* Common functions */ 1176 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1177 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1178 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1179 struct amdgpu_job *job, 1180 struct amdgpu_reset_context *reset_context); 1181 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1182 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1183 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1184 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1185 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1186 1187 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1188 u64 num_vis_bytes); 1189 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1190 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1191 const u32 *registers, 1192 const u32 array_size); 1193 1194 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1195 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1196 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1197 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1198 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1199 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1200 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1201 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1202 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1203 struct amdgpu_device *peer_adev); 1204 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1205 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1206 1207 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1208 struct amdgpu_ring *ring); 1209 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1210 struct amdgpu_ring *ring); 1211 1212 void amdgpu_device_halt(struct amdgpu_device *adev); 1213 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1214 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1215 struct dma_fence *gang); 1216 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1217 struct amdgpu_ring *ring, 1218 struct amdgpu_job *job); 1219 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1220 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1221 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1222 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1223 const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1224 void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev, 1225 const struct amdgpu_buffer_funcs *buffer_funcs); 1226 1227 /* atpx handler */ 1228 #if defined(CONFIG_VGA_SWITCHEROO) 1229 void amdgpu_register_atpx_handler(void); 1230 void amdgpu_unregister_atpx_handler(void); 1231 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1232 bool amdgpu_is_atpx_hybrid(void); 1233 bool amdgpu_has_atpx(void); 1234 #else 1235 static inline void amdgpu_register_atpx_handler(void) {} 1236 static inline void amdgpu_unregister_atpx_handler(void) {} 1237 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1238 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1239 static inline bool amdgpu_has_atpx(void) { return false; } 1240 #endif 1241 1242 /* 1243 * KMS 1244 */ 1245 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1246 extern const int amdgpu_max_kms_ioctl; 1247 1248 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1249 void amdgpu_driver_unload_kms(struct drm_device *dev); 1250 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1251 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1252 struct drm_file *file_priv); 1253 void amdgpu_driver_release_kms(struct drm_device *dev); 1254 1255 int amdgpu_device_prepare(struct drm_device *dev); 1256 void amdgpu_device_complete(struct drm_device *dev); 1257 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1258 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1259 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1260 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1261 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1262 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1263 struct drm_file *filp); 1264 int amdgpu_proc_options_ioctl(struct drm_device *dev, void *data, 1265 struct drm_file *filp); 1266 1267 /* 1268 * functions used by amdgpu_encoder.c 1269 */ 1270 struct amdgpu_afmt_acr { 1271 u32 clock; 1272 1273 int n_32khz; 1274 int cts_32khz; 1275 1276 int n_44_1khz; 1277 int cts_44_1khz; 1278 1279 int n_48khz; 1280 int cts_48khz; 1281 1282 }; 1283 1284 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1285 1286 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1287 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1288 1289 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1290 pci_channel_state_t state); 1291 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1292 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1293 void amdgpu_pci_resume(struct pci_dev *pdev); 1294 1295 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1296 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1297 1298 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1299 1300 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1301 enum amd_clockgating_state state); 1302 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1303 enum amd_powergating_state state); 1304 1305 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1306 { 1307 return amdgpu_gpu_recovery != 0 && 1308 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1309 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1310 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1311 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1312 } 1313 1314 #include "amdgpu_object.h" 1315 1316 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1317 { 1318 return adev->gmc.tmz_enabled; 1319 } 1320 1321 int amdgpu_in_reset(struct amdgpu_device *adev); 1322 1323 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1324 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1325 extern const struct attribute_group amdgpu_flash_attr_group; 1326 1327 void amdgpu_set_init_level(struct amdgpu_device *adev, 1328 enum amdgpu_init_lvl_id lvl); 1329 1330 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1331 { 1332 u32 status; 1333 int r; 1334 1335 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1336 if (r || PCI_POSSIBLE_ERROR(status)) { 1337 dev_err(adev->dev, "device lost from bus!"); 1338 return -ENODEV; 1339 } 1340 1341 return 0; 1342 } 1343 1344 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1345 enum amdgpu_uid_type type, uint8_t inst, 1346 uint64_t uid); 1347 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1348 enum amdgpu_uid_type type, uint8_t inst); 1349 #endif 1350