| /freebsd/contrib/llvm-project/clang/lib/Rewrite/ |
| H A D | HTMLRewrite.cpp | 60 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E, in HighlightRange()
144 RewriteBuffer &RB = R.getEditBuffer(FID); in EscapeText() local
237 static void AddLineNumber(RewriteBuffer &RB, unsigned LineNo, in AddLineNumber()
261 RewriteBuffer &RB = R.getEditBuffer(FID); in AddLineNumbers() local
479 RewriteBuffer &RB = R.getEditBuffer(FID); in SyntaxHighlightImpl() local
565 RewriteBuffer &RB = R.getEditBuffer(FID); in SyntaxHighlight() local
584 const char *StartTag, const char *EndTag) { in SyntaxHighlight()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/scudo/standalone/ |
| H A D | combined.h | 188 AllocationRingBuffer *RB = getRingBuffer(); in enableRingBuffer() local
196 AllocationRingBuffer *RB = getRingBuffer(); in disableRingBuffer() local
843 AllocationRingBuffer *RB = getRingBuffer(); in getStackDepotAddress() local
849 AllocationRingBuffer *RB = getRingBuffer(); in getStackDepotSize() local
868 AllocationRingBuffer *RB = getRingBuffer(); in getRingBufferSize() local
1391 AllocationRingBuffer *RB = getRingBuffer(); in storePrimaryAllocationStackMaybe() local
1399 void storeRingBufferEntry(AllocationRingBuffer *RB, void *Ptr, in storeRingBufferEntry()
1428 AllocationRingBuffer *RB = getRingBuffer(); in storeSecondaryAllocationStackMaybe() local
1445 AllocationRingBuffer *RB = getRingBuffer(); in storeDeallocationStackMaybe() local
1632 getRingBufferEntry(AllocationRingBuffer *RB, uptr N) { in getRingBufferEntry()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 156 Register RB = MI.getOperand(3).getReg(); in expandAtomicRMW128() local
232 Register RB = MI.getOperand(3).getReg(); in expandAtomicCmpSwap128() local
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| /freebsd/contrib/llvm-project/clang/lib/Frontend/Rewrite/ |
| H A D | RewriteMacros.cpp | 94 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local
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| /freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/ |
| H A D | sanitizer_ring_buffer.h | 27 RingBuffer *RB = reinterpret_cast<RingBuffer*>(Ptr); in New() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 273 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
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| H A D | PPCInstructionSelector.cpp | 103 static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) { in getRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 104 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \ in AArch64RegisterBankInfo() argument
536 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
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| H A D | AArch64InstructionSelector.cpp | 571 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
607 getMinClassForRegBank(const RegisterBank &RB, TypeSize SizeInBits, in getMinClassForRegBank()
677 static unsigned getMinSizeForRegBank(const RegisterBank &RB) { in getMinSizeForRegBank()
992 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in selectDebugInstr() local
2477 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local
2610 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() local
2935 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select() local
3099 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select() local
3791 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI); in selectMergeValues() local
4212 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) { in getInsertVecEltOpInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 94 if (auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank)) in getRegBank() local
142 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 606 virtual bool isDivergentRegBank(const RegisterBank *RB) const { in isDivergentRegBank()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 262 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank); in selectDebugInstr() local
450 const RegisterBank &RB, in getLoadStoreOp()
570 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
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| H A D | X86RegisterBankInfo.cpp | 114 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEInfo.cpp | 399 if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB)) addNodeIDReg() local
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| H A D | RegBankSelect.cpp | 644 const RegisterBank *RB = in assignInstr() local
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| /freebsd/contrib/llvm-project/clang/lib/Frontend/ |
| H A D | ASTUnit.cpp | 189 for (const auto &RB : PreprocessorOpts.RemappedFileBuffers) { in getBufferForFileHandlingRemapping() local
264 for (const auto &RB : PPOpts.RemappedFileBuffers) in ~ASTUnit() local
1882 for (const auto &RB : PPOpts.RemappedFileBuffers) in Reparse() local
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| H A D | PrecompiledPreamble.cpp | 650 for (const auto &RB : PreprocessorOpts.RemappedFileBuffers) { in CanReuse() local
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| /freebsd/sys/contrib/openzfs/module/lua/ |
| H A D | lvm.c | 552 #define RB(i) check_exp(getBMode(GET_OPCODE(i)) == OpArgR, base+GETARG_B(i)) macro
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DAGISelMatcherGen.cpp | 724 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand() local
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| /freebsd/contrib/llvm-project/clang/lib/AST/ |
| H A D | Stmt.cpp | 367 SourceLocation LB, SourceLocation RB) in CompoundStmt()
385 SourceLocation LB, SourceLocation RB) { in Create()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 473 const MachineOperand &RB = MI.getOperand(3); in computePhiCost() local
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| H A D | HexagonVLIWPacketizer.cpp | 254 MachineBasicBlock::iterator RB = Begin; in runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 534 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 2977 auto *RB = RBI.getRegBank(Reg, MRI, *MRI.getTargetRegisterInfo()); in isUniformReg() local
3117 if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>()) in getConstrainedRegClassForOperand() local
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