xref: /linux/drivers/net/wireless/ti/wl1251/reg.h (revision cbecf716ca618fd44feda6bd9a64a8179d031fc5)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * This file is part of wl12xx
4  *
5  * Copyright (c) 1998-2007 Texas Instruments Incorporated
6  * Copyright (C) 2008 Nokia Corporation
7  */
8 
9 #ifndef __REG_H__
10 #define __REG_H__
11 
12 #include <linux/bitops.h>
13 
14 #define REGISTERS_BASE 0x00300000
15 #define DRPW_BASE      0x00310000
16 
17 #define REGISTERS_DOWN_SIZE 0x00008800
18 #define REGISTERS_WORK_SIZE 0x0000b000
19 
20 #define HW_ACCESS_ELP_CTRL_REG_ADDR         0x1FFFC
21 
22 /* ELP register commands */
23 #define ELPCTRL_WAKE_UP             0x1
24 #define ELPCTRL_WAKE_UP_WLAN_READY  0x5
25 #define ELPCTRL_SLEEP               0x0
26 /* ELP WLAN_READY bit */
27 #define ELPCTRL_WLAN_READY          0x2
28 
29 /* Device Configuration registers*/
30 #define SOR_CFG                        (REGISTERS_BASE + 0x0800)
31 #define ECPU_CTRL                      (REGISTERS_BASE + 0x0804)
32 #define HI_CFG                         (REGISTERS_BASE + 0x0808)
33 
34 /* EEPROM registers */
35 #define EE_START                       (REGISTERS_BASE + 0x080C)
36 #define EE_CTL                         (REGISTERS_BASE + 0x2000)
37 #define EE_DATA                        (REGISTERS_BASE + 0x2004)
38 #define EE_ADDR                        (REGISTERS_BASE + 0x2008)
39 
40 #define EE_CTL_READ                   2
41 
42 #define CHIP_ID_B                      (REGISTERS_BASE + 0x5674)
43 
44 #define CHIP_ID_1251_PG10	           (0x7010101)
45 #define CHIP_ID_1251_PG11	           (0x7020101)
46 #define CHIP_ID_1251_PG12	           (0x7030101)
47 
48 #define ENABLE                         (REGISTERS_BASE + 0x5450)
49 
50 /* Power Management registers */
51 #define ELP_CFG_MODE                   (REGISTERS_BASE + 0x5804)
52 #define ELP_CMD                        (REGISTERS_BASE + 0x5808)
53 #define PLL_CAL_TIME                   (REGISTERS_BASE + 0x5810)
54 #define CLK_REQ_TIME                   (REGISTERS_BASE + 0x5814)
55 #define CLK_BUF_TIME                   (REGISTERS_BASE + 0x5818)
56 
57 #define CFG_PLL_SYNC_CNT               (REGISTERS_BASE + 0x5820)
58 
59 /* Scratch Pad registers*/
60 #define SCR_PAD0                       (REGISTERS_BASE + 0x5608)
61 #define SCR_PAD1                       (REGISTERS_BASE + 0x560C)
62 #define SCR_PAD2                       (REGISTERS_BASE + 0x5610)
63 #define SCR_PAD3                       (REGISTERS_BASE + 0x5614)
64 #define SCR_PAD4                       (REGISTERS_BASE + 0x5618)
65 #define SCR_PAD4_SET                   (REGISTERS_BASE + 0x561C)
66 #define SCR_PAD4_CLR                   (REGISTERS_BASE + 0x5620)
67 #define SCR_PAD5                       (REGISTERS_BASE + 0x5624)
68 #define SCR_PAD5_SET                   (REGISTERS_BASE + 0x5628)
69 #define SCR_PAD5_CLR                   (REGISTERS_BASE + 0x562C)
70 #define SCR_PAD6                       (REGISTERS_BASE + 0x5630)
71 #define SCR_PAD7                       (REGISTERS_BASE + 0x5634)
72 #define SCR_PAD8                       (REGISTERS_BASE + 0x5638)
73 #define SCR_PAD9                       (REGISTERS_BASE + 0x563C)
74 
75 /* Spare registers*/
76 #define SPARE_A1                       (REGISTERS_BASE + 0x0994)
77 #define SPARE_A2                       (REGISTERS_BASE + 0x0998)
78 #define SPARE_A3                       (REGISTERS_BASE + 0x099C)
79 #define SPARE_A4                       (REGISTERS_BASE + 0x09A0)
80 #define SPARE_A5                       (REGISTERS_BASE + 0x09A4)
81 #define SPARE_A6                       (REGISTERS_BASE + 0x09A8)
82 #define SPARE_A7                       (REGISTERS_BASE + 0x09AC)
83 #define SPARE_A8                       (REGISTERS_BASE + 0x09B0)
84 #define SPARE_B1                       (REGISTERS_BASE + 0x5420)
85 #define SPARE_B2                       (REGISTERS_BASE + 0x5424)
86 #define SPARE_B3                       (REGISTERS_BASE + 0x5428)
87 #define SPARE_B4                       (REGISTERS_BASE + 0x542C)
88 #define SPARE_B5                       (REGISTERS_BASE + 0x5430)
89 #define SPARE_B6                       (REGISTERS_BASE + 0x5434)
90 #define SPARE_B7                       (REGISTERS_BASE + 0x5438)
91 #define SPARE_B8                       (REGISTERS_BASE + 0x543C)
92 
93 enum wl12xx_acx_int_reg {
94 	ACX_REG_INTERRUPT_TRIG,
95 	ACX_REG_INTERRUPT_TRIG_H,
96 
97 /*=============================================
98   Host Interrupt Mask Register - 32bit (RW)
99   ------------------------------------------
100   Setting a bit in this register masks the
101   corresponding interrupt to the host.
102   0 - RX0		- Rx first dubble buffer Data Interrupt
103   1 - TXD		- Tx Data Interrupt
104   2 - TXXFR		- Tx Transfer Interrupt
105   3 - RX1		- Rx second dubble buffer Data Interrupt
106   4 - RXXFR		- Rx Transfer Interrupt
107   5 - EVENT_A	- Event Mailbox interrupt
108   6 - EVENT_B	- Event Mailbox interrupt
109   7 - WNONHST	- Wake On Host Interrupt
110   8 - TRACE_A	- Debug Trace interrupt
111   9 - TRACE_B	- Debug Trace interrupt
112  10 - CDCMP		- Command Complete Interrupt
113  11 -
114  12 -
115  13 -
116  14 - ICOMP		- Initialization Complete Interrupt
117  16 - SG SE		- Soft Gemini - Sense enable interrupt
118  17 - SG SD		- Soft Gemini - Sense disable interrupt
119  18 -			-
120  19 -			-
121  20 -			-
122  21-			-
123  Default: 0x0001
124 *==============================================*/
125 	ACX_REG_INTERRUPT_MASK,
126 
127 /*=============================================
128   Host Interrupt Mask Set 16bit, (Write only)
129   ------------------------------------------
130  Setting a bit in this register sets
131  the corresponding bin in ACX_HINT_MASK register
132  without effecting the mask
133  state of other bits (0 = no effect).
134 ==============================================*/
135 	ACX_REG_HINT_MASK_SET,
136 
137 /*=============================================
138   Host Interrupt Mask Clear 16bit,(Write only)
139   ------------------------------------------
140  Setting a bit in this register clears
141  the corresponding bin in ACX_HINT_MASK register
142  without effecting the mask
143  state of other bits (0 = no effect).
144 =============================================*/
145 	ACX_REG_HINT_MASK_CLR,
146 
147 /*=============================================
148   Host Interrupt Status Nondestructive Read
149   16bit,(Read only)
150   ------------------------------------------
151  The host can read this register to determine
152  which interrupts are active.
153  Reading this register doesn't
154  effect its content.
155 =============================================*/
156 	ACX_REG_INTERRUPT_NO_CLEAR,
157 
158 /*=============================================
159   Host Interrupt Status Clear on Read  Register
160   16bit,(Read only)
161   ------------------------------------------
162  The host can read this register to determine
163  which interrupts are active.
164  Reading this register clears it,
165  thus making all interrupts inactive.
166 ==============================================*/
167 	ACX_REG_INTERRUPT_CLEAR,
168 
169 /*=============================================
170   Host Interrupt Acknowledge Register
171   16bit,(Write only)
172   ------------------------------------------
173  The host can set individual bits in this
174  register to clear (acknowledge) the corresp.
175  interrupt status bits in the HINT_STS_CLR and
176  HINT_STS_ND registers, thus making the
177  assotiated interrupt inactive. (0-no effect)
178 ==============================================*/
179 	ACX_REG_INTERRUPT_ACK,
180 
181 /*===============================================
182    Host Software Reset - 32bit RW
183  ------------------------------------------
184     [31:1] Reserved
185     0  SOFT_RESET Soft Reset  - When this bit is set,
186     it holds the Wlan hardware in a soft reset state.
187     This reset disables all MAC and baseband processor
188     clocks except the CardBus/PCI interface clock.
189     It also initializes all MAC state machines except
190     the host interface. It does not reload the
191     contents of the EEPROM. When this bit is cleared
192     (not self-clearing), the Wlan hardware
193     exits the software reset state.
194 ===============================================*/
195 	ACX_REG_SLV_SOFT_RESET,
196 
197 /*===============================================
198  EEPROM Burst Read Start  - 32bit RW
199  ------------------------------------------
200  [31:1] Reserved
201  0  ACX_EE_START -  EEPROM Burst Read Start 0
202  Setting this bit starts a burst read from
203  the external EEPROM.
204  If this bit is set (after reset) before an EEPROM read/write,
205  the burst read starts at EEPROM address 0.
206  Otherwise, it starts at the address
207  following the address of the previous access.
208  TheWlan hardware hardware clears this bit automatically.
209 
210  Default: 0x00000000
211 *================================================*/
212 	ACX_REG_EE_START,
213 
214 /* Embedded ARM CPU Control */
215 
216 /*===============================================
217  Halt eCPU   - 32bit RW
218  ------------------------------------------
219  0 HALT_ECPU Halt Embedded CPU - This bit is the
220  complement of bit 1 (MDATA2) in the SOR_CFG register.
221  During a hardware reset, this bit holds
222  the inverse of MDATA2.
223  When downloading firmware from the host,
224  set this bit (pull down MDATA2).
225  The host clears this bit after downloading the firmware into
226  zero-wait-state SSRAM.
227  When loading firmware from Flash, clear this bit (pull up MDATA2)
228  so that the eCPU can run the bootloader code in Flash
229  HALT_ECPU eCPU State
230  --------------------
231  1 halt eCPU
232  0 enable eCPU
233  ===============================================*/
234 	ACX_REG_ECPU_CONTROL,
235 
236 	ACX_REG_TABLE_LEN
237 };
238 
239 #define ACX_SLV_SOFT_RESET_BIT   BIT(0)
240 #define ACX_REG_EEPROM_START_BIT BIT(0)
241 
242 /* Command/Information Mailbox Pointers */
243 
244 /*===============================================
245   Command Mailbox Pointer - 32bit RW
246  ------------------------------------------
247  This register holds the start address of
248  the command mailbox located in the Wlan hardware memory.
249  The host must read this pointer after a reset to
250  find the location of the command mailbox.
251  The Wlan hardware initializes the command mailbox
252  pointer with the default address of the command mailbox.
253  The command mailbox pointer is not valid until after
254  the host receives the Init Complete interrupt from
255  the Wlan hardware.
256  ===============================================*/
257 #define REG_COMMAND_MAILBOX_PTR				(SCR_PAD0)
258 
259 /*===============================================
260   Information Mailbox Pointer - 32bit RW
261  ------------------------------------------
262  This register holds the start address of
263  the information mailbox located in the Wlan hardware memory.
264  The host must read this pointer after a reset to find
265  the location of the information mailbox.
266  The Wlan hardware initializes the information mailbox pointer
267  with the default address of the information mailbox.
268  The information mailbox pointer is not valid
269  until after the host receives the Init Complete interrupt from
270  the Wlan hardware.
271  ===============================================*/
272 #define REG_EVENT_MAILBOX_PTR				(SCR_PAD1)
273 
274 
275 /* Misc */
276 
277 #define REG_ENABLE_TX_RX				(ENABLE)
278 /*
279  * Rx configuration (filter) information element
280  * ---------------------------------------------
281  */
282 #define REG_RX_CONFIG				(RX_CFG)
283 #define REG_RX_FILTER				(RX_FILTER_CFG)
284 
285 
286 #define RX_CFG_ENABLE_PHY_HEADER_PLCP	 0x0002
287 
288 /* promiscuous - receives all valid frames */
289 #define RX_CFG_PROMISCUOUS		 0x0008
290 
291 /* receives frames from any BSSID */
292 #define RX_CFG_BSSID			 0x0020
293 
294 /* receives frames destined to any MAC address */
295 #define RX_CFG_MAC			 0x0010
296 
297 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC	 0x0010
298 #define RX_CFG_ENABLE_ANY_DEST_MAC	 0x0000
299 #define RX_CFG_ENABLE_ONLY_MY_BSSID	 0x0020
300 #define RX_CFG_ENABLE_ANY_BSSID		 0x0000
301 
302 /* discards all broadcast frames */
303 #define RX_CFG_DISABLE_BCAST		 0x0200
304 
305 #define RX_CFG_ENABLE_ONLY_MY_SSID	 0x0400
306 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
307 #define RX_CFG_COPY_RX_STATUS		 0x2000
308 #define RX_CFG_TSF			 0x10000
309 
310 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS	 (RX_CFG_ENABLE_ANY_DEST_MAC | \
311 					  RX_CFG_ENABLE_ONLY_MY_BSSID)
312 
313 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS	 (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
314 					  | RX_CFG_ENABLE_ANY_BSSID)
315 
316 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
317 					  RX_CFG_ENABLE_ANY_BSSID)
318 
319 #define RX_CONFIG_OPTION_MY_DST_MY_BSS	 (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
320 					  | RX_CFG_ENABLE_ONLY_MY_BSSID)
321 
322 #define RX_CONFIG_OPTION_FOR_SCAN  (RX_CFG_ENABLE_PHY_HEADER_PLCP \
323 				    | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
324 				    | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
325 
326 #define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
327 
328 #define RX_CONFIG_OPTION_FOR_JOIN	 (RX_CFG_ENABLE_ONLY_MY_BSSID | \
329 					  RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
330 
331 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN   (RX_CFG_ENABLE_ONLY_MY_SSID | \
332 					  RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
333 
334 #define RX_FILTER_OPTION_DEF	      (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
335 				       | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
336 				       | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
337 
338 #define RX_FILTER_OPTION_FILTER_ALL	 0
339 
340 #define RX_FILTER_OPTION_DEF_PRSP_BCN  (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
341 					| CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
342 
343 #define RX_FILTER_OPTION_JOIN	     (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
344 				      | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
345 				      | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
346 				      | CFG_RX_PRSP_EN)
347 
348 
349 /*===============================================
350  EEPROM Read/Write Request 32bit RW
351  ------------------------------------------
352  1 EE_READ - EEPROM Read Request 1 - Setting this bit
353  loads a single byte of data into the EE_DATA
354  register from the EEPROM location specified in
355  the EE_ADDR register.
356  The Wlan hardware hardware clears this bit automatically.
357  EE_DATA is valid when this bit is cleared.
358 
359  0 EE_WRITE  - EEPROM Write Request  - Setting this bit
360  writes a single byte of data from the EE_DATA register into the
361  EEPROM location specified in the EE_ADDR register.
362  The Wlan hardware hardware clears this bit automatically.
363 *===============================================*/
364 #define EE_CTL                              (REGISTERS_BASE + 0x2000)
365 #define ACX_EE_CTL_REG                      EE_CTL
366 #define EE_WRITE                            0x00000001ul
367 #define EE_READ                             0x00000002ul
368 
369 /*===============================================
370   EEPROM Address  - 32bit RW
371   ------------------------------------------
372   This register specifies the address
373   within the EEPROM from/to which to read/write data.
374   ===============================================*/
375 #define EE_ADDR                             (REGISTERS_BASE + 0x2008)
376 #define ACX_EE_ADDR_REG                     EE_ADDR
377 
378 /*===============================================
379   EEPROM Data  - 32bit RW
380   ------------------------------------------
381   This register either holds the read 8 bits of
382   data from the EEPROM or the write data
383   to be written to the EEPROM.
384   ===============================================*/
385 #define EE_DATA                             (REGISTERS_BASE + 0x2004)
386 #define ACX_EE_DATA_REG                     EE_DATA
387 
388 #define EEPROM_ACCESS_TO                    10000   /* timeout counter */
389 #define START_EEPROM_MGR                    0x00000001
390 
391 /*===============================================
392   EEPROM Base Address  - 32bit RW
393   ------------------------------------------
394   This register holds the upper nine bits
395   [23:15] of the 24-bit Wlan hardware memory
396   address for burst reads from EEPROM accesses.
397   The EEPROM provides the lower 15 bits of this address.
398   The MSB of the address from the EEPROM is ignored.
399   ===============================================*/
400 #define ACX_EE_CFG                          EE_CFG
401 
402 /*===============================================
403   GPIO Output Values  -32bit, RW
404   ------------------------------------------
405   [31:16]  Reserved
406   [15: 0]  Specify the output values (at the output driver inputs) for
407   GPIO[15:0], respectively.
408   ===============================================*/
409 #define ACX_GPIO_OUT_REG            GPIO_OUT
410 #define ACX_MAX_GPIO_LINES          15
411 
412 /*===============================================
413   Contention window  -32bit, RW
414   ------------------------------------------
415   [31:26]  Reserved
416   [25:16]  Max (0x3ff)
417   [15:07]  Reserved
418   [06:00]  Current contention window value - default is 0x1F
419   ===============================================*/
420 #define ACX_CONT_WIND_CFG_REG    CONT_WIND_CFG
421 #define ACX_CONT_WIND_MIN_MASK   0x0000007f
422 #define ACX_CONT_WIND_MAX        0x03ff0000
423 
424 /*===============================================
425   HI_CFG Interface Configuration Register Values
426   ------------------------------------------
427   ===============================================*/
428 #define HI_CFG_UART_ENABLE          0x00000004
429 #define HI_CFG_RST232_ENABLE        0x00000008
430 #define HI_CFG_CLOCK_REQ_SELECT     0x00000010
431 #define HI_CFG_HOST_INT_ENABLE      0x00000020
432 #define HI_CFG_VLYNQ_OUTPUT_ENABLE  0x00000040
433 #define HI_CFG_HOST_INT_ACTIVE_LOW  0x00000080
434 #define HI_CFG_UART_TX_OUT_GPIO_15  0x00000100
435 #define HI_CFG_UART_TX_OUT_GPIO_14  0x00000200
436 #define HI_CFG_UART_TX_OUT_GPIO_7   0x00000400
437 
438 /*
439  * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
440  *       for platforms using active high interrupt level
441  */
442 #ifdef USE_ACTIVE_HIGH
443 #define HI_CFG_DEF_VAL              \
444 	(HI_CFG_UART_ENABLE |        \
445 	HI_CFG_RST232_ENABLE |      \
446 	HI_CFG_CLOCK_REQ_SELECT |   \
447 	HI_CFG_HOST_INT_ENABLE)
448 #else
449 #define HI_CFG_DEF_VAL              \
450 	(HI_CFG_UART_ENABLE |        \
451 	HI_CFG_RST232_ENABLE |      \
452 	HI_CFG_CLOCK_REQ_SELECT |   \
453 	HI_CFG_HOST_INT_ENABLE)
454 
455 #endif
456 
457 #define REF_FREQ_19_2                       0
458 #define REF_FREQ_26_0                       1
459 #define REF_FREQ_38_4                       2
460 #define REF_FREQ_40_0                       3
461 #define REF_FREQ_33_6                       4
462 #define REF_FREQ_NUM                        5
463 
464 #define LUT_PARAM_INTEGER_DIVIDER           0
465 #define LUT_PARAM_FRACTIONAL_DIVIDER        1
466 #define LUT_PARAM_ATTN_BB                   2
467 #define LUT_PARAM_ALPHA_BB                  3
468 #define LUT_PARAM_STOP_TIME_BB              4
469 #define LUT_PARAM_BB_PLL_LOOP_FILTER        5
470 #define LUT_PARAM_NUM                       6
471 
472 #define ACX_EEPROMLESS_IND_REG              (SCR_PAD4)
473 #define USE_EEPROM                          0
474 #define SOFT_RESET_MAX_TIME                 1000000
475 #define SOFT_RESET_STALL_TIME               1000
476 #define NVS_DATA_BUNDARY_ALIGNMENT          4
477 
478 
479 /* Firmware image load chunk size */
480 #define CHUNK_SIZE          512
481 
482 /* Firmware image header size */
483 #define FW_HDR_SIZE 8
484 
485 #define ECPU_CONTROL_HALT					0x00000101
486 
487 
488 /******************************************************************************
489 
490     CHANNELS, BAND & REG DOMAINS definitions
491 
492 ******************************************************************************/
493 
494 
495 enum {
496 	RADIO_BAND_2_4GHZ = 0,  /* 2.4 Ghz band */
497 	RADIO_BAND_5GHZ = 1,    /* 5 Ghz band */
498 	RADIO_BAND_JAPAN_4_9_GHZ = 2,
499 	DEFAULT_BAND = RADIO_BAND_2_4GHZ,
500 	INVALID_BAND = 0xFE,
501 	MAX_RADIO_BANDS = 0xFF
502 };
503 
504 enum {
505 	NO_RATE      = 0,
506 	RATE_1MBPS   = 0x0A,
507 	RATE_2MBPS   = 0x14,
508 	RATE_5_5MBPS = 0x37,
509 	RATE_6MBPS   = 0x0B,
510 	RATE_9MBPS   = 0x0F,
511 	RATE_11MBPS  = 0x6E,
512 	RATE_12MBPS  = 0x0A,
513 	RATE_18MBPS  = 0x0E,
514 	RATE_22MBPS  = 0xDC,
515 	RATE_24MBPS  = 0x09,
516 	RATE_36MBPS  = 0x0D,
517 	RATE_48MBPS  = 0x08,
518 	RATE_54MBPS  = 0x0C
519 };
520 
521 enum {
522 	RATE_INDEX_1MBPS   =  0,
523 	RATE_INDEX_2MBPS   =  1,
524 	RATE_INDEX_5_5MBPS =  2,
525 	RATE_INDEX_6MBPS   =  3,
526 	RATE_INDEX_9MBPS   =  4,
527 	RATE_INDEX_11MBPS  =  5,
528 	RATE_INDEX_12MBPS  =  6,
529 	RATE_INDEX_18MBPS  =  7,
530 	RATE_INDEX_22MBPS  =  8,
531 	RATE_INDEX_24MBPS  =  9,
532 	RATE_INDEX_36MBPS  =  10,
533 	RATE_INDEX_48MBPS  =  11,
534 	RATE_INDEX_54MBPS  =  12,
535 	RATE_INDEX_MAX     =  RATE_INDEX_54MBPS,
536 	MAX_RATE_INDEX,
537 	INVALID_RATE_INDEX = MAX_RATE_INDEX,
538 	RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF
539 };
540 
541 enum {
542 	RATE_MASK_1MBPS = 0x1,
543 	RATE_MASK_2MBPS = 0x2,
544 	RATE_MASK_5_5MBPS = 0x4,
545 	RATE_MASK_11MBPS = 0x20,
546 };
547 
548 #define SHORT_PREAMBLE_BIT   BIT(0) /* CCK or Barker depending on the rate */
549 #define OFDM_RATE_BIT        BIT(6)
550 #define PBCC_RATE_BIT        BIT(7)
551 
552 enum {
553 	CCK_LONG = 0,
554 	CCK_SHORT = SHORT_PREAMBLE_BIT,
555 	PBCC_LONG = PBCC_RATE_BIT,
556 	PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
557 	OFDM = OFDM_RATE_BIT
558 };
559 
560 /******************************************************************************
561 
562 Transmit-Descriptor RATE-SET field definitions...
563 
564 Define a new "Rate-Set" for TX path that incorporates the
565 Rate & Modulation info into a single 16-bit field.
566 
567 TxdRateSet_t:
568 b15   - Indicates Preamble type (1=SHORT, 0=LONG).
569 	Notes:
570 	Must be LONG (0) for 1Mbps rate.
571 	Does not apply (set to 0) for RevG-OFDM rates.
572 b14   - Indicates PBCC encoding (1=PBCC, 0=not).
573 	Notes:
574 	Does not apply (set to 0) for rates 1 and 2 Mbps.
575 	Does not apply (set to 0) for RevG-OFDM rates.
576 b13    - Unused (set to 0).
577 b12-b0 - Supported Rate indicator bits as defined below.
578 
579 ******************************************************************************/
580 
581 
582 /*************************************************************************
583 
584     Interrupt Trigger Register (Host -> WiLink)
585 
586 **************************************************************************/
587 
588 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
589 
590 /*
591  * Host Command Interrupt. Setting this bit masks
592  * the interrupt that the host issues to inform
593  * the FW that it has sent a command
594  * to the Wlan hardware Command Mailbox.
595  */
596 #define INTR_TRIG_CMD       BIT(0)
597 
598 /*
599  * Host Event Acknowlegde Interrupt. The host
600  * sets this bit to acknowledge that it received
601  * the unsolicited information from the event
602  * mailbox.
603  */
604 #define INTR_TRIG_EVENT_ACK BIT(1)
605 
606 /*
607  * The host sets this bit to inform the Wlan
608  * FW that a TX packet is in the XFER
609  * Buffer #0.
610  */
611 #define INTR_TRIG_TX_PROC0 BIT(2)
612 
613 /*
614  * The host sets this bit to inform the FW
615  * that it read a packet from RX XFER
616  * Buffer #0.
617  */
618 #define INTR_TRIG_RX_PROC0 BIT(3)
619 
620 #define INTR_TRIG_DEBUG_ACK BIT(4)
621 
622 #define INTR_TRIG_STATE_CHANGED BIT(5)
623 
624 
625 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
626 
627 /*
628  * The host sets this bit to inform the FW
629  * that it read a packet from RX XFER
630  * Buffer #1.
631  */
632 #define INTR_TRIG_RX_PROC1 BIT(17)
633 
634 /*
635  * The host sets this bit to inform the Wlan
636  * hardware that a TX packet is in the XFER
637  * Buffer #1.
638  */
639 #define INTR_TRIG_TX_PROC1 BIT(18)
640 
641 #endif
642