1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 * 3 * Copyright (C) 2025 Renesas Electronics Corp. 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 7 #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ 8 9 #include <dt-bindings/clock/renesas-cpg-mssr.h> 10 11 /* R9A09G077 CPG Core Clocks */ 12 #define R9A09G077_CLK_CA55C0 0 13 #define R9A09G077_CLK_CA55C1 1 14 #define R9A09G077_CLK_CA55C2 2 15 #define R9A09G077_CLK_CA55C3 3 16 #define R9A09G077_CLK_CA55S 4 17 #define R9A09G077_CLK_CR52_CPU0 5 18 #define R9A09G077_CLK_CR52_CPU1 6 19 #define R9A09G077_CLK_CKIO 7 20 #define R9A09G077_CLK_PCLKAH 8 21 #define R9A09G077_CLK_PCLKAM 9 22 #define R9A09G077_CLK_PCLKAL 10 23 #define R9A09G077_CLK_PCLKGPTL 11 24 #define R9A09G077_CLK_PCLKH 12 25 #define R9A09G077_CLK_PCLKM 13 26 #define R9A09G077_CLK_PCLKL 14 27 #define R9A09G077_SDHI_CLKHS 15 28 #define R9A09G077_USB_CLK 16 29 #define R9A09G077_ETCLKA 17 30 #define R9A09G077_ETCLKB 18 31 #define R9A09G077_ETCLKC 19 32 #define R9A09G077_ETCLKD 20 33 #define R9A09G077_ETCLKE 21 34 35 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ 36