1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Freescale QuadSPI driver. 5 * 6 * Copyright (C) 2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2018 Bootlin 8 * Copyright (C) 2018 exceet electronics GmbH 9 * Copyright (C) 2018 Kontron Electronics GmbH 10 * 11 * Transition to SPI MEM interface: 12 * Authors: 13 * Boris Brezillon <bbrezillon@kernel.org> 14 * Frieder Schrempf <frieder.schrempf@kontron.de> 15 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com> 16 * Suresh Gupta <suresh.gupta@nxp.com> 17 * 18 * Based on the original fsl-quadspi.c SPI NOR driver: 19 * Author: Freescale Semiconductor, Inc. 20 * 21 */ 22 23 #include <linux/bitops.h> 24 #include <linux/clk.h> 25 #include <linux/completion.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/jiffies.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/mutex.h> 36 #include <linux/of.h> 37 #include <linux/platform_device.h> 38 #include <linux/pm_qos.h> 39 #include <linux/reset.h> 40 #include <linux/sizes.h> 41 42 #include <linux/spi/spi.h> 43 #include <linux/spi/spi-mem.h> 44 45 /* 46 * The driver only uses one single LUT entry, that is updated on 47 * each call of exec_op(). Index 0 is preset at boot with a basic 48 * read operation, so let's use the last entry (15). 49 */ 50 #define SEQID_LUT 15 51 52 /* Registers used by the driver */ 53 #define QUADSPI_MCR 0x00 54 #define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) 55 #define QUADSPI_MCR_MDIS_MASK BIT(14) 56 #define QUADSPI_MCR_CLR_TXF_MASK BIT(11) 57 #define QUADSPI_MCR_CLR_RXF_MASK BIT(10) 58 #define QUADSPI_MCR_DDR_EN_MASK BIT(7) 59 #define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) 60 #define QUADSPI_MCR_SWRSTHD_MASK BIT(1) 61 #define QUADSPI_MCR_SWRSTSD_MASK BIT(0) 62 63 #define QUADSPI_IPCR 0x08 64 #define QUADSPI_IPCR_SEQID(x) ((x) << 24) 65 66 #define QUADSPI_FLSHCR 0x0c 67 #define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) 68 #define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) 69 #define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) 70 71 #define QUADSPI_BUF0CR 0x10 72 #define QUADSPI_BUF1CR 0x14 73 #define QUADSPI_BUF2CR 0x18 74 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe 75 76 #define QUADSPI_BUF3CR 0x1c 77 #define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) 78 #define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) 79 #define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) 80 81 #define QUADSPI_BFGENCR 0x20 82 #define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) 83 84 #define QUADSPI_BUF0IND 0x30 85 #define QUADSPI_BUF1IND 0x34 86 #define QUADSPI_BUF2IND 0x38 87 #define QUADSPI_SFAR 0x100 88 89 #define QUADSPI_SMPR 0x108 90 #define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) 91 #define QUADSPI_SMPR_FSDLY_MASK BIT(6) 92 #define QUADSPI_SMPR_FSPHS_MASK BIT(5) 93 #define QUADSPI_SMPR_HSENA_MASK BIT(0) 94 95 #define QUADSPI_RBCT 0x110 96 #define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) 97 #define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) 98 99 #define QUADSPI_TBDR 0x154 100 101 #define QUADSPI_SR 0x15c 102 #define QUADSPI_SR_IP_ACC_MASK BIT(1) 103 #define QUADSPI_SR_AHB_ACC_MASK BIT(2) 104 105 #define QUADSPI_FR 0x160 106 #define QUADSPI_FR_TFF_MASK BIT(0) 107 108 #define QUADSPI_RSER 0x164 109 #define QUADSPI_RSER_TFIE BIT(0) 110 111 #define QUADSPI_SPTRCLR 0x16c 112 #define QUADSPI_SPTRCLR_IPPTRC BIT(8) 113 #define QUADSPI_SPTRCLR_BFPTRC BIT(0) 114 115 #define QUADSPI_SFA1AD 0x180 116 #define QUADSPI_SFA2AD 0x184 117 #define QUADSPI_SFB1AD 0x188 118 #define QUADSPI_SFB2AD 0x18c 119 #define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) 120 121 #define QUADSPI_LUTKEY 0x300 122 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 123 124 #define QUADSPI_LCKCR 0x304 125 #define QUADSPI_LCKER_LOCK BIT(0) 126 #define QUADSPI_LCKER_UNLOCK BIT(1) 127 128 #define QUADSPI_LUT_BASE 0x310 129 #define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 130 #define QUADSPI_LUT_REG(idx) \ 131 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) 132 133 /* Instruction set for the LUT register */ 134 #define LUT_STOP 0 135 #define LUT_CMD 1 136 #define LUT_ADDR 2 137 #define LUT_DUMMY 3 138 #define LUT_MODE 4 139 #define LUT_MODE2 5 140 #define LUT_MODE4 6 141 #define LUT_FSL_READ 7 142 #define LUT_FSL_WRITE 8 143 #define LUT_JMP_ON_CS 9 144 #define LUT_ADDR_DDR 10 145 #define LUT_MODE_DDR 11 146 #define LUT_MODE2_DDR 12 147 #define LUT_MODE4_DDR 13 148 #define LUT_FSL_READ_DDR 14 149 #define LUT_FSL_WRITE_DDR 15 150 #define LUT_DATA_LEARN 16 151 152 /* 153 * The PAD definitions for LUT register. 154 * 155 * The pad stands for the number of IO lines [0:3]. 156 * For example, the quad read needs four IO lines, 157 * so you should use LUT_PAD(4). 158 */ 159 #define LUT_PAD(x) (fls(x) - 1) 160 161 /* 162 * Macro for constructing the LUT entries with the following 163 * register layout: 164 * 165 * --------------------------------------------------- 166 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 167 * --------------------------------------------------- 168 */ 169 #define LUT_DEF(idx, ins, pad, opr) \ 170 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) 171 172 /* Controller needs driver to swap endianness */ 173 #define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) 174 175 /* Controller needs 4x internal clock */ 176 #define QUADSPI_QUIRK_4X_INT_CLK BIT(1) 177 178 /* 179 * TKT253890, the controller needs the driver to fill the txfifo with 180 * 16 bytes at least to trigger a data transfer, even though the extra 181 * data won't be transferred. 182 */ 183 #define QUADSPI_QUIRK_TKT253890 BIT(2) 184 185 /* TKT245618, the controller cannot wake up from wait mode */ 186 #define QUADSPI_QUIRK_TKT245618 BIT(3) 187 188 /* 189 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) 190 * internally. No need to add it when setting SFXXAD and SFAR registers 191 */ 192 #define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) 193 194 /* 195 * Controller uses TDH bits in register QUADSPI_FLSHCR. 196 * They need to be set in accordance with the DDR/SDR mode. 197 */ 198 #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) 199 200 /* 201 * Do not disable the "qspi" clock when changing its rate. 202 */ 203 #define QUADSPI_QUIRK_SKIP_CLK_DISABLE BIT(6) 204 205 struct fsl_qspi_devtype_data { 206 unsigned int rxfifo; 207 unsigned int txfifo; 208 int invalid_mstrid; 209 unsigned int ahb_buf_size; 210 unsigned int sfa_size; 211 unsigned int quirks; 212 bool little_endian; 213 }; 214 215 static const struct fsl_qspi_devtype_data vybrid_data = { 216 .rxfifo = SZ_128, 217 .txfifo = SZ_64, 218 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 219 .ahb_buf_size = SZ_1K, 220 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, 221 .little_endian = true, 222 }; 223 224 static const struct fsl_qspi_devtype_data imx6sx_data = { 225 .rxfifo = SZ_128, 226 .txfifo = SZ_512, 227 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 228 .ahb_buf_size = SZ_1K, 229 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, 230 .little_endian = true, 231 }; 232 233 static const struct fsl_qspi_devtype_data imx7d_data = { 234 .rxfifo = SZ_128, 235 .txfifo = SZ_512, 236 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 237 .ahb_buf_size = SZ_1K, 238 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | 239 QUADSPI_QUIRK_USE_TDH_SETTING, 240 .little_endian = true, 241 }; 242 243 static const struct fsl_qspi_devtype_data imx6ul_data = { 244 .rxfifo = SZ_128, 245 .txfifo = SZ_512, 246 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 247 .ahb_buf_size = SZ_1K, 248 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | 249 QUADSPI_QUIRK_USE_TDH_SETTING, 250 .little_endian = true, 251 }; 252 253 static const struct fsl_qspi_devtype_data ls1021a_data = { 254 .rxfifo = SZ_128, 255 .txfifo = SZ_64, 256 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 257 .ahb_buf_size = SZ_1K, 258 .quirks = 0, 259 .little_endian = false, 260 }; 261 262 static const struct fsl_qspi_devtype_data ls2080a_data = { 263 .rxfifo = SZ_128, 264 .txfifo = SZ_64, 265 .ahb_buf_size = SZ_1K, 266 .invalid_mstrid = 0x0, 267 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, 268 .little_endian = true, 269 }; 270 271 static const struct fsl_qspi_devtype_data spacemit_k1_data = { 272 .rxfifo = SZ_128, 273 .txfifo = SZ_256, 274 .ahb_buf_size = SZ_512, 275 .sfa_size = SZ_1K, 276 .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, 277 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE, 278 .little_endian = true, 279 }; 280 281 struct fsl_qspi { 282 void __iomem *iobase; 283 void __iomem *ahb_addr; 284 const struct fsl_qspi_devtype_data *devtype_data; 285 struct mutex lock; 286 struct completion c; 287 struct reset_control *resets; 288 struct clk *clk, *clk_en; 289 struct pm_qos_request pm_qos_req; 290 struct device *dev; 291 int selected; 292 u32 memmap_phy; 293 }; 294 295 static bool needs_swap_endian(struct fsl_qspi *q) 296 { 297 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN); 298 } 299 300 static bool needs_4x_clock(struct fsl_qspi *q) 301 { 302 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK); 303 } 304 305 static bool needs_fill_txfifo(struct fsl_qspi *q) 306 { 307 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890); 308 } 309 310 static bool needs_wakeup_wait_mode(struct fsl_qspi *q) 311 { 312 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618); 313 } 314 315 static bool needs_amba_base_offset(struct fsl_qspi *q) 316 { 317 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); 318 } 319 320 static bool needs_tdh_setting(struct fsl_qspi *q) 321 { 322 return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING); 323 } 324 325 static bool needs_clk_disable(struct fsl_qspi *q) 326 { 327 return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE); 328 } 329 330 /* 331 * An IC bug makes it necessary to rearrange the 32-bit data. 332 * Later chips, such as IMX6SLX, have fixed this bug. 333 */ 334 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) 335 { 336 return needs_swap_endian(q) ? __swab32(a) : a; 337 } 338 339 /* 340 * R/W functions for big- or little-endian registers: 341 * The QSPI controller's endianness is independent of 342 * the CPU core's endianness. So far, although the CPU 343 * core is little-endian the QSPI controller can use 344 * big-endian or little-endian. 345 */ 346 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) 347 { 348 if (q->devtype_data->little_endian) 349 iowrite32(val, addr); 350 else 351 iowrite32be(val, addr); 352 } 353 354 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) 355 { 356 if (q->devtype_data->little_endian) 357 return ioread32(addr); 358 359 return ioread32be(addr); 360 } 361 362 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id) 363 { 364 struct fsl_qspi *q = dev_id; 365 u32 reg; 366 367 /* clear interrupt */ 368 reg = qspi_readl(q, q->iobase + QUADSPI_FR); 369 qspi_writel(q, reg, q->iobase + QUADSPI_FR); 370 371 if (reg & QUADSPI_FR_TFF_MASK) 372 complete(&q->c); 373 374 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg); 375 return IRQ_HANDLED; 376 } 377 378 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) 379 { 380 switch (width) { 381 case 1: 382 case 2: 383 case 4: 384 return 0; 385 } 386 387 return -ENOTSUPP; 388 } 389 390 static bool fsl_qspi_supports_op(struct spi_mem *mem, 391 const struct spi_mem_op *op) 392 { 393 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); 394 int ret; 395 396 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); 397 398 if (op->addr.nbytes) 399 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); 400 401 if (op->dummy.nbytes) 402 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); 403 404 if (op->data.nbytes) 405 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); 406 407 if (ret) 408 return false; 409 410 /* 411 * The number of instructions needed for the op, needs 412 * to fit into a single LUT entry. 413 */ 414 if (op->addr.nbytes + 415 (op->dummy.nbytes ? 1:0) + 416 (op->data.nbytes ? 1:0) > 6) 417 return false; 418 419 /* Max 64 dummy clock cycles supported */ 420 if (op->dummy.nbytes && 421 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 422 return false; 423 424 /* Max data length, check controller limits and alignment */ 425 if (op->data.dir == SPI_MEM_DATA_IN && 426 (op->data.nbytes > q->devtype_data->ahb_buf_size || 427 (op->data.nbytes > q->devtype_data->rxfifo - 4 && 428 !IS_ALIGNED(op->data.nbytes, 8)))) 429 return false; 430 431 if (op->data.dir == SPI_MEM_DATA_OUT && 432 op->data.nbytes > q->devtype_data->txfifo) 433 return false; 434 435 return spi_mem_default_supports_op(mem, op); 436 } 437 438 static void fsl_qspi_prepare_lut(struct fsl_qspi *q, 439 const struct spi_mem_op *op) 440 { 441 void __iomem *base = q->iobase; 442 u32 lutval[4] = {}; 443 int lutidx = 1, i; 444 445 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 446 op->cmd.opcode); 447 448 /* 449 * For some unknown reason, using LUT_ADDR doesn't work in some 450 * cases (at least with only one byte long addresses), so 451 * let's use LUT_MODE to write the address bytes one by one 452 */ 453 for (i = 0; i < op->addr.nbytes; i++) { 454 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); 455 456 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, 457 LUT_PAD(op->addr.buswidth), 458 addrbyte); 459 lutidx++; 460 } 461 462 if (op->dummy.nbytes) { 463 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 464 LUT_PAD(op->dummy.buswidth), 465 op->dummy.nbytes * 8 / 466 op->dummy.buswidth); 467 lutidx++; 468 } 469 470 if (op->data.nbytes) { 471 lutval[lutidx / 2] |= LUT_DEF(lutidx, 472 op->data.dir == SPI_MEM_DATA_IN ? 473 LUT_FSL_READ : LUT_FSL_WRITE, 474 LUT_PAD(op->data.buswidth), 475 0); 476 lutidx++; 477 } 478 479 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 480 481 /* unlock LUT */ 482 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); 483 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); 484 485 /* fill LUT */ 486 for (i = 0; i < ARRAY_SIZE(lutval); i++) 487 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); 488 489 /* lock LUT */ 490 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); 491 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); 492 } 493 494 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q) 495 { 496 int ret; 497 498 ret = clk_prepare_enable(q->clk_en); 499 if (ret) 500 return ret; 501 502 ret = clk_prepare_enable(q->clk); 503 if (ret) { 504 clk_disable_unprepare(q->clk_en); 505 return ret; 506 } 507 508 if (needs_wakeup_wait_mode(q)) 509 cpu_latency_qos_add_request(&q->pm_qos_req, 0); 510 511 return 0; 512 } 513 514 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q) 515 { 516 if (needs_wakeup_wait_mode(q)) 517 cpu_latency_qos_remove_request(&q->pm_qos_req); 518 519 clk_disable_unprepare(q->clk); 520 clk_disable_unprepare(q->clk_en); 521 } 522 523 /* 524 * If we have changed the content of the flash by writing or erasing, or if we 525 * read from flash with a different offset into the page buffer, we need to 526 * invalidate the AHB buffer. If we do not do so, we may read out the wrong 527 * data. The spec tells us reset the AHB domain and Serial Flash domain at 528 * the same time. 529 */ 530 static void fsl_qspi_invalidate(struct fsl_qspi *q) 531 { 532 u32 reg; 533 534 reg = qspi_readl(q, q->iobase + QUADSPI_MCR); 535 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; 536 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); 537 538 /* 539 * The minimum delay : 1 AHB + 2 SFCK clocks. 540 * Delay 1 us is enough. 541 */ 542 udelay(1); 543 544 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); 545 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); 546 } 547 548 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi, 549 const struct spi_mem_op *op) 550 { 551 unsigned long rate = op->max_freq; 552 int ret; 553 554 if (q->selected == spi_get_chipselect(spi, 0)) 555 return; 556 557 if (needs_4x_clock(q)) 558 rate *= 4; 559 560 if (needs_clk_disable(q)) 561 fsl_qspi_clk_disable_unprep(q); 562 563 ret = clk_set_rate(q->clk, rate); 564 if (ret) 565 return; 566 567 if (needs_clk_disable(q)) { 568 ret = fsl_qspi_clk_prep_enable(q); 569 if (ret) 570 return; 571 } 572 573 q->selected = spi_get_chipselect(spi, 0); 574 575 fsl_qspi_invalidate(q); 576 } 577 578 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) 579 { 580 memcpy_fromio(op->data.buf.in, 581 q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, 582 op->data.nbytes); 583 } 584 585 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, 586 const struct spi_mem_op *op) 587 { 588 void __iomem *base = q->iobase; 589 int i; 590 u32 val; 591 592 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { 593 memcpy(&val, op->data.buf.out + i, 4); 594 val = fsl_qspi_endian_xchg(q, val); 595 qspi_writel(q, val, base + QUADSPI_TBDR); 596 } 597 598 if (i < op->data.nbytes) { 599 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); 600 val = fsl_qspi_endian_xchg(q, val); 601 qspi_writel(q, val, base + QUADSPI_TBDR); 602 } 603 604 if (needs_fill_txfifo(q)) { 605 for (i = op->data.nbytes; i < 16; i += 4) 606 qspi_writel(q, 0, base + QUADSPI_TBDR); 607 } 608 } 609 610 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, 611 const struct spi_mem_op *op) 612 { 613 void __iomem *base = q->iobase; 614 int i; 615 u8 *buf = op->data.buf.in; 616 u32 val; 617 618 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { 619 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); 620 val = fsl_qspi_endian_xchg(q, val); 621 memcpy(buf + i, &val, 4); 622 } 623 624 if (i < op->data.nbytes) { 625 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); 626 val = fsl_qspi_endian_xchg(q, val); 627 memcpy(buf + i, &val, op->data.nbytes - i); 628 } 629 } 630 631 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) 632 { 633 void __iomem *base = q->iobase; 634 int err = 0; 635 636 init_completion(&q->c); 637 638 /* 639 * Always start the sequence at the same index since we update 640 * the LUT at each exec_op() call. And also specify the DATA 641 * length, since it's has not been specified in the LUT. 642 */ 643 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), 644 base + QUADSPI_IPCR); 645 646 /* Wait for the interrupt. */ 647 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) 648 err = -ETIMEDOUT; 649 650 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 651 fsl_qspi_read_rxfifo(q, op); 652 653 return err; 654 } 655 656 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, 657 u32 mask, u32 delay_us, u32 timeout_us) 658 { 659 u32 reg; 660 661 if (!q->devtype_data->little_endian) 662 mask = (u32)cpu_to_be32(mask); 663 664 return readl_poll_timeout(base, reg, !(reg & mask), delay_us, 665 timeout_us); 666 } 667 668 static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 669 { 670 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); 671 void __iomem *base = q->iobase; 672 u32 addr_offset = 0; 673 int err = 0; 674 int invalid_mstrid = q->devtype_data->invalid_mstrid; 675 676 mutex_lock(&q->lock); 677 678 /* wait for the controller being ready */ 679 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | 680 QUADSPI_SR_AHB_ACC_MASK), 10, 1000); 681 682 fsl_qspi_select_mem(q, mem->spi, op); 683 684 if (needs_amba_base_offset(q)) 685 addr_offset = q->memmap_phy; 686 687 qspi_writel(q, 688 q->selected * q->devtype_data->ahb_buf_size + addr_offset, 689 base + QUADSPI_SFAR); 690 691 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | 692 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, 693 base + QUADSPI_MCR); 694 695 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, 696 base + QUADSPI_SPTRCLR); 697 698 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR); 699 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR); 700 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR); 701 702 fsl_qspi_prepare_lut(q, op); 703 704 /* 705 * If we have large chunks of data, we read them through the AHB bus 706 * by accessing the mapped memory. In all other cases we use 707 * IP commands to access the flash. 708 */ 709 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && 710 op->data.dir == SPI_MEM_DATA_IN) { 711 fsl_qspi_read_ahb(q, op); 712 } else { 713 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | 714 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); 715 716 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 717 fsl_qspi_fill_txfifo(q, op); 718 719 err = fsl_qspi_do_op(q, op); 720 } 721 722 /* Invalidate the data in the AHB buffer. */ 723 fsl_qspi_invalidate(q); 724 725 mutex_unlock(&q->lock); 726 727 return err; 728 } 729 730 static int fsl_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 731 { 732 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); 733 734 if (op->data.dir == SPI_MEM_DATA_OUT) { 735 if (op->data.nbytes > q->devtype_data->txfifo) 736 op->data.nbytes = q->devtype_data->txfifo; 737 } else { 738 if (op->data.nbytes > q->devtype_data->ahb_buf_size) 739 op->data.nbytes = q->devtype_data->ahb_buf_size; 740 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) 741 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 742 } 743 744 return 0; 745 } 746 747 static int fsl_qspi_default_setup(struct fsl_qspi *q) 748 { 749 void __iomem *base = q->iobase; 750 u32 reg, addr_offset = 0; 751 u32 sfa_size; 752 int ret; 753 754 /* disable and unprepare clock to avoid glitch pass to controller */ 755 fsl_qspi_clk_disable_unprep(q); 756 757 /* the default frequency, we will change it later if necessary. */ 758 ret = clk_set_rate(q->clk, 66000000); 759 if (ret) 760 return ret; 761 762 ret = fsl_qspi_clk_prep_enable(q); 763 if (ret) 764 return ret; 765 766 /* Reset the module */ 767 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, 768 base + QUADSPI_MCR); 769 udelay(1); 770 771 /* Disable the module */ 772 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, 773 base + QUADSPI_MCR); 774 775 /* 776 * Previous boot stages (BootROM, bootloader) might have used DDR 777 * mode and did not clear the TDH bits. As we currently use SDR mode 778 * only, clear the TDH bits if necessary. 779 */ 780 if (needs_tdh_setting(q)) 781 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & 782 ~QUADSPI_FLSHCR_TDH_MASK, 783 base + QUADSPI_FLSHCR); 784 785 reg = qspi_readl(q, base + QUADSPI_SMPR); 786 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK 787 | QUADSPI_SMPR_FSPHS_MASK 788 | QUADSPI_SMPR_HSENA_MASK 789 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); 790 791 /* We only use the buffer3 for AHB read */ 792 qspi_writel(q, 0, base + QUADSPI_BUF0IND); 793 qspi_writel(q, 0, base + QUADSPI_BUF1IND); 794 qspi_writel(q, 0, base + QUADSPI_BUF2IND); 795 796 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), 797 q->iobase + QUADSPI_BFGENCR); 798 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); 799 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | 800 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), 801 base + QUADSPI_BUF3CR); 802 803 if (needs_amba_base_offset(q)) 804 addr_offset = q->memmap_phy; 805 806 /* 807 * In HW there can be a maximum of four chips on two buses with 808 * two chip selects on each bus. We use four chip selects in SW 809 * to differentiate between the four chips. 810 * 811 * By default we write the AHB buffer size to each chip, but 812 * a different size can be specified with devtype_data->sfa_size. 813 * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the 814 * top (end) of these four regions. 815 */ 816 sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size; 817 qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD); 818 qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD); 819 qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD); 820 qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD); 821 822 q->selected = -1; 823 824 /* Enable the module */ 825 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, 826 base + QUADSPI_MCR); 827 828 /* clear all interrupt status */ 829 qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR); 830 831 /* enable the interrupt */ 832 qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); 833 834 return 0; 835 } 836 837 static const char *fsl_qspi_get_name(struct spi_mem *mem) 838 { 839 struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller); 840 struct device *dev = &mem->spi->dev; 841 const char *name; 842 843 /* 844 * In order to keep mtdparts compatible with the old MTD driver at 845 * mtd/spi-nor/fsl-quadspi.c, we set a custom name derived from the 846 * platform_device of the controller. 847 */ 848 if (of_get_available_child_count(q->dev->of_node) == 1) 849 return dev_name(q->dev); 850 851 name = devm_kasprintf(dev, GFP_KERNEL, 852 "%s-%d", dev_name(q->dev), 853 spi_get_chipselect(mem->spi, 0)); 854 855 if (!name) { 856 dev_err(dev, "failed to get memory for custom flash name\n"); 857 return ERR_PTR(-ENOMEM); 858 } 859 860 return name; 861 } 862 863 static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { 864 .adjust_op_size = fsl_qspi_adjust_op_size, 865 .supports_op = fsl_qspi_supports_op, 866 .exec_op = fsl_qspi_exec_op, 867 .get_name = fsl_qspi_get_name, 868 }; 869 870 static const struct spi_controller_mem_caps fsl_qspi_mem_caps = { 871 .per_op_freq = true, 872 }; 873 874 static void fsl_qspi_disable(void *data) 875 { 876 struct fsl_qspi *q = data; 877 878 /* disable the hardware */ 879 qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); 880 qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER); 881 } 882 883 static void fsl_qspi_cleanup(void *data) 884 { 885 struct fsl_qspi *q = data; 886 887 reset_control_assert(q->resets); 888 889 fsl_qspi_clk_disable_unprep(q); 890 891 mutex_destroy(&q->lock); 892 } 893 894 static int fsl_qspi_probe(struct platform_device *pdev) 895 { 896 struct spi_controller *ctlr; 897 struct device *dev = &pdev->dev; 898 struct device_node *np = dev->of_node; 899 struct resource *res; 900 struct fsl_qspi *q; 901 int ret; 902 903 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*q)); 904 if (!ctlr) 905 return -ENOMEM; 906 907 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | 908 SPI_TX_DUAL | SPI_TX_QUAD; 909 910 q = spi_controller_get_devdata(ctlr); 911 q->dev = dev; 912 q->devtype_data = of_device_get_match_data(dev); 913 if (!q->devtype_data) 914 return -ENODEV; 915 916 platform_set_drvdata(pdev, q); 917 918 /* find the resources */ 919 q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI"); 920 if (IS_ERR(q->iobase)) 921 return PTR_ERR(q->iobase); 922 923 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 924 "QuadSPI-memory"); 925 if (!res) 926 return -EINVAL; 927 q->memmap_phy = res->start; 928 /* Since there are 4 cs, map size required is 4 times ahb_buf_size */ 929 q->ahb_addr = devm_ioremap(dev, q->memmap_phy, 930 (q->devtype_data->ahb_buf_size * 4)); 931 if (!q->ahb_addr) 932 return -ENOMEM; 933 934 q->resets = devm_reset_control_array_get_optional_exclusive(dev); 935 if (IS_ERR(q->resets)) 936 return PTR_ERR(q->resets); 937 938 /* find the clocks */ 939 q->clk_en = devm_clk_get(dev, "qspi_en"); 940 if (IS_ERR(q->clk_en)) 941 return PTR_ERR(q->clk_en); 942 943 q->clk = devm_clk_get(dev, "qspi"); 944 if (IS_ERR(q->clk)) 945 return PTR_ERR(q->clk); 946 947 mutex_init(&q->lock); 948 949 ret = fsl_qspi_clk_prep_enable(q); 950 if (ret) { 951 dev_err(dev, "can not enable the clock\n"); 952 return ret; 953 } 954 955 ret = devm_add_action_or_reset(dev, fsl_qspi_cleanup, q); 956 if (ret) 957 return ret; 958 959 ret = reset_control_deassert(q->resets); 960 if (ret) 961 return ret; 962 963 /* find the irq */ 964 ret = platform_get_irq(pdev, 0); 965 if (ret < 0) 966 return ret; 967 968 ret = devm_request_irq(dev, ret, 969 fsl_qspi_irq_handler, 0, pdev->name, q); 970 if (ret) { 971 dev_err(dev, "failed to request irq: %d\n", ret); 972 return ret; 973 } 974 975 ctlr->bus_num = -1; 976 ctlr->num_chipselect = 4; 977 ctlr->mem_ops = &fsl_qspi_mem_ops; 978 ctlr->mem_caps = &fsl_qspi_mem_caps; 979 980 fsl_qspi_default_setup(q); 981 982 ctlr->dev.of_node = np; 983 984 ret = devm_add_action_or_reset(dev, fsl_qspi_disable, q); 985 if (ret) 986 return ret; 987 988 ret = devm_spi_register_controller(dev, ctlr); 989 if (ret) 990 return ret; 991 992 return 0; 993 } 994 995 static int fsl_qspi_suspend(struct device *dev) 996 { 997 return 0; 998 } 999 1000 static int fsl_qspi_resume(struct device *dev) 1001 { 1002 struct fsl_qspi *q = dev_get_drvdata(dev); 1003 1004 fsl_qspi_default_setup(q); 1005 1006 return 0; 1007 } 1008 1009 static const struct of_device_id fsl_qspi_dt_ids[] = { 1010 { .compatible = "fsl,vf610-qspi", .data = &vybrid_data, }, 1011 { .compatible = "fsl,imx6sx-qspi", .data = &imx6sx_data, }, 1012 { .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, }, 1013 { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, }, 1014 { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, }, 1015 { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, }, 1016 { .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, }, 1017 { /* sentinel */ } 1018 }; 1019 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids); 1020 1021 static const struct dev_pm_ops fsl_qspi_pm_ops = { 1022 .suspend = fsl_qspi_suspend, 1023 .resume = fsl_qspi_resume, 1024 }; 1025 1026 static struct platform_driver fsl_qspi_driver = { 1027 .driver = { 1028 .name = "fsl-quadspi", 1029 .of_match_table = fsl_qspi_dt_ids, 1030 .pm = &fsl_qspi_pm_ops, 1031 }, 1032 .probe = fsl_qspi_probe, 1033 }; 1034 module_platform_driver(fsl_qspi_driver); 1035 1036 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver"); 1037 MODULE_AUTHOR("Freescale Semiconductor Inc."); 1038 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1039 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1040 MODULE_AUTHOR("Yogesh Gaur <yogeshnarayan.gaur@nxp.com>"); 1041 MODULE_AUTHOR("Suresh Gupta <suresh.gupta@nxp.com>"); 1042 MODULE_LICENSE("GPL v2"); 1043