1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 #include <linux/sizes.h> 23 #include <linux/spi/spi-mem.h> 24 25 #define QSPI_CR 0x00 26 #define CR_EN BIT(0) 27 #define CR_ABORT BIT(1) 28 #define CR_DMAEN BIT(2) 29 #define CR_TCEN BIT(3) 30 #define CR_SSHIFT BIT(4) 31 #define CR_DFM BIT(6) 32 #define CR_FSEL BIT(7) 33 #define CR_FTHRES_SHIFT 8 34 #define CR_FTIE BIT(18) 35 #define CR_SMIE BIT(19) 36 #define CR_TOIE BIT(20) 37 #define CR_APMS BIT(22) 38 #define CR_PRESC_MASK GENMASK(31, 24) 39 40 #define QSPI_DCR 0x04 41 #define DCR_FSIZE_MASK GENMASK(20, 16) 42 43 #define QSPI_SR 0x08 44 #define SR_TEF BIT(0) 45 #define SR_TCF BIT(1) 46 #define SR_FTF BIT(2) 47 #define SR_SMF BIT(3) 48 #define SR_TOF BIT(4) 49 #define SR_BUSY BIT(5) 50 #define SR_FLEVEL_MASK GENMASK(13, 8) 51 52 #define QSPI_FCR 0x0c 53 #define FCR_CTEF BIT(0) 54 #define FCR_CTCF BIT(1) 55 #define FCR_CSMF BIT(3) 56 57 #define QSPI_DLR 0x10 58 59 #define QSPI_CCR 0x14 60 #define CCR_INST_MASK GENMASK(7, 0) 61 #define CCR_IMODE_MASK GENMASK(9, 8) 62 #define CCR_ADMODE_MASK GENMASK(11, 10) 63 #define CCR_ADSIZE_MASK GENMASK(13, 12) 64 #define CCR_DCYC_MASK GENMASK(22, 18) 65 #define CCR_DMODE_MASK GENMASK(25, 24) 66 #define CCR_FMODE_MASK GENMASK(27, 26) 67 #define CCR_FMODE_INDW (0U << 26) 68 #define CCR_FMODE_INDR (1U << 26) 69 #define CCR_FMODE_APM (2U << 26) 70 #define CCR_FMODE_MM (3U << 26) 71 #define CCR_BUSWIDTH_0 0x0 72 #define CCR_BUSWIDTH_1 0x1 73 #define CCR_BUSWIDTH_2 0x2 74 #define CCR_BUSWIDTH_4 0x3 75 76 #define QSPI_AR 0x18 77 #define QSPI_ABR 0x1c 78 #define QSPI_DR 0x20 79 #define QSPI_PSMKR 0x24 80 #define QSPI_PSMAR 0x28 81 #define QSPI_PIR 0x2c 82 #define QSPI_LPTR 0x30 83 84 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M 85 #define STM32_QSPI_MAX_NORCHIP 2 86 87 #define STM32_FIFO_TIMEOUT_US 30000 88 #define STM32_BUSY_TIMEOUT_US 100000 89 #define STM32_ABT_TIMEOUT_US 100000 90 #define STM32_WAIT_CMD_TIMEOUT_US 5000 91 #define STM32_COMP_TIMEOUT_MS 1000 92 #define STM32_AUTOSUSPEND_DELAY -1 93 94 struct stm32_qspi_flash { 95 u32 cs; 96 u32 presc; 97 }; 98 99 struct stm32_qspi { 100 struct device *dev; 101 struct spi_controller *ctrl; 102 phys_addr_t phys_base; 103 void __iomem *io_base; 104 void __iomem *mm_base; 105 resource_size_t mm_size; 106 struct clk *clk; 107 u32 clk_rate; 108 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP]; 109 struct completion match_completion; 110 u32 fmode; 111 112 struct dma_chan *dma_chtx; 113 struct dma_chan *dma_chrx; 114 struct completion dma_completion; 115 116 u32 cr_reg; 117 u32 dcr_reg; 118 unsigned long status_timeout; 119 120 /* 121 * to protect device configuration, could be different between 122 * 2 flash access (bk1, bk2) 123 */ 124 struct mutex lock; 125 }; 126 127 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) 128 { 129 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; 130 u32 cr, sr; 131 132 cr = readl_relaxed(qspi->io_base + QSPI_CR); 133 sr = readl_relaxed(qspi->io_base + QSPI_SR); 134 135 if (sr & SR_SMF) { 136 /* disable irq */ 137 cr &= ~CR_SMIE; 138 writel_relaxed(cr, qspi->io_base + QSPI_CR); 139 complete(&qspi->match_completion); 140 } 141 142 return IRQ_HANDLED; 143 } 144 145 static void stm32_qspi_read_fifo(void *val, void __iomem *addr, u8 len) 146 { 147 switch (len) { 148 case sizeof(u32): 149 *((u32 *)val) = readl_relaxed(addr); 150 break; 151 case sizeof(u16): 152 *((u16 *)val) = readw_relaxed(addr); 153 break; 154 case sizeof(u8): 155 *((u8 *)val) = readb_relaxed(addr); 156 } 157 } 158 159 static void stm32_qspi_write_fifo(void *val, void __iomem *addr, u8 len) 160 { 161 switch (len) { 162 case sizeof(u32): 163 writel_relaxed(*((u32 *)val), addr); 164 break; 165 case sizeof(u16): 166 writew_relaxed(*((u16 *)val), addr); 167 break; 168 case sizeof(u8): 169 writeb_relaxed(*((u8 *)val), addr); 170 } 171 } 172 173 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, 174 const struct spi_mem_op *op) 175 { 176 void (*fifo)(void *val, void __iomem *addr, u8 len); 177 u32 len = op->data.nbytes, sr; 178 void *buf; 179 int ret; 180 u8 step; 181 182 if (op->data.dir == SPI_MEM_DATA_IN) { 183 fifo = stm32_qspi_read_fifo; 184 buf = op->data.buf.in; 185 186 } else { 187 fifo = stm32_qspi_write_fifo; 188 buf = (void *)op->data.buf.out; 189 } 190 191 while (len) { 192 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, 193 sr, (sr & SR_FTF), 1, 194 STM32_FIFO_TIMEOUT_US); 195 if (ret) { 196 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", 197 len, sr); 198 return ret; 199 } 200 201 if (len >= sizeof(u32)) 202 step = sizeof(u32); 203 else if (len >= sizeof(u16)) 204 step = sizeof(u16); 205 else 206 step = sizeof(u8); 207 208 fifo(buf, qspi->io_base + QSPI_DR, step); 209 len -= step; 210 buf += step; 211 } 212 213 return 0; 214 } 215 216 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi, 217 const struct spi_mem_op *op) 218 { 219 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, 220 op->data.nbytes); 221 return 0; 222 } 223 224 static void stm32_qspi_dma_callback(void *arg) 225 { 226 struct completion *dma_completion = arg; 227 228 complete(dma_completion); 229 } 230 231 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi, 232 const struct spi_mem_op *op) 233 { 234 struct dma_async_tx_descriptor *desc; 235 enum dma_transfer_direction dma_dir; 236 struct dma_chan *dma_ch; 237 struct sg_table sgt; 238 dma_cookie_t cookie; 239 u32 cr, t_out; 240 int err; 241 242 if (op->data.dir == SPI_MEM_DATA_IN) { 243 dma_dir = DMA_DEV_TO_MEM; 244 dma_ch = qspi->dma_chrx; 245 } else { 246 dma_dir = DMA_MEM_TO_DEV; 247 dma_ch = qspi->dma_chtx; 248 } 249 250 /* 251 * spi_map_buf return -EINVAL if the buffer is not DMA-able 252 * (DMA-able: in vmalloc | kmap | virt_addr_valid) 253 */ 254 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt); 255 if (err) 256 return err; 257 258 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents, 259 dma_dir, DMA_PREP_INTERRUPT); 260 if (!desc) { 261 err = -ENOMEM; 262 goto out_unmap; 263 } 264 265 cr = readl_relaxed(qspi->io_base + QSPI_CR); 266 267 reinit_completion(&qspi->dma_completion); 268 desc->callback = stm32_qspi_dma_callback; 269 desc->callback_param = &qspi->dma_completion; 270 cookie = dmaengine_submit(desc); 271 err = dma_submit_error(cookie); 272 if (err) 273 goto out; 274 275 dma_async_issue_pending(dma_ch); 276 277 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); 278 279 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS; 280 if (!wait_for_completion_timeout(&qspi->dma_completion, 281 msecs_to_jiffies(t_out))) 282 err = -ETIMEDOUT; 283 284 if (err) 285 dmaengine_terminate_all(dma_ch); 286 287 out: 288 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); 289 out_unmap: 290 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt); 291 292 return err; 293 } 294 295 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op) 296 { 297 if (!op->data.nbytes) 298 return 0; 299 300 if (qspi->fmode == CCR_FMODE_MM) 301 return stm32_qspi_tx_mm(qspi, op); 302 else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) || 303 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) && 304 op->data.nbytes > 4) 305 if (!stm32_qspi_tx_dma(qspi, op)) 306 return 0; 307 308 return stm32_qspi_tx_poll(qspi, op); 309 } 310 311 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi) 312 { 313 u32 sr; 314 315 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, 316 !(sr & SR_BUSY), 1, 317 STM32_BUSY_TIMEOUT_US); 318 } 319 320 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi) 321 { 322 u32 sr; 323 int err = 0; 324 325 if (qspi->fmode == CCR_FMODE_APM) 326 goto out; 327 328 err = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, 329 (sr & (SR_TEF | SR_TCF)), 1, 330 STM32_WAIT_CMD_TIMEOUT_US); 331 332 if (sr & SR_TEF) 333 err = -EIO; 334 335 out: 336 /* clear flags */ 337 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR); 338 if (!err) 339 err = stm32_qspi_wait_nobusy(qspi); 340 341 return err; 342 } 343 344 static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi) 345 { 346 u32 cr; 347 348 reinit_completion(&qspi->match_completion); 349 cr = readl_relaxed(qspi->io_base + QSPI_CR); 350 writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR); 351 352 if (!wait_for_completion_timeout(&qspi->match_completion, 353 msecs_to_jiffies(qspi->status_timeout))) 354 return -ETIMEDOUT; 355 356 writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR); 357 358 return 0; 359 } 360 361 static int stm32_qspi_get_mode(u8 buswidth) 362 { 363 if (buswidth >= 4) 364 return CCR_BUSWIDTH_4; 365 366 return buswidth; 367 } 368 369 static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op) 370 { 371 struct stm32_qspi *qspi = spi_controller_get_devdata(spi->controller); 372 struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)]; 373 u32 ccr, cr; 374 int timeout, err = 0, err_poll_status = 0; 375 376 cr = readl_relaxed(qspi->io_base + QSPI_CR); 377 cr &= ~CR_PRESC_MASK & ~CR_FSEL; 378 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc); 379 cr |= FIELD_PREP(CR_FSEL, flash->cs); 380 writel_relaxed(cr, qspi->io_base + QSPI_CR); 381 382 if (op->data.nbytes) 383 writel_relaxed(op->data.nbytes - 1, 384 qspi->io_base + QSPI_DLR); 385 386 ccr = qspi->fmode; 387 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); 388 ccr |= FIELD_PREP(CCR_IMODE_MASK, 389 stm32_qspi_get_mode(op->cmd.buswidth)); 390 391 if (op->addr.nbytes) { 392 ccr |= FIELD_PREP(CCR_ADMODE_MASK, 393 stm32_qspi_get_mode(op->addr.buswidth)); 394 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); 395 } 396 397 if (op->dummy.nbytes) 398 ccr |= FIELD_PREP(CCR_DCYC_MASK, 399 op->dummy.nbytes * 8 / op->dummy.buswidth); 400 401 if (op->data.nbytes) { 402 ccr |= FIELD_PREP(CCR_DMODE_MASK, 403 stm32_qspi_get_mode(op->data.buswidth)); 404 } 405 406 writel_relaxed(ccr, qspi->io_base + QSPI_CCR); 407 408 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM) 409 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); 410 411 if (qspi->fmode == CCR_FMODE_APM) 412 err_poll_status = stm32_qspi_wait_poll_status(qspi); 413 414 err = stm32_qspi_tx(qspi, op); 415 416 /* 417 * Abort in: 418 * -error case 419 * -read memory map: prefetching must be stopped if we read the last 420 * byte of device (device size - fifo size). like device size is not 421 * knows, the prefetching is always stop. 422 */ 423 if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM) 424 goto abort; 425 426 /* wait end of tx in indirect mode */ 427 err = stm32_qspi_wait_cmd(qspi); 428 if (err) 429 goto abort; 430 431 return 0; 432 433 abort: 434 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT; 435 writel_relaxed(cr, qspi->io_base + QSPI_CR); 436 437 /* wait clear of abort bit by hw */ 438 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR, 439 cr, !(cr & CR_ABORT), 1, 440 STM32_ABT_TIMEOUT_US); 441 442 writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR); 443 444 if (err || err_poll_status || timeout) 445 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n", 446 __func__, err, err_poll_status, timeout); 447 448 return err; 449 } 450 451 static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op, 452 u16 mask, u16 match, 453 unsigned long initial_delay_us, 454 unsigned long polling_rate_us, 455 unsigned long timeout_ms) 456 { 457 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); 458 int ret; 459 460 if (!spi_mem_supports_op(mem, op)) 461 return -EOPNOTSUPP; 462 463 ret = pm_runtime_resume_and_get(qspi->dev); 464 if (ret < 0) 465 return ret; 466 467 mutex_lock(&qspi->lock); 468 469 writel_relaxed(mask, qspi->io_base + QSPI_PSMKR); 470 writel_relaxed(match, qspi->io_base + QSPI_PSMAR); 471 qspi->fmode = CCR_FMODE_APM; 472 qspi->status_timeout = timeout_ms; 473 474 ret = stm32_qspi_send(mem->spi, op); 475 mutex_unlock(&qspi->lock); 476 477 pm_runtime_put_autosuspend(qspi->dev); 478 479 return ret; 480 } 481 482 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 483 { 484 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); 485 int ret; 486 487 ret = pm_runtime_resume_and_get(qspi->dev); 488 if (ret < 0) 489 return ret; 490 491 mutex_lock(&qspi->lock); 492 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) 493 qspi->fmode = CCR_FMODE_INDR; 494 else 495 qspi->fmode = CCR_FMODE_INDW; 496 497 ret = stm32_qspi_send(mem->spi, op); 498 mutex_unlock(&qspi->lock); 499 500 pm_runtime_put_autosuspend(qspi->dev); 501 502 return ret; 503 } 504 505 static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc) 506 { 507 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); 508 509 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) 510 return -EOPNOTSUPP; 511 512 /* should never happen, as mm_base == null is an error probe exit condition */ 513 if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) 514 return -EOPNOTSUPP; 515 516 if (!qspi->mm_size) 517 return -EOPNOTSUPP; 518 519 return 0; 520 } 521 522 static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc, 523 u64 offs, size_t len, void *buf) 524 { 525 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); 526 struct spi_mem_op op; 527 u32 addr_max; 528 int ret; 529 530 ret = pm_runtime_resume_and_get(qspi->dev); 531 if (ret < 0) 532 return ret; 533 534 mutex_lock(&qspi->lock); 535 /* make a local copy of desc op_tmpl and complete dirmap rdesc 536 * spi_mem_op template with offs, len and *buf in order to get 537 * all needed transfer information into struct spi_mem_op 538 */ 539 memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op)); 540 dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf); 541 542 op.data.nbytes = len; 543 op.addr.val = desc->info.offset + offs; 544 op.data.buf.in = buf; 545 546 addr_max = op.addr.val + op.data.nbytes + 1; 547 if (addr_max < qspi->mm_size && op.addr.buswidth) 548 qspi->fmode = CCR_FMODE_MM; 549 else 550 qspi->fmode = CCR_FMODE_INDR; 551 552 ret = stm32_qspi_send(desc->mem->spi, &op); 553 mutex_unlock(&qspi->lock); 554 555 pm_runtime_put_autosuspend(qspi->dev); 556 557 return ret ?: len; 558 } 559 560 static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl, 561 struct spi_message *msg) 562 { 563 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); 564 struct spi_transfer *transfer; 565 struct spi_device *spi = msg->spi; 566 struct spi_mem_op op; 567 int ret = 0; 568 569 if (!spi_get_csgpiod(spi, 0)) 570 return -EOPNOTSUPP; 571 572 ret = pm_runtime_resume_and_get(qspi->dev); 573 if (ret < 0) 574 return ret; 575 576 mutex_lock(&qspi->lock); 577 578 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true); 579 580 list_for_each_entry(transfer, &msg->transfers, transfer_list) { 581 u8 dummy_bytes = 0; 582 583 memset(&op, 0, sizeof(op)); 584 585 dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n", 586 transfer->tx_buf, transfer->tx_nbits, 587 transfer->rx_buf, transfer->rx_nbits, 588 transfer->len, transfer->dummy_data); 589 590 /* 591 * QSPI hardware supports dummy bytes transfer. 592 * If current transfer is dummy byte, merge it with the next 593 * transfer in order to take into account QSPI block constraint 594 */ 595 if (transfer->dummy_data) { 596 op.dummy.buswidth = transfer->tx_nbits; 597 op.dummy.nbytes = transfer->len; 598 dummy_bytes = transfer->len; 599 600 /* if happens, means that message is not correctly built */ 601 if (list_is_last(&transfer->transfer_list, &msg->transfers)) { 602 ret = -EINVAL; 603 goto end_of_transfer; 604 } 605 606 transfer = list_next_entry(transfer, transfer_list); 607 } 608 609 op.data.nbytes = transfer->len; 610 611 if (transfer->rx_buf) { 612 qspi->fmode = CCR_FMODE_INDR; 613 op.data.buswidth = transfer->rx_nbits; 614 op.data.dir = SPI_MEM_DATA_IN; 615 op.data.buf.in = transfer->rx_buf; 616 } else { 617 qspi->fmode = CCR_FMODE_INDW; 618 op.data.buswidth = transfer->tx_nbits; 619 op.data.dir = SPI_MEM_DATA_OUT; 620 op.data.buf.out = transfer->tx_buf; 621 } 622 623 ret = stm32_qspi_send(spi, &op); 624 if (ret) 625 goto end_of_transfer; 626 627 msg->actual_length += transfer->len + dummy_bytes; 628 } 629 630 end_of_transfer: 631 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false); 632 633 mutex_unlock(&qspi->lock); 634 635 msg->status = ret; 636 spi_finalize_current_message(ctrl); 637 638 pm_runtime_put_autosuspend(qspi->dev); 639 640 return ret; 641 } 642 643 static int stm32_qspi_setup(struct spi_device *spi) 644 { 645 struct spi_controller *ctrl = spi->controller; 646 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); 647 struct stm32_qspi_flash *flash; 648 u32 presc, mode; 649 int ret; 650 651 if (ctrl->busy) 652 return -EBUSY; 653 654 if (!spi->max_speed_hz) 655 return -EINVAL; 656 657 mode = spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL); 658 if (mode && gpiod_count(qspi->dev, "cs") == -ENOENT) { 659 dev_err(qspi->dev, "spi-rx-bus-width\\/spi-tx-bus-width\\/cs-gpios\n"); 660 dev_err(qspi->dev, "configuration not supported\n"); 661 662 return -EINVAL; 663 } 664 665 ret = pm_runtime_resume_and_get(qspi->dev); 666 if (ret < 0) 667 return ret; 668 669 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; 670 671 flash = &qspi->flash[spi_get_chipselect(spi, 0)]; 672 flash->cs = spi_get_chipselect(spi, 0); 673 flash->presc = presc; 674 675 mutex_lock(&qspi->lock); 676 qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN; 677 678 /* 679 * Dual flash mode is only enable in case SPI_TX_OCTAL or SPI_RX_OCTAL 680 * is set in spi->mode and "cs-gpios" properties is found in DT 681 */ 682 if (mode) { 683 qspi->cr_reg |= CR_DFM; 684 dev_dbg(qspi->dev, "Dual flash mode enable"); 685 } 686 687 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); 688 689 /* set dcr fsize to max address */ 690 qspi->dcr_reg = DCR_FSIZE_MASK; 691 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); 692 mutex_unlock(&qspi->lock); 693 694 pm_runtime_put_autosuspend(qspi->dev); 695 696 return 0; 697 } 698 699 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) 700 { 701 struct dma_slave_config dma_cfg; 702 struct device *dev = qspi->dev; 703 struct dma_slave_caps caps; 704 int ret = 0; 705 706 memset(&dma_cfg, 0, sizeof(dma_cfg)); 707 708 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 709 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 710 dma_cfg.src_addr = qspi->phys_base + QSPI_DR; 711 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR; 712 713 qspi->dma_chrx = dma_request_chan(dev, "rx"); 714 if (IS_ERR(qspi->dma_chrx)) { 715 ret = PTR_ERR(qspi->dma_chrx); 716 qspi->dma_chrx = NULL; 717 if (ret == -EPROBE_DEFER) 718 goto out; 719 } else { 720 ret = dma_get_slave_caps(qspi->dma_chrx, &caps); 721 if (ret) 722 return ret; 723 724 dma_cfg.src_maxburst = caps.max_burst / dma_cfg.src_addr_width; 725 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) { 726 dev_err(dev, "dma rx config failed\n"); 727 dma_release_channel(qspi->dma_chrx); 728 qspi->dma_chrx = NULL; 729 } 730 } 731 732 qspi->dma_chtx = dma_request_chan(dev, "tx"); 733 if (IS_ERR(qspi->dma_chtx)) { 734 ret = PTR_ERR(qspi->dma_chtx); 735 qspi->dma_chtx = NULL; 736 } else { 737 ret = dma_get_slave_caps(qspi->dma_chtx, &caps); 738 if (ret) 739 return ret; 740 741 dma_cfg.dst_maxburst = caps.max_burst / dma_cfg.dst_addr_width; 742 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) { 743 dev_err(dev, "dma tx config failed\n"); 744 dma_release_channel(qspi->dma_chtx); 745 qspi->dma_chtx = NULL; 746 } 747 } 748 749 out: 750 init_completion(&qspi->dma_completion); 751 752 if (ret != -EPROBE_DEFER) 753 ret = 0; 754 755 return ret; 756 } 757 758 static void stm32_qspi_dma_free(struct stm32_qspi *qspi) 759 { 760 if (qspi->dma_chtx) 761 dma_release_channel(qspi->dma_chtx); 762 if (qspi->dma_chrx) 763 dma_release_channel(qspi->dma_chrx); 764 } 765 766 /* 767 * no special host constraint, so use default spi_mem_default_supports_op 768 * to check supported mode. 769 */ 770 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = { 771 .exec_op = stm32_qspi_exec_op, 772 .dirmap_create = stm32_qspi_dirmap_create, 773 .dirmap_read = stm32_qspi_dirmap_read, 774 .poll_status = stm32_qspi_poll_status, 775 }; 776 777 static int stm32_qspi_probe(struct platform_device *pdev) 778 { 779 struct device *dev = &pdev->dev; 780 struct spi_controller *ctrl; 781 struct reset_control *rstc; 782 struct stm32_qspi *qspi; 783 struct resource *res; 784 int ret, irq; 785 786 ctrl = devm_spi_alloc_host(dev, sizeof(*qspi)); 787 if (!ctrl) 788 return -ENOMEM; 789 790 qspi = spi_controller_get_devdata(ctrl); 791 qspi->ctrl = ctrl; 792 793 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); 794 qspi->io_base = devm_ioremap_resource(dev, res); 795 if (IS_ERR(qspi->io_base)) 796 return PTR_ERR(qspi->io_base); 797 798 qspi->phys_base = res->start; 799 800 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); 801 qspi->mm_base = devm_ioremap_resource(dev, res); 802 if (IS_ERR(qspi->mm_base)) 803 return PTR_ERR(qspi->mm_base); 804 805 qspi->mm_size = resource_size(res); 806 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) 807 return -EINVAL; 808 809 irq = platform_get_irq(pdev, 0); 810 if (irq < 0) 811 return irq; 812 813 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, 814 dev_name(dev), qspi); 815 if (ret) { 816 dev_err(dev, "failed to request irq\n"); 817 return ret; 818 } 819 820 init_completion(&qspi->match_completion); 821 822 qspi->clk = devm_clk_get(dev, NULL); 823 if (IS_ERR(qspi->clk)) 824 return PTR_ERR(qspi->clk); 825 826 qspi->clk_rate = clk_get_rate(qspi->clk); 827 if (!qspi->clk_rate) 828 return -EINVAL; 829 830 ret = clk_prepare_enable(qspi->clk); 831 if (ret) { 832 dev_err(dev, "can not enable the clock\n"); 833 return ret; 834 } 835 836 rstc = devm_reset_control_get_exclusive(dev, NULL); 837 if (IS_ERR(rstc)) { 838 ret = PTR_ERR(rstc); 839 if (ret == -EPROBE_DEFER) 840 goto err_clk_disable; 841 } else { 842 reset_control_assert(rstc); 843 udelay(2); 844 reset_control_deassert(rstc); 845 } 846 847 qspi->dev = dev; 848 platform_set_drvdata(pdev, qspi); 849 ret = stm32_qspi_dma_setup(qspi); 850 if (ret) 851 goto err_dma_free; 852 853 mutex_init(&qspi->lock); 854 855 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL 856 | SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_OCTAL; 857 ctrl->setup = stm32_qspi_setup; 858 ctrl->bus_num = -1; 859 ctrl->mem_ops = &stm32_qspi_mem_ops; 860 ctrl->use_gpio_descriptors = true; 861 ctrl->transfer_one_message = stm32_qspi_transfer_one_message; 862 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; 863 864 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY); 865 pm_runtime_use_autosuspend(dev); 866 pm_runtime_set_active(dev); 867 pm_runtime_enable(dev); 868 pm_runtime_get_noresume(dev); 869 870 ret = spi_register_controller(ctrl); 871 if (ret) 872 goto err_pm_runtime_free; 873 874 pm_runtime_put_autosuspend(dev); 875 876 return 0; 877 878 err_pm_runtime_free: 879 pm_runtime_get_sync(qspi->dev); 880 /* disable qspi */ 881 writel_relaxed(0, qspi->io_base + QSPI_CR); 882 mutex_destroy(&qspi->lock); 883 pm_runtime_put_noidle(qspi->dev); 884 pm_runtime_disable(qspi->dev); 885 pm_runtime_set_suspended(qspi->dev); 886 pm_runtime_dont_use_autosuspend(qspi->dev); 887 err_dma_free: 888 stm32_qspi_dma_free(qspi); 889 err_clk_disable: 890 clk_disable_unprepare(qspi->clk); 891 892 return ret; 893 } 894 895 static void stm32_qspi_remove(struct platform_device *pdev) 896 { 897 struct stm32_qspi *qspi = platform_get_drvdata(pdev); 898 899 pm_runtime_get_sync(qspi->dev); 900 spi_unregister_controller(qspi->ctrl); 901 /* disable qspi */ 902 writel_relaxed(0, qspi->io_base + QSPI_CR); 903 stm32_qspi_dma_free(qspi); 904 mutex_destroy(&qspi->lock); 905 pm_runtime_put_noidle(qspi->dev); 906 pm_runtime_disable(qspi->dev); 907 pm_runtime_set_suspended(qspi->dev); 908 pm_runtime_dont_use_autosuspend(qspi->dev); 909 clk_disable_unprepare(qspi->clk); 910 } 911 912 static int stm32_qspi_runtime_suspend(struct device *dev) 913 { 914 struct stm32_qspi *qspi = dev_get_drvdata(dev); 915 916 clk_disable_unprepare(qspi->clk); 917 918 return 0; 919 } 920 921 static int stm32_qspi_runtime_resume(struct device *dev) 922 { 923 struct stm32_qspi *qspi = dev_get_drvdata(dev); 924 925 return clk_prepare_enable(qspi->clk); 926 } 927 928 static int stm32_qspi_suspend(struct device *dev) 929 { 930 pinctrl_pm_select_sleep_state(dev); 931 932 return pm_runtime_force_suspend(dev); 933 } 934 935 static int stm32_qspi_resume(struct device *dev) 936 { 937 struct stm32_qspi *qspi = dev_get_drvdata(dev); 938 int ret; 939 940 ret = pm_runtime_force_resume(dev); 941 if (ret < 0) 942 return ret; 943 944 pinctrl_pm_select_default_state(dev); 945 946 ret = pm_runtime_resume_and_get(dev); 947 if (ret < 0) 948 return ret; 949 950 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); 951 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); 952 953 pm_runtime_put_autosuspend(dev); 954 955 return 0; 956 } 957 958 static const struct dev_pm_ops stm32_qspi_pm_ops = { 959 RUNTIME_PM_OPS(stm32_qspi_runtime_suspend, stm32_qspi_runtime_resume, NULL) 960 SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume) 961 }; 962 963 static const struct of_device_id stm32_qspi_match[] = { 964 {.compatible = "st,stm32f469-qspi"}, 965 {} 966 }; 967 MODULE_DEVICE_TABLE(of, stm32_qspi_match); 968 969 static struct platform_driver stm32_qspi_driver = { 970 .probe = stm32_qspi_probe, 971 .remove = stm32_qspi_remove, 972 .driver = { 973 .name = "stm32-qspi", 974 .of_match_table = stm32_qspi_match, 975 .pm = pm_ptr(&stm32_qspi_pm_ops), 976 }, 977 }; 978 module_platform_driver(stm32_qspi_driver); 979 980 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>"); 981 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver"); 982 MODULE_LICENSE("GPL v2"); 983