1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2025 Arm Ltd. 4 * Based on arch/x86/kernel/cpu/resctrl/internal.h 5 */ 6 7 #ifndef __LINUX_RESCTRL_TYPES_H 8 #define __LINUX_RESCTRL_TYPES_H 9 10 #define MAX_MBA_BW 100u 11 #define MBM_OVERFLOW_INTERVAL 1000 12 13 /* Reads to Local DRAM Memory */ 14 #define READS_TO_LOCAL_MEM BIT(0) 15 16 /* Reads to Remote DRAM Memory */ 17 #define READS_TO_REMOTE_MEM BIT(1) 18 19 /* Non-Temporal Writes to Local Memory */ 20 #define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) 21 22 /* Non-Temporal Writes to Remote Memory */ 23 #define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) 24 25 /* Reads to Local Memory the system identifies as "Slow Memory" */ 26 #define READS_TO_LOCAL_S_MEM BIT(4) 27 28 /* Reads to Remote Memory the system identifies as "Slow Memory" */ 29 #define READS_TO_REMOTE_S_MEM BIT(5) 30 31 /* Dirty Victims to All Types of Memory */ 32 #define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) 33 34 /* Max event bits supported */ 35 #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) 36 37 /* Number of memory transactions that an MBM event can be configured with */ 38 #define NUM_MBM_TRANSACTIONS 7 39 40 /* Event IDs */ 41 enum resctrl_event_id { 42 /* Must match value of first event below */ 43 QOS_FIRST_EVENT = 0x01, 44 45 /* 46 * These values match those used to program IA32_QM_EVTSEL before 47 * reading IA32_QM_CTR on RDT systems. 48 */ 49 QOS_L3_OCCUP_EVENT_ID = 0x01, 50 QOS_L3_MBM_TOTAL_EVENT_ID = 0x02, 51 QOS_L3_MBM_LOCAL_EVENT_ID = 0x03, 52 53 /* Must be the last */ 54 QOS_NUM_EVENTS, 55 }; 56 57 #define QOS_NUM_L3_MBM_EVENTS (QOS_L3_MBM_LOCAL_EVENT_ID - QOS_L3_MBM_TOTAL_EVENT_ID + 1) 58 #define MBM_STATE_IDX(evt) ((evt) - QOS_L3_MBM_TOTAL_EVENT_ID) 59 60 #endif /* __LINUX_RESCTRL_TYPES_H */ 61