xref: /linux/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h (revision a3ebb59eee2e558e8f8f27fc3f75cd367f17cd8e)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2021 HiSilicon Ltd. */
3 
4 #ifndef HISI_ACC_VFIO_PCI_H
5 #define HISI_ACC_VFIO_PCI_H
6 
7 #include <linux/hisi_acc_qm.h>
8 
9 #define MB_POLL_PERIOD_US		10
10 #define MB_POLL_TIMEOUT_US		1000
11 #define QM_CACHE_WB_START		0x204
12 #define QM_CACHE_WB_DONE		0x208
13 #define QM_MB_CMD_PAUSE_QM		0xe
14 #define QM_ABNORMAL_INT_STATUS		0x100008
15 #define QM_IFC_INT_STATUS		0x0028
16 #define SEC_CORE_INT_STATUS		0x301008
17 #define HPRE_HAC_INT_STATUS		0x301800
18 #define HZIP_CORE_INT_STATUS		0x3010AC
19 
20 #define QM_VFT_CFG_RDY			0x10006c
21 #define QM_VFT_CFG_OP_WR		0x100058
22 #define QM_VFT_CFG_TYPE			0x10005c
23 #define QM_VFT_CFG			0x100060
24 #define QM_VFT_CFG_OP_ENABLE		0x100054
25 #define QM_VFT_CFG_DATA_L		0x100064
26 #define QM_VFT_CFG_DATA_H		0x100068
27 
28 #define ERROR_CHECK_TIMEOUT		100
29 #define CHECK_DELAY_TIME		100
30 
31 #define QM_SQC_VFT_BASE_SHIFT_V2	28
32 #define QM_SQC_VFT_BASE_MASK_V2		GENMASK(15, 0)
33 #define QM_SQC_VFT_NUM_SHIFT_V2		45
34 #define QM_SQC_VFT_NUM_MASK_V2		GENMASK(9, 0)
35 #define QM_MB_CMD_NOT_READY	0xffffffff
36 
37 /* RW regs */
38 #define QM_REGS_MAX_LEN		7
39 #define QM_REG_ADDR_OFFSET	0x0004
40 
41 #define QM_XQC_ADDR_OFFSET	32U
42 #define QM_XQC_ADDR_LOW	0x1
43 #define QM_XQC_ADDR_HIGH	0x2
44 
45 #define QM_VF_AEQ_INT_MASK	0x0004
46 #define QM_VF_EQ_INT_MASK	0x000c
47 #define QM_IFC_INT_SOURCE_V	0x0020
48 #define QM_IFC_INT_MASK		0x0024
49 #define QM_IFC_INT_SET_V	0x002c
50 #define QM_QUE_ISO_CFG_V	0x0030
51 #define QM_PAGE_SIZE		0x0034
52 
53 #define QM_EQC_VF_DW0		0X8000
54 #define QM_AEQC_VF_DW0		0X8020
55 #define QM_EQC_PF_DW0		0x1c00
56 #define QM_AEQC_PF_DW0		0x1c20
57 
58 #define ACC_DRV_MAJOR_VER 1
59 #define ACC_DRV_MINOR_VER 0
60 
61 #define ACC_DEV_MAGIC_V1	0XCDCDCDCDFEEDAACC
62 #define ACC_DEV_MAGIC_V2	0xAACCFEEDDECADEDE
63 
64 #define QM_MIG_REGION_OFFSET		0x180000
65 #define QM_MIG_REGION_SIZE		0x2000
66 
67 /**
68  * On HW_ACC_MIG_VF_CTRL mode, the configuration domain supporting live
69  * migration functionality is located in the latter 32KB of the VF's BAR2.
70  * The Guest is only provided with the first 32KB of the VF's BAR2.
71  * On HW_ACC_MIG_PF_CTRL mode, the configuration domain supporting live
72  * migration functionality is located in the PF's BAR2, and the entire 64KB
73  * of the VF's BAR2 is allocated to the Guest.
74  */
75 enum hw_drv_mode {
76 	HW_ACC_MIG_VF_CTRL = 0,
77 	HW_ACC_MIG_PF_CTRL,
78 };
79 
80 struct acc_vf_data {
81 #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
82 	/* QM match information */
83 	u64 acc_magic;
84 	u32 qp_num;
85 	u32 dev_id;
86 	u32 que_iso_cfg;
87 	u32 qp_base;
88 	u32 vf_qm_state;
89 	/* QM reserved match information */
90 	u16 major_ver;
91 	u16 minor_ver;
92 	u32 qm_rsv_state[2];
93 
94 	/* QM RW regs */
95 	u32 aeq_int_mask;
96 	u32 eq_int_mask;
97 	u32 ifc_int_source;
98 	u32 ifc_int_mask;
99 	u32 ifc_int_set;
100 	u32 page_size;
101 
102 	/* QM_EQC_DW has 7 regs */
103 	u32 qm_eqc_dw[7];
104 
105 	/* QM_AEQC_DW has 7 regs */
106 	u32 qm_aeqc_dw[7];
107 
108 	/* QM reserved 5 regs */
109 	u32 qm_rsv_regs[5];
110 	u32 padding;
111 	/* QM memory init information */
112 	u64 eqe_dma;
113 	u64 aeqe_dma;
114 	u64 sqc_dma;
115 	u64 cqc_dma;
116 };
117 
118 struct hisi_acc_vf_migration_file {
119 	struct file *filp;
120 	struct mutex lock;
121 	bool disabled;
122 
123 	struct hisi_acc_vf_core_device *hisi_acc_vdev;
124 	struct acc_vf_data vf_data;
125 	size_t total_length;
126 };
127 
128 struct hisi_acc_vf_core_device {
129 	struct vfio_pci_core_device core_device;
130 	u8 match_done;
131 	/*
132 	 * io_base is only valid when dev_opened is true,
133 	 * which is protected by open_mutex.
134 	 */
135 	bool dev_opened;
136 	/* Ensure the accuracy of dev_opened operation */
137 	struct mutex open_mutex;
138 
139 	/* For migration state */
140 	struct mutex state_mutex;
141 	enum vfio_device_mig_state mig_state;
142 	struct pci_dev *pf_dev;
143 	struct pci_dev *vf_dev;
144 	struct hisi_qm *pf_qm;
145 	struct hisi_qm vf_qm;
146 	enum hw_drv_mode drv_mode;
147 	/*
148 	 * vf_qm_state represents the QM_VF_STATE register value.
149 	 * It is set by Guest driver for the ACC VF dev indicating
150 	 * the driver has loaded and configured the dev correctly.
151 	 */
152 	u32 vf_qm_state;
153 	int vf_id;
154 	struct hisi_acc_vf_migration_file *resuming_migf;
155 	struct hisi_acc_vf_migration_file *saving_migf;
156 
157 	/*
158 	 * It holds migration data corresponding to the last migration
159 	 * and is used by the debugfs interface to report it.
160 	 */
161 	struct hisi_acc_vf_migration_file *debug_migf;
162 };
163 #endif /* HISI_ACC_VFIO_PCI_H */
164