xref: /linux/drivers/usb/mtu3/mtu3_hw_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
4  *
5  * Copyright (C) 2016 MediaTek Inc.
6  *
7  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8  */
9 
10 #ifndef _SSUSB_HW_REGS_H_
11 #define _SSUSB_HW_REGS_H_
12 
13 /* segment offset of MAC register */
14 #define SSUSB_DEV_BASE		0x0000
15 #define SSUSB_EPCTL_CSR_BASE	0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE	0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE	0x1400
18 #define SSUSB_USB2_CSR_BASE	0x2400
19 
20 /* IPPC register in Infra */
21 #define SSUSB_SIFSLV_IPPC_BASE	0x0000
22 
23 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
24 
25 #define U3D_LV1ISR		(SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER		(SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR		(SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR		(SSUSB_DEV_BASE + 0x000C)
29 
30 #define U3D_EPISR		(SSUSB_DEV_BASE + 0x0080)
31 #define U3D_EPIER		(SSUSB_DEV_BASE + 0x0084)
32 #define U3D_EPIESR		(SSUSB_DEV_BASE + 0x0088)
33 #define U3D_EPIECR		(SSUSB_DEV_BASE + 0x008C)
34 
35 #define U3D_EP0CSR		(SSUSB_DEV_BASE + 0x0100)
36 #define U3D_RXCOUNT0		(SSUSB_DEV_BASE + 0x0108)
37 #define U3D_RESERVED		(SSUSB_DEV_BASE + 0x010C)
38 #define U3D_TX1CSR0		(SSUSB_DEV_BASE + 0x0110)
39 #define U3D_TX1CSR1		(SSUSB_DEV_BASE + 0x0114)
40 #define U3D_TX1CSR2		(SSUSB_DEV_BASE + 0x0118)
41 
42 #define U3D_RX1CSR0		(SSUSB_DEV_BASE + 0x0210)
43 #define U3D_RX1CSR1		(SSUSB_DEV_BASE + 0x0214)
44 #define U3D_RX1CSR2		(SSUSB_DEV_BASE + 0x0218)
45 
46 #define U3D_FIFO0		(SSUSB_DEV_BASE + 0x0300)
47 
48 #define U3D_QCR0		(SSUSB_DEV_BASE + 0x0400)
49 #define U3D_QCR1		(SSUSB_DEV_BASE + 0x0404)
50 #define U3D_QCR2		(SSUSB_DEV_BASE + 0x0408)
51 #define U3D_QCR3		(SSUSB_DEV_BASE + 0x040C)
52 #define U3D_QFCR		(SSUSB_DEV_BASE + 0x0428)
53 #define U3D_TXQHIAR1		(SSUSB_DEV_BASE + 0x0484)
54 #define U3D_RXQHIAR1		(SSUSB_DEV_BASE + 0x04C4)
55 
56 #define U3D_TXQCSR1		(SSUSB_DEV_BASE + 0x0510)
57 #define U3D_TXQSAR1		(SSUSB_DEV_BASE + 0x0514)
58 #define U3D_TXQCPR1		(SSUSB_DEV_BASE + 0x0518)
59 
60 #define U3D_RXQCSR1		(SSUSB_DEV_BASE + 0x0610)
61 #define U3D_RXQSAR1		(SSUSB_DEV_BASE + 0x0614)
62 #define U3D_RXQCPR1		(SSUSB_DEV_BASE + 0x0618)
63 #define U3D_RXQLDPR1		(SSUSB_DEV_BASE + 0x061C)
64 
65 #define U3D_QISAR0		(SSUSB_DEV_BASE + 0x0700)
66 #define U3D_QIER0		(SSUSB_DEV_BASE + 0x0704)
67 #define U3D_QIESR0		(SSUSB_DEV_BASE + 0x0708)
68 #define U3D_QIECR0		(SSUSB_DEV_BASE + 0x070C)
69 #define U3D_QISAR1		(SSUSB_DEV_BASE + 0x0710)
70 #define U3D_QIER1		(SSUSB_DEV_BASE + 0x0714)
71 #define U3D_QIESR1		(SSUSB_DEV_BASE + 0x0718)
72 #define U3D_QIECR1		(SSUSB_DEV_BASE + 0x071C)
73 
74 #define U3D_TQERRIR0		(SSUSB_DEV_BASE + 0x0780)
75 #define U3D_TQERRIER0		(SSUSB_DEV_BASE + 0x0784)
76 #define U3D_TQERRIESR0		(SSUSB_DEV_BASE + 0x0788)
77 #define U3D_TQERRIECR0		(SSUSB_DEV_BASE + 0x078C)
78 #define U3D_RQERRIR0		(SSUSB_DEV_BASE + 0x07C0)
79 #define U3D_RQERRIER0		(SSUSB_DEV_BASE + 0x07C4)
80 #define U3D_RQERRIESR0		(SSUSB_DEV_BASE + 0x07C8)
81 #define U3D_RQERRIECR0		(SSUSB_DEV_BASE + 0x07CC)
82 #define U3D_RQERRIR1		(SSUSB_DEV_BASE + 0x07D0)
83 #define U3D_RQERRIER1		(SSUSB_DEV_BASE + 0x07D4)
84 #define U3D_RQERRIESR1		(SSUSB_DEV_BASE + 0x07D8)
85 #define U3D_RQERRIECR1		(SSUSB_DEV_BASE + 0x07DC)
86 
87 #define U3D_CAP_EP0FFSZ		(SSUSB_DEV_BASE + 0x0C04)
88 #define U3D_CAP_EPNTXFFSZ	(SSUSB_DEV_BASE + 0x0C08)
89 #define U3D_CAP_EPNRXFFSZ	(SSUSB_DEV_BASE + 0x0C0C)
90 #define U3D_CAP_EPINFO		(SSUSB_DEV_BASE + 0x0C10)
91 #define U3D_MISC_CTRL		(SSUSB_DEV_BASE + 0x0C84)
92 
93 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
94 
95 /* U3D_LV1ISR */
96 #define EP_CTRL_INTR		BIT(5)
97 #define MAC2_INTR		BIT(4)
98 #define DMA_INTR		BIT(3)
99 #define MAC3_INTR		BIT(2)
100 #define QMU_INTR		BIT(1)
101 #define BMU_INTR		BIT(0)
102 
103 /* U3D_LV1IECR */
104 #define LV1IECR_MSK		GENMASK(31, 0)
105 
106 /* U3D_EPISR */
107 #define EPRISR(x)		(BIT(16) << (x))
108 #define SETUPENDISR		BIT(16)
109 #define EPTISR(x)		(BIT(0) << (x))
110 #define EP0ISR			BIT(0)
111 
112 /* U3D_EP0CSR */
113 #define EP0_SENDSTALL		BIT(25)
114 #define EP0_FIFOFULL		BIT(23)
115 #define EP0_SENTSTALL		BIT(22)
116 #define EP0_DPHTX		BIT(20)
117 #define EP0_DATAEND		BIT(19)
118 #define EP0_TXPKTRDY		BIT(18)
119 #define EP0_SETUPPKTRDY		BIT(17)
120 #define EP0_RXPKTRDY		BIT(16)
121 #define EP0_MAXPKTSZ_MSK	GENMASK(9, 0)
122 #define EP0_MAXPKTSZ(x)		((x) & EP0_MAXPKTSZ_MSK)
123 #define EP0_W1C_BITS	(~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
124 
125 /* U3D_TX1CSR0 */
126 #define TX_DMAREQEN		BIT(29)
127 #define TX_FIFOFULL		BIT(25)
128 #define TX_FIFOEMPTY		BIT(24)
129 #define TX_SENTSTALL		BIT(22)
130 #define TX_SENDSTALL		BIT(21)
131 #define TX_FLUSHFIFO		BIT(20)
132 #define TX_TXPKTRDY		BIT(16)
133 #define TX_TXMAXPKTSZ_MSK	GENMASK(10, 0)
134 #define TX_TXMAXPKTSZ(x)	((x) & TX_TXMAXPKTSZ_MSK)
135 #define TX_W1C_BITS		(~(TX_SENTSTALL))
136 
137 /* U3D_TX1CSR1 */
138 #define TX_MAX_PKT_G2(x)	(((x) & 0xff) << 24)
139 #define TX_MULT_G2(x)		(((x) & 0x7) << 21)
140 #define TX_MULT_OG(x)		(((x) & 0x3) << 22)
141 #define TX_MAX_PKT_OG(x)	(((x) & 0x3f) << 16)
142 #define TX_SLOT(x)		(((x) & 0x3f) << 8)
143 #define TX_TYPE(x)		(((x) & 0x3) << 4)
144 #define TX_SS_BURST(x)		(((x) & 0xf) << 0)
145 #define TX_MULT(g2c, x)		\
146 ({				\
147 	typeof(x) x_ = (x);	\
148 	(g2c) ? TX_MULT_G2(x_) : TX_MULT_OG(x_);	\
149 })
150 #define TX_MAX_PKT(g2c, x)	\
151 ({				\
152 	typeof(x) x_ = (x);	\
153 	(g2c) ? TX_MAX_PKT_G2(x_) : TX_MAX_PKT_OG(x_);	\
154 })
155 
156 /* for TX_TYPE & RX_TYPE */
157 #define TYPE_BULK		(0x0)
158 #define TYPE_INT		(0x1)
159 #define TYPE_ISO		(0x2)
160 #define TYPE_MASK		(0x3)
161 
162 /* U3D_TX1CSR2 */
163 #define TX_BINTERVAL(x)		(((x) & 0xff) << 24)
164 #define TX_FIFOSEGSIZE(x)	(((x) & 0xf) << 16)
165 #define TX_FIFOADDR(x)		(((x) & 0x1fff) << 0)
166 
167 /* U3D_RX1CSR0 */
168 #define RX_DMAREQEN		BIT(29)
169 #define RX_SENTSTALL		BIT(22)
170 #define RX_SENDSTALL		BIT(21)
171 #define RX_RXPKTRDY		BIT(16)
172 #define RX_RXMAXPKTSZ_MSK	GENMASK(10, 0)
173 #define RX_RXMAXPKTSZ(x)	((x) & RX_RXMAXPKTSZ_MSK)
174 #define RX_W1C_BITS		(~(RX_SENTSTALL | RX_RXPKTRDY))
175 
176 /* U3D_RX1CSR1 */
177 #define RX_MAX_PKT_G2(x)	(((x) & 0xff) << 24)
178 #define RX_MULT_G2(x)		(((x) & 0x7) << 21)
179 #define RX_MULT_OG(x)		(((x) & 0x3) << 22)
180 #define RX_MAX_PKT_OG(x)	(((x) & 0x3f) << 16)
181 #define RX_SLOT(x)		(((x) & 0x3f) << 8)
182 #define RX_TYPE(x)		(((x) & 0x3) << 4)
183 #define RX_SS_BURST(x)		(((x) & 0xf) << 0)
184 #define RX_MULT(g2c, x)		\
185 ({				\
186 	typeof(x) x_ = (x);	\
187 	(g2c) ? RX_MULT_G2(x_) : RX_MULT_OG(x_);	\
188 })
189 #define RX_MAX_PKT(g2c, x)	\
190 ({				\
191 	typeof(x) x_ = (x);	\
192 	(g2c) ? RX_MAX_PKT_G2(x_) : RX_MAX_PKT_OG(x_);	\
193 })
194 
195 /* U3D_RX1CSR2 */
196 #define RX_BINTERVAL(x)		(((x) & 0xff) << 24)
197 #define RX_FIFOSEGSIZE(x)	(((x) & 0xf) << 16)
198 #define RX_FIFOADDR(x)		(((x) & 0x1fff) << 0)
199 
200 /* U3D_QCR0 */
201 #define QMU_RX_CS_EN(x)		(BIT(16) << (x))
202 #define QMU_TX_CS_EN(x)		(BIT(0) << (x))
203 #define QMU_CS16B_EN		BIT(0)
204 
205 /* U3D_QCR1 */
206 #define QMU_TX_ZLP(x)		(BIT(0) << (x))
207 
208 /* U3D_QCR3 */
209 #define QMU_RX_COZ(x)		(BIT(16) << (x))
210 #define QMU_RX_ZLP(x)		(BIT(0) << (x))
211 
212 /* U3D_TXQHIAR1 */
213 /* U3D_RXQHIAR1 */
214 #define QMU_LAST_DONE_PTR_HI(x)	(((x) >> 16) & 0xf)
215 #define QMU_CUR_GPD_ADDR_HI(x)	(((x) >> 8) & 0xf)
216 #define QMU_START_ADDR_HI_MSK	GENMASK(3, 0)
217 #define QMU_START_ADDR_HI(x)	(((x) & 0xf) << 0)
218 
219 /* U3D_TXQCSR1 */
220 /* U3D_RXQCSR1 */
221 #define QMU_Q_ACTIVE		BIT(15)
222 #define QMU_Q_STOP		BIT(2)
223 #define QMU_Q_RESUME		BIT(1)
224 #define QMU_Q_START		BIT(0)
225 
226 /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
227 #define QMU_RX_DONE_INT(x)	(BIT(16) << (x))
228 #define QMU_TX_DONE_INT(x)	(BIT(0) << (x))
229 
230 /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
231 #define RXQ_ZLPERR_INT		BIT(20)
232 #define RXQ_LENERR_INT		BIT(18)
233 #define RXQ_CSERR_INT		BIT(17)
234 #define RXQ_EMPTY_INT		BIT(16)
235 #define TXQ_LENERR_INT		BIT(2)
236 #define TXQ_CSERR_INT		BIT(1)
237 #define TXQ_EMPTY_INT		BIT(0)
238 
239 /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
240 #define QMU_TX_LEN_ERR(x)	(BIT(16) << (x))
241 #define QMU_TX_CS_ERR(x)	(BIT(0) << (x))
242 
243 /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
244 #define QMU_RX_LEN_ERR(x)	(BIT(16) << (x))
245 #define QMU_RX_CS_ERR(x)	(BIT(0) << (x))
246 
247 /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
248 #define QMU_RX_ZLP_ERR(n)	(BIT(16) << (n))
249 
250 /* U3D_CAP_EPINFO */
251 #define CAP_RX_EP_NUM(x)	(((x) >> 8) & 0x1f)
252 #define CAP_TX_EP_NUM(x)	((x) & 0x1f)
253 
254 /* U3D_MISC_CTRL */
255 #define DMA_ADDR_36BIT		BIT(31)
256 #define VBUS_ON			BIT(1)
257 #define VBUS_FRC_EN		BIT(0)
258 
259 
260 /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
261 
262 #define U3D_DEVICE_CONF			(SSUSB_EPCTL_CSR_BASE + 0x0000)
263 #define U3D_EP_RST			(SSUSB_EPCTL_CSR_BASE + 0x0004)
264 
265 #define U3D_DEV_LINK_INTR_ENABLE	(SSUSB_EPCTL_CSR_BASE + 0x0050)
266 #define U3D_DEV_LINK_INTR		(SSUSB_EPCTL_CSR_BASE + 0x0054)
267 
268 /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
269 
270 /* U3D_DEVICE_CONF */
271 #define DEV_ADDR_MSK		GENMASK(30, 24)
272 #define DEV_ADDR(x)		((0x7f & (x)) << 24)
273 #define HW_USB2_3_SEL		BIT(18)
274 #define SW_USB2_3_SEL_EN	BIT(17)
275 #define SW_USB2_3_SEL		BIT(16)
276 #define SSUSB_DEV_SPEED(x)	((x) & 0x7)
277 
278 /* U3D_EP_RST */
279 #define EP1_IN_RST		BIT(17)
280 #define EP1_OUT_RST		BIT(1)
281 #define EP_RST(is_in, epnum)	(((is_in) ? BIT(16) : BIT(0)) << (epnum))
282 #define EP0_RST			BIT(0)
283 
284 /* U3D_DEV_LINK_INTR_ENABLE */
285 /* U3D_DEV_LINK_INTR */
286 #define SSUSB_DEV_SPEED_CHG_INTR	BIT(0)
287 
288 
289 /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
290 
291 #define U3D_LTSSM_CTRL		(SSUSB_USB3_MAC_CSR_BASE + 0x0010)
292 #define U3D_USB3_CONFIG		(SSUSB_USB3_MAC_CSR_BASE + 0x001C)
293 
294 #define U3D_LINK_STATE_MACHINE	(SSUSB_USB3_MAC_CSR_BASE + 0x0134)
295 #define U3D_LTSSM_INTR_ENABLE	(SSUSB_USB3_MAC_CSR_BASE + 0x013C)
296 #define U3D_LTSSM_INTR		(SSUSB_USB3_MAC_CSR_BASE + 0x0140)
297 
298 #define U3D_U3U2_SWITCH_CTRL	(SSUSB_USB3_MAC_CSR_BASE + 0x0170)
299 
300 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
301 
302 /* U3D_LTSSM_CTRL */
303 #define FORCE_POLLING_FAIL	BIT(4)
304 #define FORCE_RXDETECT_FAIL	BIT(3)
305 #define SOFT_U3_EXIT_EN		BIT(2)
306 #define COMPLIANCE_EN		BIT(1)
307 #define U1_GO_U2_EN		BIT(0)
308 
309 /* U3D_USB3_CONFIG */
310 #define USB3_EN			BIT(0)
311 
312 /* U3D_LINK_STATE_MACHINE */
313 #define LTSSM_STATE(x)	((x) & 0x1f)
314 
315 /* U3D_LTSSM_INTR_ENABLE */
316 /* U3D_LTSSM_INTR */
317 #define U3_RESUME_INTR		BIT(18)
318 #define U3_LFPS_TMOUT_INTR	BIT(17)
319 #define VBUS_FALL_INTR		BIT(16)
320 #define VBUS_RISE_INTR		BIT(15)
321 #define RXDET_SUCCESS_INTR	BIT(14)
322 #define EXIT_U3_INTR		BIT(13)
323 #define EXIT_U2_INTR		BIT(12)
324 #define EXIT_U1_INTR		BIT(11)
325 #define ENTER_U3_INTR		BIT(10)
326 #define ENTER_U2_INTR		BIT(9)
327 #define ENTER_U1_INTR		BIT(8)
328 #define ENTER_U0_INTR		BIT(7)
329 #define RECOVERY_INTR		BIT(6)
330 #define WARM_RST_INTR		BIT(5)
331 #define HOT_RST_INTR		BIT(4)
332 #define LOOPBACK_INTR		BIT(3)
333 #define COMPLIANCE_INTR		BIT(2)
334 #define SS_DISABLE_INTR		BIT(1)
335 #define SS_INACTIVE_INTR	BIT(0)
336 
337 /* U3D_U3U2_SWITCH_CTRL */
338 #define SOFTCON_CLR_AUTO_EN	BIT(0)
339 
340 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
341 
342 #define U3D_LINK_UX_INACT_TIMER	(SSUSB_USB3_SYS_CSR_BASE + 0x020C)
343 #define U3D_LINK_POWER_CONTROL	(SSUSB_USB3_SYS_CSR_BASE + 0x0210)
344 #define U3D_LINK_ERR_COUNT	(SSUSB_USB3_SYS_CSR_BASE + 0x0214)
345 #define U3D_DEV_NOTIF_0		(SSUSB_USB3_SYS_CSR_BASE + 0x0290)
346 #define U3D_DEV_NOTIF_1		(SSUSB_USB3_SYS_CSR_BASE + 0x0294)
347 
348 /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
349 
350 /* U3D_LINK_UX_INACT_TIMER */
351 #define DEV_U2_INACT_TIMEOUT_MSK	GENMASK(23, 16)
352 #define DEV_U2_INACT_TIMEOUT_VALUE(x)	(((x) & 0xff) << 16)
353 #define U2_INACT_TIMEOUT_MSK		GENMASK(15, 8)
354 #define U1_INACT_TIMEOUT_MSK		GENMASK(7, 0)
355 #define U1_INACT_TIMEOUT_VALUE(x)	((x) & 0xff)
356 
357 /* U3D_LINK_POWER_CONTROL */
358 #define SW_U2_ACCEPT_ENABLE	BIT(9)
359 #define SW_U1_ACCEPT_ENABLE	BIT(8)
360 #define UX_EXIT			BIT(5)
361 #define LGO_U3			BIT(4)
362 #define LGO_U2			BIT(3)
363 #define LGO_U1			BIT(2)
364 #define SW_U2_REQUEST_ENABLE	BIT(1)
365 #define SW_U1_REQUEST_ENABLE	BIT(0)
366 
367 /* U3D_LINK_ERR_COUNT */
368 #define CLR_LINK_ERR_CNT	BIT(16)
369 #define LINK_ERROR_COUNT	GENMASK(15, 0)
370 
371 /* U3D_DEV_NOTIF_0 */
372 #define DEV_NOTIF_TYPE_SPECIFIC_LOW_MSK		GENMASK(31, 8)
373 #define DEV_NOTIF_VAL_FW(x)		(((x) & 0xff) << 8)
374 #define DEV_NOTIF_VAL_LTM(x)	(((x) & 0xfff) << 8)
375 #define DEV_NOTIF_VAL_IAM(x)	(((x) & 0xffff) << 8)
376 #define DEV_NOTIF_TYPE_MSK		GENMASK(7, 4)
377 /* Notification Type */
378 #define TYPE_FUNCTION_WAKE			(0x1 << 4)
379 #define TYPE_LATENCY_TOLERANCE_MESSAGE		(0x2 << 4)
380 #define TYPE_BUS_INTERVAL_ADJUST_MESSAGE	(0x3 << 4)
381 #define TYPE_HOST_ROLE_REQUEST			(0x4 << 4)
382 #define TYPE_SUBLINK_SPEED			(0x5 << 4)
383 #define SEND_DEV_NOTIF			BIT(0)
384 
385 /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
386 
387 #define U3D_POWER_MANAGEMENT		(SSUSB_USB2_CSR_BASE + 0x0004)
388 #define U3D_DEVICE_CONTROL		(SSUSB_USB2_CSR_BASE + 0x000C)
389 #define U3D_USB2_TEST_MODE		(SSUSB_USB2_CSR_BASE + 0x0014)
390 #define U3D_COMMON_USB_INTR_ENABLE	(SSUSB_USB2_CSR_BASE + 0x0018)
391 #define U3D_COMMON_USB_INTR		(SSUSB_USB2_CSR_BASE + 0x001C)
392 #define U3D_LINK_RESET_INFO		(SSUSB_USB2_CSR_BASE + 0x0024)
393 #define U3D_USB20_FRAME_NUM		(SSUSB_USB2_CSR_BASE + 0x003C)
394 #define U3D_USB20_LPM_PARAMETER		(SSUSB_USB2_CSR_BASE + 0x0044)
395 #define U3D_USB20_MISC_CONTROL		(SSUSB_USB2_CSR_BASE + 0x004C)
396 #define U3D_USB20_OPSTATE		(SSUSB_USB2_CSR_BASE + 0x0060)
397 
398 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
399 
400 /* U3D_POWER_MANAGEMENT */
401 #define LPM_BESL_STALL		BIT(14)
402 #define LPM_BESLD_STALL		BIT(13)
403 #define LPM_RWP			BIT(11)
404 #define LPM_HRWE		BIT(10)
405 #define LPM_MODE(x)		(((x) & 0x3) << 8)
406 #define ISO_UPDATE		BIT(7)
407 #define SOFT_CONN		BIT(6)
408 #define HS_ENABLE		BIT(5)
409 #define RESUME			BIT(2)
410 #define SUSPENDM_ENABLE		BIT(0)
411 
412 /* U3D_DEVICE_CONTROL */
413 #define DC_HOSTREQ		BIT(1)
414 #define DC_SESSION		BIT(0)
415 
416 /* U3D_USB2_TEST_MODE */
417 #define U2U3_AUTO_SWITCH	BIT(10)
418 #define LPM_FORCE_STALL		BIT(8)
419 #define FIFO_ACCESS		BIT(6)
420 #define FORCE_FS		BIT(5)
421 #define FORCE_HS		BIT(4)
422 #define TEST_PACKET_MODE	BIT(3)
423 #define TEST_K_MODE		BIT(2)
424 #define TEST_J_MODE		BIT(1)
425 #define TEST_SE0_NAK_MODE	BIT(0)
426 
427 /* U3D_COMMON_USB_INTR_ENABLE */
428 /* U3D_COMMON_USB_INTR */
429 #define LPM_RESUME_INTR		BIT(9)
430 #define LPM_INTR		BIT(8)
431 #define DISCONN_INTR		BIT(5)
432 #define CONN_INTR		BIT(4)
433 #define SOF_INTR		BIT(3)
434 #define RESET_INTR		BIT(2)
435 #define RESUME_INTR		BIT(1)
436 #define SUSPEND_INTR		BIT(0)
437 
438 /* U3D_LINK_RESET_INFO */
439 #define WTCHRP_MSK		GENMASK(19, 16)
440 
441 /* U3D_USB20_LPM_PARAMETER */
442 #define LPM_BESLCK_U3(x)	(((x) & 0xf) << 12)
443 #define LPM_BESLCK(x)		(((x) & 0xf) << 8)
444 #define LPM_BESLDCK(x)		(((x) & 0xf) << 4)
445 #define LPM_BESL		GENMASK(3, 0)
446 
447 /* U3D_USB20_MISC_CONTROL */
448 #define LPM_U3_ACK_EN		BIT(0)
449 
450 /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
451 
452 #define U3D_SSUSB_IP_PW_CTRL0	(SSUSB_SIFSLV_IPPC_BASE + 0x0000)
453 #define U3D_SSUSB_IP_PW_CTRL1	(SSUSB_SIFSLV_IPPC_BASE + 0x0004)
454 #define U3D_SSUSB_IP_PW_CTRL2	(SSUSB_SIFSLV_IPPC_BASE + 0x0008)
455 #define U3D_SSUSB_IP_PW_CTRL3	(SSUSB_SIFSLV_IPPC_BASE + 0x000C)
456 #define U3D_SSUSB_IP_PW_STS1	(SSUSB_SIFSLV_IPPC_BASE + 0x0010)
457 #define U3D_SSUSB_IP_PW_STS2	(SSUSB_SIFSLV_IPPC_BASE + 0x0014)
458 #define U3D_SSUSB_OTG_STS	(SSUSB_SIFSLV_IPPC_BASE + 0x0018)
459 #define U3D_SSUSB_OTG_STS_CLR	(SSUSB_SIFSLV_IPPC_BASE + 0x001C)
460 #define U3D_SSUSB_IP_XHCI_CAP	(SSUSB_SIFSLV_IPPC_BASE + 0x0024)
461 #define U3D_SSUSB_IP_DEV_CAP	(SSUSB_SIFSLV_IPPC_BASE + 0x0028)
462 #define U3D_SSUSB_OTG_INT_EN	(SSUSB_SIFSLV_IPPC_BASE + 0x002C)
463 #define U3D_SSUSB_U3_CTRL_0P	(SSUSB_SIFSLV_IPPC_BASE + 0x0030)
464 #define U3D_SSUSB_U2_CTRL_0P	(SSUSB_SIFSLV_IPPC_BASE + 0x0050)
465 #define U3D_SSUSB_REF_CK_CTRL	(SSUSB_SIFSLV_IPPC_BASE + 0x008C)
466 #define U3D_SSUSB_DEV_RST_CTRL	(SSUSB_SIFSLV_IPPC_BASE + 0x0098)
467 #define U3D_SSUSB_HW_ID		(SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
468 #define U3D_SSUSB_HW_SUB_ID	(SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
469 #define U3D_SSUSB_IP_TRUNK_VERS	(U3D_SSUSB_HW_SUB_ID)
470 #define U3D_SSUSB_PRB_CTRL0	(SSUSB_SIFSLV_IPPC_BASE + 0x00B0)
471 #define U3D_SSUSB_PRB_CTRL1	(SSUSB_SIFSLV_IPPC_BASE + 0x00B4)
472 #define U3D_SSUSB_PRB_CTRL2	(SSUSB_SIFSLV_IPPC_BASE + 0x00B8)
473 #define U3D_SSUSB_PRB_CTRL3	(SSUSB_SIFSLV_IPPC_BASE + 0x00BC)
474 #define U3D_SSUSB_PRB_CTRL4	(SSUSB_SIFSLV_IPPC_BASE + 0x00C0)
475 #define U3D_SSUSB_PRB_CTRL5	(SSUSB_SIFSLV_IPPC_BASE + 0x00C4)
476 #define U3D_SSUSB_IP_SPARE0	(SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
477 
478 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
479 
480 /* U3D_SSUSB_IP_PW_CTRL0 */
481 #define SSUSB_IP_SW_RST			BIT(0)
482 
483 /* U3D_SSUSB_IP_PW_CTRL1 */
484 #define SSUSB_IP_HOST_PDN		BIT(0)
485 
486 /* U3D_SSUSB_IP_PW_CTRL2 */
487 #define SSUSB_IP_DEV_PDN		BIT(0)
488 
489 /* U3D_SSUSB_IP_PW_CTRL3 */
490 #define SSUSB_IP_PCIE_PDN		BIT(0)
491 
492 /* U3D_SSUSB_IP_PW_STS1 */
493 #define SSUSB_IP_SLEEP_STS		BIT(30)
494 #define SSUSB_U3_MAC_RST_B_STS		BIT(16)
495 #define SSUSB_XHCI_RST_B_STS		BIT(11)
496 #define SSUSB_SYS125_RST_B_STS		BIT(10)
497 #define SSUSB_REF_RST_B_STS		BIT(8)
498 #define SSUSB_SYSPLL_STABLE		BIT(0)
499 
500 /* U3D_SSUSB_IP_PW_STS2 */
501 #define SSUSB_U2_MAC_SYS_RST_B_STS	BIT(0)
502 
503 /* U3D_SSUSB_OTG_STS */
504 #define SSUSB_VBUS_VALID		BIT(9)
505 
506 /* U3D_SSUSB_OTG_STS_CLR */
507 #define SSUSB_VBUS_INTR_CLR		BIT(6)
508 
509 /* U3D_SSUSB_IP_XHCI_CAP */
510 #define SSUSB_IP_XHCI_U2_PORT_NUM(x)	(((x) >> 8) & 0xff)
511 #define SSUSB_IP_XHCI_U3_PORT_NUM(x)	((x) & 0xff)
512 
513 /* U3D_SSUSB_IP_DEV_CAP */
514 #define SSUSB_IP_DEV_U3_PORT_NUM(x)	((x) & 0xff)
515 
516 /* U3D_SSUSB_OTG_INT_EN */
517 #define SSUSB_VBUS_CHG_INT_A_EN		BIT(7)
518 #define SSUSB_VBUS_CHG_INT_B_EN		BIT(6)
519 
520 /* U3D_SSUSB_U3_CTRL_0P */
521 #define SSUSB_U3_PORT_SSP_SPEED	BIT(9)
522 #define SSUSB_U3_PORT_DUAL_MODE	BIT(7)
523 #define SSUSB_U3_PORT_HOST_SEL		BIT(2)
524 #define SSUSB_U3_PORT_PDN		BIT(1)
525 #define SSUSB_U3_PORT_DIS		BIT(0)
526 
527 /* U3D_SSUSB_U2_CTRL_0P */
528 #define SSUSB_U2_PORT_RG_IDDIG		BIT(12)
529 #define SSUSB_U2_PORT_FORCE_IDDIG	BIT(11)
530 #define SSUSB_U2_PORT_VBUSVALID	BIT(9)
531 #define SSUSB_U2_PORT_OTG_SEL		BIT(7)
532 #define SSUSB_U2_PORT_HOST		BIT(2)
533 #define SSUSB_U2_PORT_PDN		BIT(1)
534 #define SSUSB_U2_PORT_DIS		BIT(0)
535 #define SSUSB_U2_PORT_HOST_SEL	(SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
536 
537 /* U3D_SSUSB_DEV_RST_CTRL */
538 #define SSUSB_DEV_SW_RST		BIT(0)
539 
540 /* U3D_SSUSB_IP_TRUNK_VERS */
541 #define IP_TRUNK_VERS(x)		(((x) >> 16) & 0xffff)
542 
543 #endif	/* _SSUSB_HW_REGS_H_ */
544