1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic qlcnic NIC Driver 4 * Copyright (c) 2009-2013 QLogic Corporation 5 */ 6 7 #ifndef __QLCNIC_83XX_HW_H 8 #define __QLCNIC_83XX_HW_H 9 10 #include <linux/types.h> 11 #include <linux/etherdevice.h> 12 13 #include "qlcnic_hw.h" 14 15 #define QLCNIC_83XX_BAR0_LENGTH 0x4000 16 17 /* Directly mapped registers */ 18 #define QLC_83XX_CRB_WIN_BASE 0x3800 19 #define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) 20 #define QLC_83XX_SEM_LOCK_BASE 0x3840 21 #define QLC_83XX_SEM_UNLOCK_BASE 0x3844 22 #define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) 23 #define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) 24 #define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 25 #define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 26 #define QLC_83XX_LINK_SPEED_FACTOR 10 27 #define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) 28 #define QLC_83XX_INTX_PTR 0x38C0 29 #define QLC_83XX_INTX_TRGR 0x38C4 30 #define QLC_83XX_INTX_MASK 0x38C8 31 32 #define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 33 #define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 34 #define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 35 #define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 36 #define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 37 #define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 38 #define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 39 #define QLC_83XX_LB_WAIT_COUNT 250 40 #define QLC_83XX_LB_MSLEEP_COUNT 20 41 #define QLC_83XX_NO_NIC_RESOURCE 0x5 42 #define QLC_83XX_MAC_PRESENT 0xC 43 #define QLC_83XX_MAC_ABSENT 0xD 44 45 46 #define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) 47 48 /* PEG status definitions */ 49 #define QLC_83XX_CMDPEG_COMPLETE 0xff01 50 #define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) 51 #define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) 52 #define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) 53 #define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 54 #define QLC_83XX_LEGACY_INTX_DELAY 4 55 #define QLC_83XX_REG_DESC 1 56 #define QLC_83XX_LRO_DESC 2 57 #define QLC_83XX_CTRL_DESC 3 58 #define QLC_83XX_FW_CAPABILITY_TSO BIT_6 59 #define QLC_83XX_FW_CAP_LRO_MSS BIT_17 60 #define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 61 #define QLC_83XX_HOST_SDS_MBX_IDX 8 62 63 #define QLCNIC_HOST_RDS_MBX_IDX 88 64 65 /* Pause control registers */ 66 #define QLC_83XX_SRE_SHIM_REG 0x0D200284 67 #define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 68 #define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 69 #define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 70 #define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 71 #define QLC_83XX_PORT0_TC_STATS 0x0B20039C 72 #define QLC_83XX_PORT1_TC_STATS 0x0B20139C 73 #define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 74 #define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 75 76 /* Peg PC status registers */ 77 #define QLC_83XX_CRB_PEG_NET_0 0x3400003c 78 #define QLC_83XX_CRB_PEG_NET_1 0x3410003c 79 #define QLC_83XX_CRB_PEG_NET_2 0x3420003c 80 #define QLC_83XX_CRB_PEG_NET_3 0x3430003c 81 #define QLC_83XX_CRB_PEG_NET_4 0x34b0003c 82 83 /* Firmware image definitions */ 84 #define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 85 #define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" 86 #define QLC_83XX_POST_FW_FILE_NAME "83xx_post_fw.bin" 87 #define QLC_84XX_FW_FILE_NAME "84xx_fw.bin" 88 #define QLC_83XX_BOOT_FROM_FLASH 0 89 #define QLC_83XX_BOOT_FROM_FILE 0x12345678 90 91 #define QLC_FW_FILE_NAME_LEN 20 92 #define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16 93 94 #define QLC_83XX_MBX_POST_BC_OP 0x1 95 #define QLC_83XX_MBX_COMPLETION 0x0 96 #define QLC_83XX_MBX_REQUEST 0x1 97 98 #define QLC_83XX_MBX_TIMEOUT (5 * HZ) 99 #define QLC_83XX_MBX_CMD_LOOP 5000000 100 101 /* status descriptor mailbox data 102 * @phy_addr_{low|high}: physical address of buffer 103 * @sds_ring_size: buffer size 104 * @intrpt_id: interrupt id 105 * @intrpt_val: source of interrupt 106 */ 107 struct qlcnic_sds_mbx { 108 u32 phy_addr_low; 109 u32 phy_addr_high; 110 u32 rsvd1[4]; 111 #if defined(__LITTLE_ENDIAN) 112 u16 sds_ring_size; 113 u16 rsvd2; 114 u16 rsvd3[2]; 115 u16 intrpt_id; 116 u8 intrpt_val; 117 u8 rsvd4; 118 #elif defined(__BIG_ENDIAN) 119 u16 rsvd2; 120 u16 sds_ring_size; 121 u16 rsvd3[2]; 122 u8 rsvd4; 123 u8 intrpt_val; 124 u16 intrpt_id; 125 #endif 126 u32 rsvd5; 127 } __packed; 128 129 /* receive descriptor buffer data 130 * phy_addr_reg_{low|high}: physical address of regular buffer 131 * phy_addr_jmb_{low|high}: physical address of jumbo buffer 132 * reg_ring_sz: size of regular buffer 133 * reg_ring_len: no. of entries in regular buffer 134 * jmb_ring_len: no. of entries in jumbo buffer 135 * jmb_ring_sz: size of jumbo buffer 136 */ 137 struct qlcnic_rds_mbx { 138 u32 phy_addr_reg_low; 139 u32 phy_addr_reg_high; 140 u32 phy_addr_jmb_low; 141 u32 phy_addr_jmb_high; 142 #if defined(__LITTLE_ENDIAN) 143 u16 reg_ring_sz; 144 u16 reg_ring_len; 145 u16 jmb_ring_sz; 146 u16 jmb_ring_len; 147 #elif defined(__BIG_ENDIAN) 148 u16 reg_ring_len; 149 u16 reg_ring_sz; 150 u16 jmb_ring_len; 151 u16 jmb_ring_sz; 152 #endif 153 } __packed; 154 155 /* host producers for regular and jumbo rings */ 156 struct __host_producer_mbx { 157 u32 reg_buf; 158 u32 jmb_buf; 159 } __packed; 160 161 /* Receive context mailbox data outbox registers 162 * @state: state of the context 163 * @vport_id: virtual port id 164 * @context_id: receive context id 165 * @num_pci_func: number of pci functions of the port 166 * @phy_port: physical port id 167 */ 168 struct qlcnic_rcv_mbx_out { 169 #if defined(__LITTLE_ENDIAN) 170 u8 rcv_num; 171 u8 sts_num; 172 u16 ctx_id; 173 u8 state; 174 u8 num_pci_func; 175 u8 phy_port; 176 u8 vport_id; 177 #elif defined(__BIG_ENDIAN) 178 u16 ctx_id; 179 u8 sts_num; 180 u8 rcv_num; 181 u8 vport_id; 182 u8 phy_port; 183 u8 num_pci_func; 184 u8 state; 185 #endif 186 u32 host_csmr[QLCNIC_MAX_SDS_RINGS]; 187 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS]; 188 } __packed; 189 190 struct qlcnic_add_rings_mbx_out { 191 #if defined(__LITTLE_ENDIAN) 192 u8 rcv_num; 193 u8 sts_num; 194 u16 ctx_id; 195 #elif defined(__BIG_ENDIAN) 196 u16 ctx_id; 197 u8 sts_num; 198 u8 rcv_num; 199 #endif 200 u32 host_csmr[QLCNIC_MAX_SDS_RINGS]; 201 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS]; 202 } __packed; 203 204 /* Transmit context mailbox inbox registers 205 * @phys_addr_{low|high}: DMA address of the transmit buffer 206 * @cnsmr_index_{low|high}: host consumer index 207 * @size: legth of transmit buffer ring 208 * @intr_id: interrupt id 209 * @src: src of interrupt 210 */ 211 struct qlcnic_tx_mbx { 212 u32 phys_addr_low; 213 u32 phys_addr_high; 214 u32 cnsmr_index_low; 215 u32 cnsmr_index_high; 216 #if defined(__LITTLE_ENDIAN) 217 u16 size; 218 u16 intr_id; 219 u8 src; 220 u8 rsvd[3]; 221 #elif defined(__BIG_ENDIAN) 222 u16 intr_id; 223 u16 size; 224 u8 rsvd[3]; 225 u8 src; 226 #endif 227 } __packed; 228 229 /* Transmit context mailbox outbox registers 230 * @host_prod: host producer index 231 * @ctx_id: transmit context id 232 * @state: state of the transmit context 233 */ 234 235 struct qlcnic_tx_mbx_out { 236 u32 host_prod; 237 #if defined(__LITTLE_ENDIAN) 238 u16 ctx_id; 239 u8 state; 240 u8 rsvd; 241 #elif defined(__BIG_ENDIAN) 242 u8 rsvd; 243 u8 state; 244 u16 ctx_id; 245 #endif 246 } __packed; 247 248 struct qlcnic_intrpt_config { 249 u8 type; 250 u8 enabled; 251 u16 id; 252 u32 src; 253 }; 254 255 struct qlcnic_macvlan_mbx { 256 #if defined(__LITTLE_ENDIAN) 257 u8 mac_addr0; 258 u8 mac_addr1; 259 u8 mac_addr2; 260 u8 mac_addr3; 261 u8 mac_addr4; 262 u8 mac_addr5; 263 u16 vlan; 264 #elif defined(__BIG_ENDIAN) 265 u8 mac_addr3; 266 u8 mac_addr2; 267 u8 mac_addr1; 268 u8 mac_addr0; 269 u16 vlan; 270 u8 mac_addr5; 271 u8 mac_addr4; 272 #endif 273 }; 274 275 struct qlc_83xx_fw_info { 276 const struct firmware *fw; 277 char fw_file_name[QLC_FW_FILE_NAME_LEN]; 278 }; 279 280 struct qlc_83xx_reset { 281 struct qlc_83xx_reset_hdr *hdr; 282 int seq_index; 283 int seq_error; 284 int array_index; 285 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES]; 286 u8 *buff; 287 u8 *stop_offset; 288 u8 *start_offset; 289 u8 *init_offset; 290 u8 seq_end; 291 u8 template_end; 292 }; 293 294 #define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 295 #define QLC_83XX_IDC_GRACEFULL_RESET 0x2 296 #define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4 297 #define QLC_83XX_IDC_TIMESTAMP 0 298 #define QLC_83XX_IDC_DURATION 1 299 #define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 300 #define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 301 #define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 302 #define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 303 #define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) 304 #define QLC_83XX_IDC_FW_FAIL_THRESH 2 305 #define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 306 #define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 307 #define QLC_83XX_IDC_MAJOR_VERSION 1 308 #define QLC_83XX_IDC_MINOR_VERSION 0 309 #define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 310 311 struct qlcnic_adapter; 312 struct qlcnic_fw_dump; 313 314 struct qlc_83xx_idc { 315 int (*state_entry) (struct qlcnic_adapter *); 316 u64 sec_counter; 317 u64 delay; 318 unsigned long status; 319 int err_code; 320 int collect_dump; 321 u8 curr_state; 322 u8 prev_state; 323 u8 vnic_state; 324 u8 vnic_wait_limit; 325 u8 quiesce_req; 326 u8 delay_reset; 327 char **name; 328 }; 329 330 enum qlcnic_vlan_operations { 331 QLC_VLAN_ADD = 0, 332 QLC_VLAN_DELETE 333 }; 334 335 /* Device States */ 336 enum qlcnic_83xx_states { 337 QLC_83XX_IDC_DEV_UNKNOWN, 338 QLC_83XX_IDC_DEV_COLD, 339 QLC_83XX_IDC_DEV_INIT, 340 QLC_83XX_IDC_DEV_READY, 341 QLC_83XX_IDC_DEV_NEED_RESET, 342 QLC_83XX_IDC_DEV_NEED_QUISCENT, 343 QLC_83XX_IDC_DEV_FAILED, 344 QLC_83XX_IDC_DEV_QUISCENT 345 }; 346 347 #define QLCNIC_MBX_RSP(reg) LSW(reg) 348 #define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) 349 #define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) 350 #define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4)) 351 #define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4)) 352 353 /* Mailbox process AEN count */ 354 #define QLC_83XX_IDC_COMP_AEN 3 355 #define QLC_83XX_MBX_AEN_CNT 5 356 #define QLC_83XX_MODULE_LOADED 1 357 #define QLC_83XX_MBX_READY 2 358 #define QLC_83XX_MBX_AEN_ACK 3 359 #define QLC_83XX_SFP_PRESENT(data) ((data) & 3) 360 #define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) 361 #define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) 362 #define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) 363 #define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) 364 #define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) 365 #define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) 366 #define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) 367 #define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) 368 #define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) 369 #define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) 370 #define QLC_83XX_DCBX(data) (((data) >> 28) & 7) 371 #define QLC_83XX_AUTONEG(data) ((data) & BIT_15) 372 #define QLC_83XX_TX_PAUSE 0x10 373 #define QLC_83XX_RX_PAUSE 0x20 374 #define QLC_83XX_TX_RX_PAUSE 0x30 375 #define QLC_83XX_CFG_STD_PAUSE (1 << 5) 376 #define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) 377 #define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) 378 #define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) 379 #define QLC_83XX_ENABLE_AUTONEG (1 << 15) 380 #define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) 381 #define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) 382 #define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) 383 384 /* LED configuration settings */ 385 #define QLC_83XX_ENABLE_BEACON 0xe 386 #define QLC_83XX_BEACON_ON 1 387 #define QLC_83XX_BEACON_OFF 0 388 #define QLC_83XX_LED_RATE 0xff 389 #define QLC_83XX_LED_ACT (1 << 10) 390 #define QLC_83XX_LED_MOD (0 << 13) 391 #define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ 392 QLC_83XX_LED_MOD) 393 394 #define QLC_83XX_10M_LINK 1 395 #define QLC_83XX_100M_LINK 2 396 #define QLC_83XX_1G_LINK 3 397 #define QLC_83XX_10G_LINK 4 398 #define QLC_83XX_STAT_TX 3 399 #define QLC_83XX_STAT_RX 2 400 #define QLC_83XX_STAT_MAC 1 401 #define QLC_83XX_TX_STAT_REGS 14 402 #define QLC_83XX_RX_STAT_REGS 40 403 #define QLC_83XX_MAC_STAT_REGS 94 404 405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) 406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) 407 #define QLC_83XX_DEFAULT_OPMODE 0x55555555 408 #define QLC_83XX_PRIVLEGED_FUNC 0x1 409 #define QLC_83XX_VIRTUAL_FUNC 0x2 410 411 #define QLC_83XX_LB_MAX_FILTERS 2048 412 #define QLC_83XX_LB_BUCKET_SIZE 256 413 #define QLC_83XX_MINIMUM_VECTOR 3 414 #define QLC_83XX_MAX_MC_COUNT 38 415 #define QLC_83XX_MAX_UC_COUNT 4096 416 417 #define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22 418 #define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) 419 #define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) 420 #define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 421 #define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) 422 #define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) 423 #define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) 424 #define QLC_83XX_ESWITCH_CAPABILITY BIT_23 425 #define QLC_83XX_SRIOV_MODE 0x1 426 #define QLCNIC_BRDTYPE_83XX_10G 0x0083 427 428 #define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 429 #define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 430 #define QLC_83XX_FLASH_STATUS 0x42100004 431 #define QLC_83XX_FLASH_CONTROL 0x42110004 432 #define QLC_83XX_FLASH_ADDR 0x42110008 433 #define QLC_83XX_FLASH_WRDATA 0x4211000C 434 #define QLC_83XX_FLASH_RDDATA 0x42110018 435 #define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 436 #define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 437 #define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 438 #define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda 439 #define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca 440 #define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 441 #define QLC_83XX_FLASH_STATUS_READY 0x6 442 #define QLC_83XX_FLASH_WRITE_MIN 2 443 #define QLC_83XX_FLASH_WRITE_MAX 64 444 #define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 445 #define QLC_83XX_ERASE_MODE 1 446 #define QLC_83XX_WRITE_MODE 2 447 #define QLC_83XX_BULK_WRITE_MODE 3 448 #define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 449 #define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 450 #define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F 451 #define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 452 #define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 453 #define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 454 #define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 455 #define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 456 #define QLC_83XX_FLASH_WRDATA_DEF 0x0 457 #define QLC_83XX_FLASH_READ_CTRL 0x3F 458 #define QLC_83XX_FLASH_SPI_CTRL 0x4 459 #define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 460 #define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 461 #define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D 462 #define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 463 #define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F 464 #define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D 465 #define QLC_83xx_FLASH_MAX_WAIT_USEC 100 466 #define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 467 468 enum qlc_83xx_mbx_cmd_type { 469 QLC_83XX_MBX_CMD_WAIT = 0, 470 QLC_83XX_MBX_CMD_NO_WAIT, 471 QLC_83XX_MBX_CMD_BUSY_WAIT, 472 }; 473 474 enum qlc_83xx_mbx_response_states { 475 QLC_83XX_MBX_RESPONSE_WAIT = 0, 476 QLC_83XX_MBX_RESPONSE_ARRIVED, 477 }; 478 479 #define QLC_83XX_MBX_RESPONSE_FAILED 0x2 480 #define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3 481 482 /* Additional registers in 83xx */ 483 enum qlc_83xx_ext_regs { 484 QLCNIC_GLOBAL_RESET = 0, 485 QLCNIC_WILDCARD, 486 QLCNIC_INFORMANT, 487 QLCNIC_HOST_MBX_CTRL, 488 QLCNIC_FW_MBX_CTRL, 489 QLCNIC_BOOTLOADER_ADDR, 490 QLCNIC_BOOTLOADER_SIZE, 491 QLCNIC_FW_IMAGE_ADDR, 492 QLCNIC_MBX_INTR_ENBL, 493 QLCNIC_DEF_INT_MASK, 494 QLCNIC_DEF_INT_ID, 495 QLC_83XX_IDC_MAJ_VERSION, 496 QLC_83XX_IDC_DEV_STATE, 497 QLC_83XX_IDC_DRV_PRESENCE, 498 QLC_83XX_IDC_DRV_ACK, 499 QLC_83XX_IDC_CTRL, 500 QLC_83XX_IDC_DRV_AUDIT, 501 QLC_83XX_IDC_MIN_VERSION, 502 QLC_83XX_RECOVER_DRV_LOCK, 503 QLC_83XX_IDC_PF_0, 504 QLC_83XX_IDC_PF_1, 505 QLC_83XX_IDC_PF_2, 506 QLC_83XX_IDC_PF_3, 507 QLC_83XX_IDC_PF_4, 508 QLC_83XX_IDC_PF_5, 509 QLC_83XX_IDC_PF_6, 510 QLC_83XX_IDC_PF_7, 511 QLC_83XX_IDC_PF_8, 512 QLC_83XX_IDC_PF_9, 513 QLC_83XX_IDC_PF_10, 514 QLC_83XX_IDC_PF_11, 515 QLC_83XX_IDC_PF_12, 516 QLC_83XX_IDC_PF_13, 517 QLC_83XX_IDC_PF_14, 518 QLC_83XX_IDC_PF_15, 519 QLC_83XX_IDC_DEV_PARTITION_INFO_1, 520 QLC_83XX_IDC_DEV_PARTITION_INFO_2, 521 QLC_83XX_DRV_OP_MODE, 522 QLC_83XX_VNIC_STATE, 523 QLC_83XX_DRV_LOCK, 524 QLC_83XX_DRV_UNLOCK, 525 QLC_83XX_DRV_LOCK_ID, 526 QLC_83XX_ASIC_TEMP, 527 }; 528 529 /* Initialize/Stop NIC command bit definitions */ 530 #define QLC_REGISTER_LB_IDC BIT_0 531 #define QLC_REGISTER_DCB_AEN BIT_1 532 #define QLC_83XX_MULTI_TENANCY_INFO BIT_29 533 #define QLC_INIT_FW_RESOURCES BIT_31 534 535 /* 83xx funcitons */ 536 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); 537 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 538 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *); 539 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); 540 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); 541 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); 542 void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); 543 void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); 544 void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 545 void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 546 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); 547 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); 548 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); 549 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); 550 int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); 551 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, 552 u16 vlan, struct qlcnic_host_tx_ring *ring); 553 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); 554 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 555 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int); 556 557 int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); 558 void qlcnic_83xx_napi_del(struct qlcnic_adapter *); 559 void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); 560 void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); 561 int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); 562 int qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); 563 int qlcnic_ind_rd(struct qlcnic_adapter *, u32); 564 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); 565 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, 566 struct qlcnic_host_tx_ring *, int); 567 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *); 568 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *, 569 struct qlcnic_host_tx_ring *); 570 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 571 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); 572 void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); 573 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); 574 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); 575 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8); 576 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, 577 struct qlcnic_adapter *, u32); 578 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); 579 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *, 580 struct ethtool_coalesce *); 581 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *); 582 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); 583 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *); 584 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *); 585 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); 586 irqreturn_t qlcnic_83xx_intr(int, void *); 587 irqreturn_t qlcnic_83xx_tmp_intr(int, void *); 588 void qlcnic_83xx_check_vf(struct qlcnic_adapter *, 589 const struct pci_device_id *); 590 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); 591 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); 592 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); 593 void qlcnic_83xx_idc_aen_work(struct work_struct *); 594 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); 595 596 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); 597 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); 598 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); 599 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); 600 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); 601 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); 602 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); 603 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); 604 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, 605 u32, u8 *, int); 606 int qlcnic_83xx_init(struct qlcnic_adapter *); 607 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); 608 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); 609 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); 610 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); 611 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); 612 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); 613 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); 614 int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); 615 int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); 616 int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *); 617 618 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); 619 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); 620 int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *); 621 int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter, 622 struct ethtool_link_ksettings *ecmd); 623 int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter, 624 const struct ethtool_link_ksettings *ecmd); 625 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, 626 struct ethtool_pauseparam *); 627 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, 628 struct ethtool_pauseparam *); 629 int qlcnic_83xx_test_link(struct qlcnic_adapter *); 630 void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter); 631 int qlcnic_83xx_reg_test(struct qlcnic_adapter *); 632 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); 633 int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); 634 int qlcnic_83xx_loopback_test(struct net_device *, u8); 635 int qlcnic_83xx_interrupt_test(struct net_device *); 636 int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state); 637 int qlcnic_83xx_flash_test(struct qlcnic_adapter *); 638 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *); 639 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *); 640 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *); 641 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *); 642 int qlcnic_83xx_idc_init(struct qlcnic_adapter *); 643 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *); 644 int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *); 645 int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *); 646 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *); 647 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *); 648 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *); 649 u32 qlcnic_83xx_get_saved_state(void *, u32); 650 void qlcnic_83xx_set_saved_state(void *, u32, u32); 651 void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *); 652 u32 qlcnic_83xx_get_cap_size(void *, int); 653 void qlcnic_83xx_set_sys_info(void *, int, u32); 654 void qlcnic_83xx_store_cap_mask(void *, u32); 655 int qlcnic_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); 656 #endif 657