1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm ICE (Inline Crypto Engine) support.
4 *
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2019, Google LLC
7 * Copyright (c) 2023, Linaro Limited
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/iopoll.h>
16 #include <linux/of.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19
20 #include <linux/firmware/qcom/qcom_scm.h>
21
22 #include <soc/qcom/ice.h>
23
24 #define AES_256_XTS_KEY_SIZE 64
25
26 /* QCOM ICE registers */
27 #define QCOM_ICE_REG_VERSION 0x0008
28 #define QCOM_ICE_REG_FUSE_SETTING 0x0010
29 #define QCOM_ICE_REG_BIST_STATUS 0x0070
30 #define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000
31
32 /* BIST ("built-in self-test") status flags */
33 #define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28)
34
35 #define QCOM_ICE_FUSE_SETTING_MASK 0x1
36 #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
37 #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
38
39 #define qcom_ice_writel(engine, val, reg) \
40 writel((val), (engine)->base + (reg))
41
42 #define qcom_ice_readl(engine, reg) \
43 readl((engine)->base + (reg))
44
45 struct qcom_ice {
46 struct device *dev;
47 void __iomem *base;
48
49 struct clk *core_clk;
50 };
51
qcom_ice_check_supported(struct qcom_ice * ice)52 static bool qcom_ice_check_supported(struct qcom_ice *ice)
53 {
54 u32 regval = qcom_ice_readl(ice, QCOM_ICE_REG_VERSION);
55 struct device *dev = ice->dev;
56 int major = FIELD_GET(GENMASK(31, 24), regval);
57 int minor = FIELD_GET(GENMASK(23, 16), regval);
58 int step = FIELD_GET(GENMASK(15, 0), regval);
59
60 /* For now this driver only supports ICE version 3 and 4. */
61 if (major != 3 && major != 4) {
62 dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
63 major, minor, step);
64 return false;
65 }
66
67 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
68 major, minor, step);
69
70 /* If fuses are blown, ICE might not work in the standard way. */
71 regval = qcom_ice_readl(ice, QCOM_ICE_REG_FUSE_SETTING);
72 if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
73 QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
74 QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
75 dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
76 return false;
77 }
78
79 return true;
80 }
81
qcom_ice_low_power_mode_enable(struct qcom_ice * ice)82 static void qcom_ice_low_power_mode_enable(struct qcom_ice *ice)
83 {
84 u32 regval;
85
86 regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL);
87
88 /* Enable low power mode sequence */
89 regval |= 0x7000;
90 qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
91 }
92
qcom_ice_optimization_enable(struct qcom_ice * ice)93 static void qcom_ice_optimization_enable(struct qcom_ice *ice)
94 {
95 u32 regval;
96
97 /* ICE Optimizations Enable Sequence */
98 regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL);
99 regval |= 0xd807100;
100 /* ICE HPG requires delay before writing */
101 udelay(5);
102 qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
103 udelay(5);
104 }
105
106 /*
107 * Wait until the ICE BIST (built-in self-test) has completed.
108 *
109 * This may be necessary before ICE can be used.
110 * Note that we don't really care whether the BIST passed or failed;
111 * we really just want to make sure that it isn't still running. This is
112 * because (a) the BIST is a FIPS compliance thing that never fails in
113 * practice, (b) ICE is documented to reject crypto requests if the BIST
114 * fails, so we needn't do it in software too, and (c) properly testing
115 * storage encryption requires testing the full storage stack anyway,
116 * and not relying on hardware-level self-tests.
117 */
qcom_ice_wait_bist_status(struct qcom_ice * ice)118 static int qcom_ice_wait_bist_status(struct qcom_ice *ice)
119 {
120 u32 regval;
121 int err;
122
123 err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS,
124 regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),
125 50, 5000);
126 if (err)
127 dev_err(ice->dev, "Timed out waiting for ICE self-test to complete\n");
128
129 return err;
130 }
131
qcom_ice_enable(struct qcom_ice * ice)132 int qcom_ice_enable(struct qcom_ice *ice)
133 {
134 qcom_ice_low_power_mode_enable(ice);
135 qcom_ice_optimization_enable(ice);
136
137 return qcom_ice_wait_bist_status(ice);
138 }
139 EXPORT_SYMBOL_GPL(qcom_ice_enable);
140
qcom_ice_resume(struct qcom_ice * ice)141 int qcom_ice_resume(struct qcom_ice *ice)
142 {
143 struct device *dev = ice->dev;
144 int err;
145
146 err = clk_prepare_enable(ice->core_clk);
147 if (err) {
148 dev_err(dev, "failed to enable core clock (%d)\n",
149 err);
150 return err;
151 }
152
153 return qcom_ice_wait_bist_status(ice);
154 }
155 EXPORT_SYMBOL_GPL(qcom_ice_resume);
156
qcom_ice_suspend(struct qcom_ice * ice)157 int qcom_ice_suspend(struct qcom_ice *ice)
158 {
159 clk_disable_unprepare(ice->core_clk);
160
161 return 0;
162 }
163 EXPORT_SYMBOL_GPL(qcom_ice_suspend);
164
qcom_ice_program_key(struct qcom_ice * ice,u8 algorithm_id,u8 key_size,const u8 crypto_key[],u8 data_unit_size,int slot)165 int qcom_ice_program_key(struct qcom_ice *ice,
166 u8 algorithm_id, u8 key_size,
167 const u8 crypto_key[], u8 data_unit_size,
168 int slot)
169 {
170 struct device *dev = ice->dev;
171 union {
172 u8 bytes[AES_256_XTS_KEY_SIZE];
173 u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
174 } key;
175 int i;
176 int err;
177
178 /* Only AES-256-XTS has been tested so far. */
179 if (algorithm_id != QCOM_ICE_CRYPTO_ALG_AES_XTS ||
180 key_size != QCOM_ICE_CRYPTO_KEY_SIZE_256) {
181 dev_err_ratelimited(dev,
182 "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
183 algorithm_id, key_size);
184 return -EINVAL;
185 }
186
187 memcpy(key.bytes, crypto_key, AES_256_XTS_KEY_SIZE);
188
189 /* The SCM call requires that the key words are encoded in big endian */
190 for (i = 0; i < ARRAY_SIZE(key.words); i++)
191 __cpu_to_be32s(&key.words[i]);
192
193 err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
194 QCOM_SCM_ICE_CIPHER_AES_256_XTS,
195 data_unit_size);
196
197 memzero_explicit(&key, sizeof(key));
198
199 return err;
200 }
201 EXPORT_SYMBOL_GPL(qcom_ice_program_key);
202
qcom_ice_evict_key(struct qcom_ice * ice,int slot)203 int qcom_ice_evict_key(struct qcom_ice *ice, int slot)
204 {
205 return qcom_scm_ice_invalidate_key(slot);
206 }
207 EXPORT_SYMBOL_GPL(qcom_ice_evict_key);
208
qcom_ice_create(struct device * dev,void __iomem * base)209 static struct qcom_ice *qcom_ice_create(struct device *dev,
210 void __iomem *base)
211 {
212 struct qcom_ice *engine;
213
214 if (!qcom_scm_is_available())
215 return ERR_PTR(-EPROBE_DEFER);
216
217 if (!qcom_scm_ice_available()) {
218 dev_warn(dev, "ICE SCM interface not found\n");
219 return NULL;
220 }
221
222 engine = devm_kzalloc(dev, sizeof(*engine), GFP_KERNEL);
223 if (!engine)
224 return ERR_PTR(-ENOMEM);
225
226 engine->dev = dev;
227 engine->base = base;
228
229 /*
230 * Legacy DT binding uses different clk names for each consumer,
231 * so lets try those first. If none of those are a match, it means
232 * the we only have one clock and it is part of the dedicated DT node.
233 * Also, enable the clock before we check what HW version the driver
234 * supports.
235 */
236 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk");
237 if (!engine->core_clk)
238 engine->core_clk = devm_clk_get_optional_enabled(dev, "ice");
239 if (!engine->core_clk)
240 engine->core_clk = devm_clk_get_enabled(dev, NULL);
241 if (IS_ERR(engine->core_clk))
242 return ERR_CAST(engine->core_clk);
243
244 if (!qcom_ice_check_supported(engine))
245 return ERR_PTR(-EOPNOTSUPP);
246
247 dev_dbg(dev, "Registered Qualcomm Inline Crypto Engine\n");
248
249 return engine;
250 }
251
252 /**
253 * of_qcom_ice_get() - get an ICE instance from a DT node
254 * @dev: device pointer for the consumer device
255 *
256 * This function will provide an ICE instance either by creating one for the
257 * consumer device if its DT node provides the 'ice' reg range and the 'ice'
258 * clock (for legacy DT style). On the other hand, if consumer provides a
259 * phandle via 'qcom,ice' property to an ICE DT, the ICE instance will already
260 * be created and so this function will return that instead.
261 *
262 * Return: ICE pointer on success, NULL if there is no ICE data provided by the
263 * consumer or ERR_PTR() on error.
264 */
of_qcom_ice_get(struct device * dev)265 static struct qcom_ice *of_qcom_ice_get(struct device *dev)
266 {
267 struct platform_device *pdev = to_platform_device(dev);
268 struct qcom_ice *ice;
269 struct resource *res;
270 void __iomem *base;
271 struct device_link *link;
272
273 if (!dev || !dev->of_node)
274 return ERR_PTR(-ENODEV);
275
276 /*
277 * In order to support legacy style devicetree bindings, we need
278 * to create the ICE instance using the consumer device and the reg
279 * range called 'ice' it provides.
280 */
281 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice");
282 if (res) {
283 base = devm_ioremap_resource(&pdev->dev, res);
284 if (IS_ERR(base))
285 return ERR_CAST(base);
286
287 /* create ICE instance using consumer dev */
288 return qcom_ice_create(&pdev->dev, base);
289 }
290
291 /*
292 * If the consumer node does not provider an 'ice' reg range
293 * (legacy DT binding), then it must at least provide a phandle
294 * to the ICE devicetree node, otherwise ICE is not supported.
295 */
296 struct device_node *node __free(device_node) = of_parse_phandle(dev->of_node,
297 "qcom,ice", 0);
298 if (!node)
299 return NULL;
300
301 pdev = of_find_device_by_node(node);
302 if (!pdev) {
303 dev_err(dev, "Cannot find device node %s\n", node->name);
304 return ERR_PTR(-EPROBE_DEFER);
305 }
306
307 ice = platform_get_drvdata(pdev);
308 if (!ice) {
309 dev_err(dev, "Cannot get ice instance from %s\n",
310 dev_name(&pdev->dev));
311 platform_device_put(pdev);
312 return ERR_PTR(-EPROBE_DEFER);
313 }
314
315 link = device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER);
316 if (!link) {
317 dev_err(&pdev->dev,
318 "Failed to create device link to consumer %s\n",
319 dev_name(dev));
320 platform_device_put(pdev);
321 ice = ERR_PTR(-EINVAL);
322 }
323
324 return ice;
325 }
326
qcom_ice_put(const struct qcom_ice * ice)327 static void qcom_ice_put(const struct qcom_ice *ice)
328 {
329 struct platform_device *pdev = to_platform_device(ice->dev);
330
331 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice"))
332 platform_device_put(pdev);
333 }
334
devm_of_qcom_ice_put(struct device * dev,void * res)335 static void devm_of_qcom_ice_put(struct device *dev, void *res)
336 {
337 qcom_ice_put(*(struct qcom_ice **)res);
338 }
339
340 /**
341 * devm_of_qcom_ice_get() - Devres managed helper to get an ICE instance from
342 * a DT node.
343 * @dev: device pointer for the consumer device.
344 *
345 * This function will provide an ICE instance either by creating one for the
346 * consumer device if its DT node provides the 'ice' reg range and the 'ice'
347 * clock (for legacy DT style). On the other hand, if consumer provides a
348 * phandle via 'qcom,ice' property to an ICE DT, the ICE instance will already
349 * be created and so this function will return that instead.
350 *
351 * Return: ICE pointer on success, NULL if there is no ICE data provided by the
352 * consumer or ERR_PTR() on error.
353 */
devm_of_qcom_ice_get(struct device * dev)354 struct qcom_ice *devm_of_qcom_ice_get(struct device *dev)
355 {
356 struct qcom_ice *ice, **dr;
357
358 dr = devres_alloc(devm_of_qcom_ice_put, sizeof(*dr), GFP_KERNEL);
359 if (!dr)
360 return ERR_PTR(-ENOMEM);
361
362 ice = of_qcom_ice_get(dev);
363 if (!IS_ERR_OR_NULL(ice)) {
364 *dr = ice;
365 devres_add(dev, dr);
366 } else {
367 devres_free(dr);
368 }
369
370 return ice;
371 }
372 EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get);
373
qcom_ice_probe(struct platform_device * pdev)374 static int qcom_ice_probe(struct platform_device *pdev)
375 {
376 struct qcom_ice *engine;
377 void __iomem *base;
378
379 base = devm_platform_ioremap_resource(pdev, 0);
380 if (IS_ERR(base)) {
381 dev_warn(&pdev->dev, "ICE registers not found\n");
382 return PTR_ERR(base);
383 }
384
385 engine = qcom_ice_create(&pdev->dev, base);
386 if (IS_ERR(engine))
387 return PTR_ERR(engine);
388
389 platform_set_drvdata(pdev, engine);
390
391 return 0;
392 }
393
394 static const struct of_device_id qcom_ice_of_match_table[] = {
395 { .compatible = "qcom,inline-crypto-engine" },
396 { },
397 };
398 MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table);
399
400 static struct platform_driver qcom_ice_driver = {
401 .probe = qcom_ice_probe,
402 .driver = {
403 .name = "qcom-ice",
404 .of_match_table = qcom_ice_of_match_table,
405 },
406 };
407
408 module_platform_driver(qcom_ice_driver);
409
410 MODULE_DESCRIPTION("Qualcomm Inline Crypto Engine driver");
411 MODULE_LICENSE("GPL");
412