xref: /linux/include/linux/dsa/tag_qca.h (revision ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 #ifndef __TAG_QCA_H
4 #define __TAG_QCA_H
5 
6 #include <linux/types.h>
7 
8 struct dsa_switch;
9 struct sk_buff;
10 
11 #define QCA_HDR_LEN	2
12 #define QCA_HDR_VERSION	0x2
13 
14 #define QCA_HDR_RECV_VERSION		GENMASK(15, 14)
15 #define QCA_HDR_RECV_PRIORITY		GENMASK(13, 11)
16 #define QCA_HDR_RECV_TYPE		GENMASK(10, 6)
17 #define QCA_HDR_RECV_FRAME_IS_TAGGED	BIT(3)
18 #define QCA_HDR_RECV_SOURCE_PORT	GENMASK(2, 0)
19 
20 /* Packet type for recv */
21 #define QCA_HDR_RECV_TYPE_NORMAL	0x0
22 #define QCA_HDR_RECV_TYPE_MIB		0x1
23 #define QCA_HDR_RECV_TYPE_RW_REG_ACK	0x2
24 
25 #define QCA_HDR_XMIT_VERSION		GENMASK(15, 14)
26 #define QCA_HDR_XMIT_PRIORITY		GENMASK(13, 11)
27 #define QCA_HDR_XMIT_CONTROL		GENMASK(10, 8)
28 #define QCA_HDR_XMIT_FROM_CPU		BIT(7)
29 #define QCA_HDR_XMIT_DP_BIT		GENMASK(6, 0)
30 
31 /* Packet type for xmit */
32 #define QCA_HDR_XMIT_TYPE_NORMAL	0x0
33 #define QCA_HDR_XMIT_TYPE_RW_REG	0x1
34 
35 /* Check code for a valid mgmt packet. Switch will ignore the packet
36  * with this wrong.
37  */
38 #define QCA_HDR_MGMT_CHECK_CODE_VAL	0x5
39 
40 /* Specific define for in-band MDIO read/write with Ethernet packet */
41 #define QCA_HDR_MGMT_SEQ_LEN		4 /* 4 byte for the seq */
42 #define QCA_HDR_MGMT_COMMAND_LEN	4 /* 4 byte for the command */
43 #define QCA_HDR_MGMT_DATA1_LEN		4 /* First 4 byte for the mdio data */
44 #define QCA_HDR_MGMT_HEADER_LEN		(QCA_HDR_MGMT_SEQ_LEN + \
45 					QCA_HDR_MGMT_COMMAND_LEN + \
46 					QCA_HDR_MGMT_DATA1_LEN)
47 
48 #define QCA_HDR_MGMT_DATA2_LEN		28 /* Other 28 byte for the mdio data */
49 #define QCA_HDR_MGMT_PADDING_LEN	18 /* Padding to reach the min Ethernet packet */
50 
51 #define QCA_HDR_MGMT_PKT_LEN		(QCA_HDR_MGMT_HEADER_LEN + \
52 					QCA_HDR_LEN + \
53 					QCA_HDR_MGMT_DATA2_LEN + \
54 					QCA_HDR_MGMT_PADDING_LEN)
55 
56 #define QCA_HDR_MGMT_SEQ_NUM		GENMASK(31, 0)  /* 63, 32 */
57 #define QCA_HDR_MGMT_CHECK_CODE		GENMASK(31, 29) /* 31, 29 */
58 #define QCA_HDR_MGMT_CMD		BIT(28)		/* 28 */
59 #define QCA_HDR_MGMT_LENGTH		GENMASK(23, 20) /* 23, 20 */
60 #define QCA_HDR_MGMT_ADDR		GENMASK(18, 0)  /* 18, 0 */
61 
62 /* Special struct emulating a Ethernet header */
63 struct qca_mgmt_ethhdr {
64 	__le32 command;		/* command bit 31:0 */
65 	__le32 seq;		/* seq 63:32 */
66 	__le32 mdio_data;		/* first 4byte mdio */
67 	__be16 hdr;		/* qca hdr */
68 } __packed;
69 
70 enum mdio_cmd {
71 	MDIO_WRITE = 0x0,
72 	MDIO_READ
73 };
74 
75 struct mib_ethhdr {
76 	__le32 data[3];		/* first 3 mib counter */
77 	__be16 hdr;		/* qca hdr */
78 } __packed;
79 
80 struct qca_tagger_data {
81 	void (*rw_reg_ack_handler)(struct dsa_switch *ds,
82 				   struct sk_buff *skb);
83 	void (*mib_autocast_handler)(struct dsa_switch *ds,
84 				     struct sk_buff *skb);
85 };
86 
87 #endif /* __TAG_QCA_H */
88