Home
last modified time | relevance | path

Searched defs:PredReg (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp73 Register PredReg; in ReplaceTailWithBranchTo() local
121 Register PredReg; in isLegalToSplitMBBAt() local
315 ARMCC::CondCodes Pred, Register PredReg, in emitT2RegPlusImmediate()
575 Register PredReg; in rewriteT2FrameIndex() local
789 Register &PredReg) { in getITInstrPredicate()
807 Register &PredReg) { in getVPTInstrPredicate()
H A DThumb2InstrInfo.h90 Register PredReg; in getVPTInstrPredicate() local
H A DARMLoadStoreOptimizer.cpp487 unsigned PredReg) { in UpdateBaseRegUses()
628 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
835 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
905 Register PredReg; in MergeOpsUpdate() local
1189 ARMCC::CondCodes Pred, Register PredReg) { in isIncrementOrDecrement()
1221 ARMCC::CondCodes Pred, Register PredReg, int &Offset) { in findIncDecBefore()
1241 ARMCC::CondCodes Pred, Register PredReg, int &Offset, in findIncDecAfter()
1294 Register PredReg; in MergeBaseUpdateLSMultiple() local
1490 Register PredReg; in MergeBaseUpdateLoadStore() local
1628 Register PredReg; in MergeBaseUpdateLSDouble() local
[all …]
H A DMVEVPTBlockPass.cpp101 Register PredReg; in StepOverPredicatedInstrs() local
247 Register PredReg; in InsertVPTBlocks() local
H A DThumb2SizeReduction.cpp466 Register PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
684 Register PredReg; in ReduceSpecial() local
726 Register PredReg; in ReduceSpecial() local
800 Register PredReg; in ReduceTo2Addr() local
892 Register PredReg; in ReduceToNarrow() local
H A DThumbRegisterInfo.cpp63 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
83 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
104 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
H A DThumb2ITBlockPass.cpp197 Register PredReg; in InsertITInstructions() local
H A DARMBaseRegisterInfo.cpp528 ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const { in emitLoadConstPool()
881 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
H A DARMConstantIslandPass.cpp1451 Register PredReg; in createNewWater() local
1497 Register PredReg; in createNewWater() local
1521 Register PredReg; in createNewWater() local
1924 Register PredReg; in optimizeThumb2Branches() local
H A DMLxExpansionPass.cpp282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
H A DARMFrameLowering.cpp677 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
691 unsigned PredReg = 0) { in emitSPUpdate()
3181 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr() local
H A DARMISelDAGToDAG.cpp1749 SDValue PredReg; in tryMVEIndexedLoad() local
2916 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in SelectCDE_CXxD() local
4258 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4270 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
4281 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
H A DARMBaseInstrInfo.cpp2077 Register &PredReg) { in getInstrPredicate()
2107 Register PredReg; in commuteInstructionImpl() local
2315 ARMCC::CondCodes Pred, Register PredReg, in emitARMRegPlusImmediate()
5465 Register PredReg; in findCMPToFoldIntoCBZ() local
H A DARMExpandPseudoInsts.cpp1062 Register PredReg; in ExpandMOV32BitImm() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
H A DHexagonMCChecker.cpp69 MCRegister &PredReg, bool &isTrue) { in initReg()
94 MCRegister PredReg; in init() local
H A DHexagonMCCompound.cpp177 MCRegister PredReg = Predicate.getReg(); in getCompoundOp() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp298 bool HexagonGenPredicate::isScalarPred(RegSubRegPair PredReg) { in isScalarPred()
H A DHexagonInstrInfo.cpp1704 Register PredReg; in PredicateInstruction() local
4554 Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
H A DHexagonHardwareLoops.cpp644 Register PredReg; in getLoopTripCount() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp4626 ScopedScavengeOrSpill PredReg( in expandFillPPRFromZPRSlotPseudo() local
H A DAArch64InstrInfo.cpp1603 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr()