1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phy.h> 15 #include <linux/regmap.h> 16 #include <net/dsa.h> 17 #include <linux/irq.h> 18 #include <linux/platform_data/microchip-ksz.h> 19 20 #include "ksz_ptp.h" 21 22 #define KSZ_MAX_NUM_PORTS 8 23 /* all KSZ switches count ports from 1 */ 24 #define KSZ_PORT_1 0 25 #define KSZ_PORT_2 1 26 #define KSZ_PORT_4 3 27 28 struct ksz_device; 29 struct ksz_port; 30 struct phylink_mac_ops; 31 32 enum ksz_regmap_width { 33 KSZ_REGMAP_8, 34 KSZ_REGMAP_16, 35 KSZ_REGMAP_32, 36 __KSZ_NUM_REGMAPS, 37 }; 38 39 struct vlan_table { 40 u32 table[3]; 41 }; 42 43 struct ksz_port_mib { 44 struct mutex cnt_mutex; /* structure access */ 45 u8 cnt_ptr; 46 u64 *counters; 47 struct rtnl_link_stats64 stats64; 48 struct ethtool_pause_stats pause_stats; 49 struct spinlock stats64_lock; 50 }; 51 52 struct ksz_mib_names { 53 int index; 54 char string[ETH_GSTRING_LEN]; 55 }; 56 57 struct ksz_chip_data { 58 u32 chip_id; 59 const char *dev_name; 60 int num_vlans; 61 int num_alus; 62 int num_statics; 63 int cpu_ports; 64 int port_cnt; 65 u8 port_nirqs; 66 u8 num_tx_queues; 67 u8 num_ipms; /* number of Internal Priority Maps */ 68 bool tc_cbs_supported; 69 70 /** 71 * @phy_side_mdio_supported: Indicates if the chip supports an additional 72 * side MDIO channel for accessing integrated PHYs. 73 */ 74 bool phy_side_mdio_supported; 75 const struct ksz_dev_ops *ops; 76 const struct phylink_mac_ops *phylink_mac_ops; 77 bool phy_errata_9477; 78 bool ksz87xx_eee_link_erratum; 79 const struct ksz_mib_names *mib_names; 80 int mib_cnt; 81 u8 reg_mib_cnt; 82 const u16 *regs; 83 const u32 *masks; 84 const u8 *shifts; 85 const u8 *xmii_ctrl0; 86 const u8 *xmii_ctrl1; 87 int stp_ctrl_reg; 88 int broadcast_ctrl_reg; 89 int multicast_ctrl_reg; 90 int start_ctrl_reg; 91 bool supports_mii[KSZ_MAX_NUM_PORTS]; 92 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 93 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 94 bool internal_phy[KSZ_MAX_NUM_PORTS]; 95 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 96 bool ptp_capable; 97 u8 sgmii_port; 98 const struct regmap_access_table *wr_table; 99 const struct regmap_access_table *rd_table; 100 }; 101 102 struct ksz_irq { 103 u16 masked; 104 u16 reg_mask; 105 u16 reg_status; 106 struct irq_domain *domain; 107 int nirqs; 108 int irq_num; 109 char name[16]; 110 struct ksz_device *dev; 111 u16 irq0_offset; 112 }; 113 114 struct ksz_ptp_irq { 115 struct ksz_port *port; 116 u16 ts_reg; 117 bool ts_en; 118 char name[16]; 119 int num; 120 }; 121 122 struct ksz_switch_macaddr { 123 unsigned char addr[ETH_ALEN]; 124 refcount_t refcount; 125 }; 126 127 struct ksz_port { 128 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 129 bool learning; 130 bool isolated; 131 int stp_state; 132 struct phy_device phydev; 133 134 u32 fiber:1; /* port is fiber */ 135 u32 force:1; 136 u32 read:1; /* read MIB counters in background */ 137 u32 freeze:1; /* MIB counter freeze is enabled */ 138 u32 sgmii_adv_write:1; 139 140 struct ksz_port_mib mib; 141 phy_interface_t interface; 142 u32 rgmii_tx_val; 143 u32 rgmii_rx_val; 144 struct ksz_device *ksz_dev; 145 void *acl_priv; 146 struct ksz_irq pirq; 147 u8 num; 148 struct phylink_pcs *pcs; 149 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 150 struct kernel_hwtstamp_config tstamp_config; 151 bool hwts_tx_en; 152 bool hwts_rx_en; 153 struct ksz_irq ptpirq; 154 struct ksz_ptp_irq ptpmsg_irq[3]; 155 ktime_t tstamp_msg; 156 struct completion tstamp_msg_comp; 157 #endif 158 bool manual_flow; 159 }; 160 161 struct ksz_device { 162 struct dsa_switch *ds; 163 struct ksz_platform_data *pdata; 164 const struct ksz_chip_data *info; 165 166 struct mutex dev_mutex; /* device access */ 167 struct mutex regmap_mutex; /* regmap access */ 168 struct mutex alu_mutex; /* ALU access */ 169 struct mutex vlan_mutex; /* vlan access */ 170 const struct ksz_dev_ops *dev_ops; 171 172 struct device *dev; 173 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 174 175 void *priv; 176 int irq; 177 178 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 179 180 /* chip specific data */ 181 u32 chip_id; 182 u8 chip_rev; 183 int cpu_port; /* port connected to CPU */ 184 int phy_port_cnt; 185 phy_interface_t compat_interface; 186 bool synclko_125; 187 bool synclko_disable; 188 bool wakeup_source; 189 bool pme_active_high; 190 191 struct vlan_table *vlan_cache; 192 193 struct ksz_port *ports; 194 struct delayed_work mib_read; 195 unsigned long mib_read_interval; 196 u16 mirror_rx; 197 u16 mirror_tx; 198 u16 port_mask; 199 struct mutex lock_irq; /* IRQ Access */ 200 struct ksz_irq girq; 201 struct ksz_ptp_data ptp_data; 202 203 struct ksz_switch_macaddr *switch_macaddr; 204 struct net_device *hsr_dev; /* HSR */ 205 u8 hsr_ports; 206 207 /** 208 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 209 * addresses. 210 */ 211 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 212 213 /** 214 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 215 * 216 * This points to an external MDIO bus controller that is used to access 217 * the PHYs integrated within the switch. Unlike an integrated MDIO 218 * bus, this external controller provides a direct path for managing 219 * the switch’s internal PHYs, bypassing the main SPI interface. 220 */ 221 struct mii_bus *parent_mdio_bus; 222 }; 223 224 /* List of supported models */ 225 enum ksz_model { 226 KSZ8463, 227 KSZ8563, 228 KSZ8567, 229 KSZ8795, 230 KSZ8794, 231 KSZ8765, 232 KSZ88X3, 233 KSZ8864, 234 KSZ8895, 235 KSZ9477, 236 KSZ9896, 237 KSZ9897, 238 KSZ9893, 239 KSZ9563, 240 KSZ9567, 241 LAN9370, 242 LAN9371, 243 LAN9372, 244 LAN9373, 245 LAN9374, 246 LAN9646, 247 }; 248 249 enum ksz_regs { 250 REG_SW_MAC_ADDR, 251 REG_IND_CTRL_0, 252 REG_IND_DATA_8, 253 REG_IND_DATA_CHECK, 254 REG_IND_DATA_HI, 255 REG_IND_DATA_LO, 256 REG_IND_MIB_CHECK, 257 REG_IND_BYTE, 258 P_FORCE_CTRL, 259 P_LINK_STATUS, 260 P_LOCAL_CTRL, 261 P_NEG_RESTART_CTRL, 262 P_REMOTE_STATUS, 263 P_SPEED_STATUS, 264 S_TAIL_TAG_CTRL, 265 P_STP_CTRL, 266 S_START_CTRL, 267 S_BROADCAST_CTRL, 268 S_MULTICAST_CTRL, 269 P_XMII_CTRL_0, 270 P_XMII_CTRL_1, 271 REG_SW_PME_CTRL, 272 REG_PORT_PME_STATUS, 273 REG_PORT_PME_CTRL, 274 PTP_CLK_CTRL, 275 PTP_RTC_NANOSEC, 276 PTP_RTC_SEC, 277 PTP_RTC_SUB_NANOSEC, 278 PTP_SUBNANOSEC_RATE, 279 PTP_MSG_CONF1, 280 }; 281 282 enum ksz_masks { 283 PORT_802_1P_REMAPPING, 284 SW_TAIL_TAG_ENABLE, 285 MIB_COUNTER_OVERFLOW, 286 MIB_COUNTER_VALID, 287 VLAN_TABLE_FID, 288 VLAN_TABLE_MEMBERSHIP, 289 VLAN_TABLE_VALID, 290 STATIC_MAC_TABLE_VALID, 291 STATIC_MAC_TABLE_USE_FID, 292 STATIC_MAC_TABLE_FID, 293 STATIC_MAC_TABLE_OVERRIDE, 294 STATIC_MAC_TABLE_FWD_PORTS, 295 DYNAMIC_MAC_TABLE_ENTRIES_H, 296 DYNAMIC_MAC_TABLE_MAC_EMPTY, 297 DYNAMIC_MAC_TABLE_NOT_READY, 298 DYNAMIC_MAC_TABLE_ENTRIES, 299 DYNAMIC_MAC_TABLE_FID, 300 DYNAMIC_MAC_TABLE_SRC_PORT, 301 DYNAMIC_MAC_TABLE_TIMESTAMP, 302 ALU_STAT_WRITE, 303 ALU_STAT_READ, 304 ALU_STAT_DIRECT, 305 ALU_RESV_MCAST_ADDR, 306 P_MII_TX_FLOW_CTRL, 307 P_MII_RX_FLOW_CTRL, 308 }; 309 310 enum ksz_shifts { 311 VLAN_TABLE_MEMBERSHIP_S, 312 VLAN_TABLE, 313 STATIC_MAC_FWD_PORTS, 314 STATIC_MAC_FID, 315 DYNAMIC_MAC_ENTRIES_H, 316 DYNAMIC_MAC_ENTRIES, 317 DYNAMIC_MAC_FID, 318 DYNAMIC_MAC_TIMESTAMP, 319 DYNAMIC_MAC_SRC_PORT, 320 ALU_STAT_INDEX, 321 }; 322 323 enum ksz_xmii_ctrl0 { 324 P_MII_100MBIT, 325 P_MII_10MBIT, 326 P_MII_FULL_DUPLEX, 327 P_MII_HALF_DUPLEX, 328 }; 329 330 enum ksz_xmii_ctrl1 { 331 P_RGMII_SEL, 332 P_RMII_SEL, 333 P_GMII_SEL, 334 P_MII_SEL, 335 P_GMII_1GBIT, 336 P_GMII_NOT_1GBIT, 337 }; 338 339 struct alu_struct { 340 /* entry 1 */ 341 u8 is_static:1; 342 u8 is_src_filter:1; 343 u8 is_dst_filter:1; 344 u8 prio_age:3; 345 u32 _reserv_0_1:23; 346 u8 mstp:3; 347 /* entry 2 */ 348 u8 is_override:1; 349 u8 is_use_fid:1; 350 u32 _reserv_1_1:23; 351 u8 port_forward:7; 352 /* entry 3 & 4*/ 353 u32 _reserv_2_1:9; 354 u8 fid:7; 355 u8 mac[ETH_ALEN]; 356 }; 357 358 struct ksz_dev_ops { 359 int (*setup)(struct dsa_switch *ds); 360 void (*teardown)(struct dsa_switch *ds); 361 u32 (*get_port_addr)(int port, int offset); 362 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 363 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 364 void (*port_cleanup)(struct ksz_device *dev, int port); 365 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 366 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 367 368 /** 369 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus 370 * for accessing PHYs. 371 * @dev: Pointer to device structure. 372 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 373 * MDIO bus. 374 * 375 * This function pointer is used to configure the MDIO bus for PHY 376 * access before initiating regular PHY operations. It enables either 377 * SPI/I2C or side MDIO access modes by unlocking necessary registers 378 * and setting up access permissions for the selected mode. 379 * 380 * Return: 381 * - 0 on success. 382 * - Negative error code on failure. 383 */ 384 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio); 385 386 /** 387 * @create_phy_addr_map: Function pointer to create a port-to-PHY 388 * address map. 389 * @dev: Pointer to device structure. 390 * @side_mdio: Boolean indicating if the PHYs are accessed over a side 391 * MDIO bus. 392 * 393 * This function pointer is responsible for mapping switch ports to PHY 394 * addresses according to the configured access mode (SPI or side MDIO) 395 * and the device’s strap configuration. The mapping setup may vary 396 * depending on the chip variant and configuration. Ensures the correct 397 * address mapping for PHY communication. 398 * 399 * Return: 400 * - 0 on success. 401 * - Negative error code on failure (e.g., invalid configuration). 402 */ 403 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio); 404 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 405 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 406 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 407 u64 *cnt); 408 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 409 u64 *dropped, u64 *cnt); 410 void (*r_mib_stat64)(struct ksz_device *dev, int port); 411 int (*vlan_filtering)(struct ksz_device *dev, int port, 412 bool flag, struct netlink_ext_ack *extack); 413 int (*vlan_add)(struct ksz_device *dev, int port, 414 const struct switchdev_obj_port_vlan *vlan, 415 struct netlink_ext_ack *extack); 416 int (*vlan_del)(struct ksz_device *dev, int port, 417 const struct switchdev_obj_port_vlan *vlan); 418 int (*mirror_add)(struct ksz_device *dev, int port, 419 struct dsa_mall_mirror_tc_entry *mirror, 420 bool ingress, struct netlink_ext_ack *extack); 421 void (*mirror_del)(struct ksz_device *dev, int port, 422 struct dsa_mall_mirror_tc_entry *mirror); 423 int (*fdb_add)(struct ksz_device *dev, int port, 424 const unsigned char *addr, u16 vid, struct dsa_db db); 425 int (*fdb_del)(struct ksz_device *dev, int port, 426 const unsigned char *addr, u16 vid, struct dsa_db db); 427 int (*fdb_dump)(struct ksz_device *dev, int port, 428 dsa_fdb_dump_cb_t *cb, void *data); 429 int (*mdb_add)(struct ksz_device *dev, int port, 430 const struct switchdev_obj_port_mdb *mdb, 431 struct dsa_db db); 432 int (*mdb_del)(struct ksz_device *dev, int port, 433 const struct switchdev_obj_port_mdb *mdb, 434 struct dsa_db db); 435 void (*get_caps)(struct ksz_device *dev, int port, 436 struct phylink_config *config); 437 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 438 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 439 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 440 u8 *data); 441 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 442 u8 data); 443 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 444 void (*port_init_cnt)(struct ksz_device *dev, int port); 445 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 446 unsigned int mode, 447 phy_interface_t interface, 448 struct phy_device *phydev, int speed, 449 int duplex, bool tx_pause, bool rx_pause); 450 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 451 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 452 void (*config_cpu_port)(struct dsa_switch *ds); 453 int (*enable_stp_addr)(struct ksz_device *dev); 454 int (*reset)(struct ksz_device *dev); 455 int (*init)(struct ksz_device *dev); 456 void (*exit)(struct ksz_device *dev); 457 458 int (*pcs_create)(struct ksz_device *dev); 459 }; 460 461 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 462 int ksz_switch_register(struct ksz_device *dev); 463 void ksz_switch_remove(struct ksz_device *dev); 464 int ksz_switch_suspend(struct device *dev); 465 int ksz_switch_resume(struct device *dev); 466 467 void ksz_init_mib_timer(struct ksz_device *dev); 468 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 469 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 470 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 471 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 472 bool ksz_get_gbit(struct ksz_device *dev, int port); 473 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 474 extern const struct ksz_chip_data ksz_switch_chips[]; 475 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 476 struct netlink_ext_ack *extack); 477 void ksz_switch_macaddr_put(struct dsa_switch *ds); 478 void ksz_switch_shutdown(struct ksz_device *dev); 479 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 480 481 /* Common register access functions */ 482 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 483 { 484 return dev->regmap[KSZ_REGMAP_8]; 485 } 486 487 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 488 { 489 return dev->regmap[KSZ_REGMAP_16]; 490 } 491 492 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 493 { 494 return dev->regmap[KSZ_REGMAP_32]; 495 } 496 497 static inline bool ksz_is_ksz8463(struct ksz_device *dev) 498 { 499 return dev->chip_id == KSZ8463_CHIP_ID; 500 } 501 502 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 503 { 504 unsigned int value; 505 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 506 507 if (ret) 508 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 509 ERR_PTR(ret)); 510 511 *val = value; 512 return ret; 513 } 514 515 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 516 { 517 unsigned int value; 518 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 519 520 if (ret) 521 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 522 ERR_PTR(ret)); 523 524 *val = value; 525 return ret; 526 } 527 528 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 529 { 530 unsigned int value; 531 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 532 533 if (ret) 534 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 535 ERR_PTR(ret)); 536 537 *val = value; 538 return ret; 539 } 540 541 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 542 { 543 u32 value[2]; 544 int ret; 545 546 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 547 if (ret) 548 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 549 ERR_PTR(ret)); 550 else 551 *val = (u64)value[0] << 32 | value[1]; 552 553 return ret; 554 } 555 556 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 557 { 558 int ret; 559 560 ret = regmap_write(ksz_regmap_8(dev), reg, value); 561 if (ret) 562 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 563 ERR_PTR(ret)); 564 565 return ret; 566 } 567 568 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 569 { 570 int ret; 571 572 ret = regmap_write(ksz_regmap_16(dev), reg, value); 573 if (ret) 574 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 575 ERR_PTR(ret)); 576 577 return ret; 578 } 579 580 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 581 { 582 int ret; 583 584 ret = regmap_write(ksz_regmap_32(dev), reg, value); 585 if (ret) 586 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 587 ERR_PTR(ret)); 588 589 return ret; 590 } 591 592 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 593 u16 value) 594 { 595 int ret; 596 597 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 598 if (ret) 599 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 600 ERR_PTR(ret)); 601 602 return ret; 603 } 604 605 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 606 u32 value) 607 { 608 int ret; 609 610 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 611 if (ret) 612 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 613 ERR_PTR(ret)); 614 615 return ret; 616 } 617 618 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 619 { 620 u32 val[2]; 621 622 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 623 value = swab64(value); 624 val[0] = swab32(value & 0xffffffffULL); 625 val[1] = swab32(value >> 32ULL); 626 627 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 628 } 629 630 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 631 { 632 int ret; 633 634 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 635 if (ret) 636 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 637 ERR_PTR(ret)); 638 639 return ret; 640 } 641 642 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 643 u8 *data) 644 { 645 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 646 } 647 648 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 649 u16 *data) 650 { 651 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 652 } 653 654 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 655 u32 *data) 656 { 657 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 658 } 659 660 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 661 u8 data) 662 { 663 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 664 } 665 666 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 667 u16 data) 668 { 669 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 670 data); 671 } 672 673 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 674 u32 data) 675 { 676 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 677 data); 678 } 679 680 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 681 u8 mask, u8 val) 682 { 683 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 684 mask, val); 685 } 686 687 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 688 u32 mask, u32 val) 689 { 690 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 691 mask, val); 692 } 693 694 static inline void ksz_regmap_lock(void *__mtx) 695 { 696 struct mutex *mtx = __mtx; 697 mutex_lock(mtx); 698 } 699 700 static inline void ksz_regmap_unlock(void *__mtx) 701 { 702 struct mutex *mtx = __mtx; 703 mutex_unlock(mtx); 704 } 705 706 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 707 { 708 return dev->chip_id == KSZ8795_CHIP_ID || 709 dev->chip_id == KSZ8794_CHIP_ID || 710 dev->chip_id == KSZ8765_CHIP_ID; 711 } 712 713 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 714 { 715 return dev->chip_id == KSZ88X3_CHIP_ID; 716 } 717 718 static inline bool ksz_is_8895_family(struct ksz_device *dev) 719 { 720 return dev->chip_id == KSZ8895_CHIP_ID || 721 dev->chip_id == KSZ8864_CHIP_ID; 722 } 723 724 static inline bool is_ksz8(struct ksz_device *dev) 725 { 726 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 727 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 728 } 729 730 static inline bool is_ksz88xx(struct ksz_device *dev) 731 { 732 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 733 ksz_is_ksz8463(dev); 734 } 735 736 static inline bool is_ksz9477(struct ksz_device *dev) 737 { 738 return dev->chip_id == KSZ9477_CHIP_ID; 739 } 740 741 static inline int is_lan937x(struct ksz_device *dev) 742 { 743 return dev->chip_id == LAN9370_CHIP_ID || 744 dev->chip_id == LAN9371_CHIP_ID || 745 dev->chip_id == LAN9372_CHIP_ID || 746 dev->chip_id == LAN9373_CHIP_ID || 747 dev->chip_id == LAN9374_CHIP_ID; 748 } 749 750 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 751 { 752 return (dev->chip_id == LAN9371_CHIP_ID || 753 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 754 } 755 756 static inline int ksz_get_sgmii_port(struct ksz_device *dev) 757 { 758 return dev->info->sgmii_port - 1; 759 } 760 761 static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 762 { 763 return dev->info->sgmii_port > 0; 764 } 765 766 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 767 { 768 return dev->info->sgmii_port == port + 1; 769 } 770 771 /* STP State Defines */ 772 #define PORT_TX_ENABLE BIT(2) 773 #define PORT_RX_ENABLE BIT(1) 774 #define PORT_LEARN_DISABLE BIT(0) 775 776 /* Switch ID Defines */ 777 #define REG_CHIP_ID0 0x00 778 779 #define SW_FAMILY_ID_M GENMASK(15, 8) 780 #define KSZ84_FAMILY_ID 0x84 781 #define KSZ87_FAMILY_ID 0x87 782 #define KSZ88_FAMILY_ID 0x88 783 #define KSZ8895_FAMILY_ID 0x95 784 785 #define KSZ8_PORT_STATUS_0 0x08 786 #define KSZ8_PORT_FIBER_MODE BIT(7) 787 788 #define SW_CHIP_ID_M GENMASK(7, 4) 789 #define KSZ87_CHIP_ID_94 0x6 790 #define KSZ87_CHIP_ID_95 0x9 791 #define KSZ88_CHIP_ID_63 0x3 792 #define KSZ8895_CHIP_ID_95 0x4 793 #define KSZ8895_CHIP_ID_95R 0x6 794 795 /* KSZ8895 specific register */ 796 #define REG_KSZ8864_CHIP_ID 0xFE 797 #define SW_KSZ8864 BIT(7) 798 799 #define SW_REV_ID_M GENMASK(7, 4) 800 801 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 802 #define REG_CHIP_ID4 0x0f 803 #define SKU_ID_KSZ8563 0x3c 804 #define SKU_ID_KSZ9563 0x1c 805 806 /* Driver set switch broadcast storm protection at 10% rate. */ 807 #define BROADCAST_STORM_PROT_RATE 10 808 809 /* 148,800 frames * 67 ms / 100 */ 810 #define BROADCAST_STORM_VALUE 9969 811 812 #define BROADCAST_STORM_RATE_HI 0x07 813 #define BROADCAST_STORM_RATE_LO 0xFF 814 #define BROADCAST_STORM_RATE 0x07FF 815 816 #define MULTICAST_STORM_DISABLE BIT(6) 817 818 #define SW_START 0x01 819 820 /* xMII configuration */ 821 #define P_MII_DUPLEX_M BIT(6) 822 #define P_MII_100MBIT_M BIT(4) 823 824 #define P_GMII_1GBIT_M BIT(6) 825 #define P_RGMII_ID_IG_ENABLE BIT(4) 826 #define P_RGMII_ID_EG_ENABLE BIT(3) 827 #define P_MII_MAC_MODE BIT(2) 828 #define P_MII_SEL_M 0x3 829 830 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 831 #define PME_WOL_MAGICPKT BIT(2) 832 #define PME_WOL_LINKUP BIT(1) 833 #define PME_WOL_ENERGY BIT(0) 834 835 #define PME_ENABLE BIT(1) 836 #define PME_POLARITY BIT(0) 837 838 #define KSZ87XX_REG_INT_EN 0x7D 839 #define KSZ87XX_INT_PME_MASK BIT(4) 840 841 /* Interrupt */ 842 #define REG_SW_PORT_INT_STATUS__1 0x001B 843 #define REG_SW_PORT_INT_MASK__1 0x001F 844 845 #define REG_PORT_INT_STATUS 0x001B 846 #define REG_PORT_INT_MASK 0x001F 847 848 #define PORT_SRC_PHY_INT 1 849 #define PORT_SRC_PTP_INT 2 850 851 #define KSZ8795_HUGE_PACKET_SIZE 2000 852 #define KSZ8863_HUGE_PACKET_SIZE 1916 853 #define KSZ8863_NORMAL_PACKET_SIZE 1536 854 #define KSZ8_LEGAL_PACKET_SIZE 1518 855 #define KSZ9477_MAX_FRAME_SIZE 9000 856 857 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 858 /* Drive Strength of I/O Pad 859 * 0: 8mA, 1: 16mA 860 */ 861 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 862 863 #define KSZ8795_REG_SW_CTRL_20 0xa3 864 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 865 #define SW_DRIVE_STRENGTH_M 0x7 866 #define SW_DRIVE_STRENGTH_2MA 0 867 #define SW_DRIVE_STRENGTH_4MA 1 868 #define SW_DRIVE_STRENGTH_8MA 2 869 #define SW_DRIVE_STRENGTH_12MA 3 870 #define SW_DRIVE_STRENGTH_16MA 4 871 #define SW_DRIVE_STRENGTH_20MA 5 872 #define SW_DRIVE_STRENGTH_24MA 6 873 #define SW_DRIVE_STRENGTH_28MA 7 874 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 875 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 876 877 /* TXQ Split Control Register for per-port, per-queue configuration. 878 * Register 0xAF is TXQ Split for Q3 on Port 1. 879 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 880 * where: port = 0..2, queue = 0..3 881 */ 882 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 883 (0xAF + ((port) * 4) + (3 - (queue))) 884 885 /* Bit 7 selects between: 886 * 0 = Strict priority mode (highest-priority queue first) 887 * 1 = Weighted Fair Queuing (WFQ) mode: 888 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 889 * If any queues are empty, weight is redistributed. 890 * 891 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 892 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 893 */ 894 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 895 896 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 897 #define KSZ9477_OUT_RATE_NO_LIMIT 0 898 899 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 900 901 #define KSZ9477_PORT_TC_MAP_S 4 902 903 /* CBS related registers */ 904 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 905 906 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 907 908 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 909 #define MTI_SCHEDULE_STRICT_PRIO 0 910 #define MTI_SCHEDULE_WRR 2 911 #define MTI_SHAPING_M GENMASK(5, 4) 912 #define MTI_SHAPING_OFF 0 913 #define MTI_SHAPING_SRP 1 914 #define MTI_SHAPING_TIME_AWARE 2 915 916 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 917 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 918 919 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 920 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 921 922 /* Regmap tables generation */ 923 #define KSZ_SPI_OP_RD 3 924 #define KSZ_SPI_OP_WR 2 925 926 #define swabnot_used(x) 0 927 928 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 929 swab##swp((opcode) << ((regbits) + (regpad))) 930 931 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 932 { \ 933 .name = #width, \ 934 .val_bits = (width), \ 935 .reg_stride = 1, \ 936 .reg_bits = (regbits) + (regalign), \ 937 .pad_bits = (regpad), \ 938 .max_register = BIT(regbits) - 1, \ 939 .cache_type = REGCACHE_NONE, \ 940 .read_flag_mask = \ 941 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 942 regbits, regpad), \ 943 .write_flag_mask = \ 944 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 945 regbits, regpad), \ 946 .lock = ksz_regmap_lock, \ 947 .unlock = ksz_regmap_unlock, \ 948 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 949 .val_format_endian = REGMAP_ENDIAN_BIG \ 950 } 951 952 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 953 static const struct regmap_config ksz##_regmap_config[] = { \ 954 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 955 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 956 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 957 } 958 959 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 960 { \ 961 .name = #width, \ 962 .val_bits = (width), \ 963 .reg_stride = (width / 8), \ 964 .reg_bits = (regbits) + (regalign), \ 965 .pad_bits = (regpad), \ 966 .read = ksz8463_spi_read, \ 967 .write = ksz8463_spi_write, \ 968 .max_register = BIT(regbits) - 1, \ 969 .cache_type = REGCACHE_NONE, \ 970 .zero_flag_mask = 1, \ 971 .use_single_read = 1, \ 972 .use_single_write = 1, \ 973 .lock = ksz_regmap_lock, \ 974 .unlock = ksz_regmap_unlock, \ 975 } 976 977 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 978 static const struct regmap_config ksz##_regmap_config[] = { \ 979 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 980 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 981 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 982 } 983 984 #endif 985