1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/clk-provider.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
15
16 #include "common.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-alpha-pll.h"
20 #include "clk-rcg.h"
21 #include "clk-branch.h"
22 #include "reset.h"
23 #include "gdsc.h"
24
25 enum {
26 P_XO,
27 P_GPLL0,
28 P_GPLL0_DIV,
29 P_MMPLL0_OUT_EVEN,
30 P_MMPLL1_OUT_EVEN,
31 P_MMPLL3_OUT_EVEN,
32 P_MMPLL4_OUT_EVEN,
33 P_MMPLL5_OUT_EVEN,
34 P_MMPLL6_OUT_EVEN,
35 P_MMPLL7_OUT_EVEN,
36 P_MMPLL10_OUT_EVEN,
37 P_DSI0PLL,
38 P_DSI1PLL,
39 P_DSI0PLL_BYTE,
40 P_DSI1PLL_BYTE,
41 P_HDMIPLL,
42 P_DPVCO,
43 P_DPLINK,
44 };
45
46 static const struct clk_div_table post_div_table_fabia_even[] = {
47 { 0x0, 1 },
48 { 0x1, 2 },
49 { 0x3, 4 },
50 { 0x7, 8 },
51 { }
52 };
53
54 static struct clk_alpha_pll mmpll0 = {
55 .offset = 0xc000,
56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
57 .clkr = {
58 .enable_reg = 0x1e0,
59 .enable_mask = BIT(0),
60 .hw.init = &(struct clk_init_data){
61 .name = "mmpll0",
62 .parent_data = &(const struct clk_parent_data){
63 .fw_name = "xo"
64 },
65 .num_parents = 1,
66 .ops = &clk_alpha_pll_fixed_fabia_ops,
67 },
68 },
69 };
70
71 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
72 .offset = 0xc000,
73 .post_div_shift = 8,
74 .post_div_table = post_div_table_fabia_even,
75 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
76 .width = 4,
77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
78 .clkr.hw.init = &(struct clk_init_data){
79 .name = "mmpll0_out_even",
80 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
81 .num_parents = 1,
82 .ops = &clk_alpha_pll_postdiv_fabia_ops,
83 },
84 };
85
86 static struct clk_alpha_pll mmpll1 = {
87 .offset = 0xc050,
88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
89 .clkr = {
90 .enable_reg = 0x1e0,
91 .enable_mask = BIT(1),
92 .hw.init = &(struct clk_init_data){
93 .name = "mmpll1",
94 .parent_data = &(const struct clk_parent_data){
95 .fw_name = "xo"
96 },
97 .num_parents = 1,
98 .ops = &clk_alpha_pll_fixed_fabia_ops,
99 },
100 },
101 };
102
103 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
104 .offset = 0xc050,
105 .post_div_shift = 8,
106 .post_div_table = post_div_table_fabia_even,
107 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
108 .width = 4,
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
110 .clkr.hw.init = &(struct clk_init_data){
111 .name = "mmpll1_out_even",
112 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
113 .num_parents = 1,
114 .ops = &clk_alpha_pll_postdiv_fabia_ops,
115 },
116 };
117
118 static struct clk_alpha_pll mmpll3 = {
119 .offset = 0x0,
120 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
121 .clkr.hw.init = &(struct clk_init_data){
122 .name = "mmpll3",
123 .parent_data = &(const struct clk_parent_data){
124 .fw_name = "xo"
125 },
126 .num_parents = 1,
127 .ops = &clk_alpha_pll_fixed_fabia_ops,
128 },
129 };
130
131 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
132 .offset = 0x0,
133 .post_div_shift = 8,
134 .post_div_table = post_div_table_fabia_even,
135 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
136 .width = 4,
137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
138 .clkr.hw.init = &(struct clk_init_data){
139 .name = "mmpll3_out_even",
140 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
141 .num_parents = 1,
142 .ops = &clk_alpha_pll_postdiv_fabia_ops,
143 },
144 };
145
146 static struct clk_alpha_pll mmpll4 = {
147 .offset = 0x50,
148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
149 .clkr.hw.init = &(struct clk_init_data){
150 .name = "mmpll4",
151 .parent_data = &(const struct clk_parent_data){
152 .fw_name = "xo"
153 },
154 .num_parents = 1,
155 .ops = &clk_alpha_pll_fixed_fabia_ops,
156 },
157 };
158
159 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
160 .offset = 0x50,
161 .post_div_shift = 8,
162 .post_div_table = post_div_table_fabia_even,
163 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
164 .width = 4,
165 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "mmpll4_out_even",
168 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
169 .num_parents = 1,
170 .ops = &clk_alpha_pll_postdiv_fabia_ops,
171 },
172 };
173
174 static struct clk_alpha_pll mmpll5 = {
175 .offset = 0xa0,
176 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
177 .clkr.hw.init = &(struct clk_init_data){
178 .name = "mmpll5",
179 .parent_data = &(const struct clk_parent_data){
180 .fw_name = "xo"
181 },
182 .num_parents = 1,
183 .ops = &clk_alpha_pll_fixed_fabia_ops,
184 },
185 };
186
187 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
188 .offset = 0xa0,
189 .post_div_shift = 8,
190 .post_div_table = post_div_table_fabia_even,
191 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
192 .width = 4,
193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
194 .clkr.hw.init = &(struct clk_init_data){
195 .name = "mmpll5_out_even",
196 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
197 .num_parents = 1,
198 .ops = &clk_alpha_pll_postdiv_fabia_ops,
199 },
200 };
201
202 static struct clk_alpha_pll mmpll6 = {
203 .offset = 0xf0,
204 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
205 .clkr.hw.init = &(struct clk_init_data){
206 .name = "mmpll6",
207 .parent_data = &(const struct clk_parent_data){
208 .fw_name = "xo"
209 },
210 .num_parents = 1,
211 .ops = &clk_alpha_pll_fixed_fabia_ops,
212 },
213 };
214
215 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
216 .offset = 0xf0,
217 .post_div_shift = 8,
218 .post_div_table = post_div_table_fabia_even,
219 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
220 .width = 4,
221 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
222 .clkr.hw.init = &(struct clk_init_data){
223 .name = "mmpll6_out_even",
224 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
225 .num_parents = 1,
226 .ops = &clk_alpha_pll_postdiv_fabia_ops,
227 },
228 };
229
230 static struct clk_alpha_pll mmpll7 = {
231 .offset = 0x140,
232 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
233 .clkr.hw.init = &(struct clk_init_data){
234 .name = "mmpll7",
235 .parent_data = &(const struct clk_parent_data){
236 .fw_name = "xo"
237 },
238 .num_parents = 1,
239 .ops = &clk_alpha_pll_fixed_fabia_ops,
240 },
241 };
242
243 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
244 .offset = 0x140,
245 .post_div_shift = 8,
246 .post_div_table = post_div_table_fabia_even,
247 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
248 .width = 4,
249 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
250 .clkr.hw.init = &(struct clk_init_data){
251 .name = "mmpll7_out_even",
252 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
253 .num_parents = 1,
254 .ops = &clk_alpha_pll_postdiv_fabia_ops,
255 },
256 };
257
258 static struct clk_alpha_pll mmpll10 = {
259 .offset = 0x190,
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
261 .clkr.hw.init = &(struct clk_init_data){
262 .name = "mmpll10",
263 .parent_data = &(const struct clk_parent_data){
264 .fw_name = "xo"
265 },
266 .num_parents = 1,
267 .ops = &clk_alpha_pll_fixed_fabia_ops,
268 },
269 };
270
271 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
272 .offset = 0x190,
273 .post_div_shift = 8,
274 .post_div_table = post_div_table_fabia_even,
275 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
276 .width = 4,
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
278 .clkr.hw.init = &(struct clk_init_data){
279 .name = "mmpll10_out_even",
280 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
281 .num_parents = 1,
282 .ops = &clk_alpha_pll_postdiv_fabia_ops,
283 },
284 };
285
286 static const struct parent_map mmss_xo_hdmi_map[] = {
287 { P_XO, 0 },
288 { P_HDMIPLL, 1 },
289 };
290
291 static const struct clk_parent_data mmss_xo_hdmi[] = {
292 { .fw_name = "xo" },
293 { .fw_name = "hdmipll" },
294 };
295
296 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
297 { P_XO, 0 },
298 { P_DSI0PLL, 1 },
299 { P_DSI1PLL, 2 },
300 };
301
302 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
303 { .fw_name = "xo" },
304 { .fw_name = "dsi0dsi" },
305 { .fw_name = "dsi1dsi" },
306 };
307
308 static const struct parent_map mmss_xo_dsibyte_map[] = {
309 { P_XO, 0 },
310 { P_DSI0PLL_BYTE, 1 },
311 { P_DSI1PLL_BYTE, 2 },
312 };
313
314 static const struct clk_parent_data mmss_xo_dsibyte[] = {
315 { .fw_name = "xo" },
316 { .fw_name = "dsi0byte" },
317 { .fw_name = "dsi1byte" },
318 };
319
320 static const struct parent_map mmss_xo_dp_map[] = {
321 { P_XO, 0 },
322 { P_DPLINK, 1 },
323 { P_DPVCO, 2 },
324 };
325
326 static const struct clk_parent_data mmss_xo_dp[] = {
327 { .fw_name = "xo" },
328 { .fw_name = "dplink" },
329 { .fw_name = "dpvco" },
330 };
331
332 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
333 { P_XO, 0 },
334 { P_GPLL0, 5 },
335 { P_GPLL0_DIV, 6 },
336 };
337
338 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
339 { .fw_name = "xo" },
340 { .fw_name = "gpll0" },
341 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
342 };
343
344 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
345 { P_XO, 0 },
346 { P_MMPLL0_OUT_EVEN, 1 },
347 { P_GPLL0, 5 },
348 { P_GPLL0_DIV, 6 },
349 };
350
351 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
352 { .fw_name = "xo" },
353 { .hw = &mmpll0_out_even.clkr.hw },
354 { .fw_name = "gpll0" },
355 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
356 };
357
358 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
359 { P_XO, 0 },
360 { P_MMPLL0_OUT_EVEN, 1 },
361 { P_MMPLL1_OUT_EVEN, 2 },
362 { P_GPLL0, 5 },
363 { P_GPLL0_DIV, 6 },
364 };
365
366 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
367 { .fw_name = "xo" },
368 { .hw = &mmpll0_out_even.clkr.hw },
369 { .hw = &mmpll1_out_even.clkr.hw },
370 { .fw_name = "gpll0" },
371 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
372 };
373
374 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
375 { P_XO, 0 },
376 { P_MMPLL0_OUT_EVEN, 1 },
377 { P_MMPLL5_OUT_EVEN, 2 },
378 { P_GPLL0, 5 },
379 { P_GPLL0_DIV, 6 },
380 };
381
382 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
383 { .fw_name = "xo" },
384 { .hw = &mmpll0_out_even.clkr.hw },
385 { .hw = &mmpll5_out_even.clkr.hw },
386 { .fw_name = "gpll0" },
387 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
388 };
389
390 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
391 { P_XO, 0 },
392 { P_MMPLL0_OUT_EVEN, 1 },
393 { P_MMPLL3_OUT_EVEN, 3 },
394 { P_MMPLL6_OUT_EVEN, 4 },
395 { P_GPLL0, 5 },
396 { P_GPLL0_DIV, 6 },
397 };
398
399 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
400 { .fw_name = "xo" },
401 { .hw = &mmpll0_out_even.clkr.hw },
402 { .hw = &mmpll3_out_even.clkr.hw },
403 { .hw = &mmpll6_out_even.clkr.hw },
404 { .fw_name = "gpll0" },
405 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
406 };
407
408 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
409 { P_XO, 0 },
410 { P_MMPLL4_OUT_EVEN, 1 },
411 { P_MMPLL7_OUT_EVEN, 2 },
412 { P_MMPLL10_OUT_EVEN, 3 },
413 { P_GPLL0, 5 },
414 { P_GPLL0_DIV, 6 },
415 };
416
417 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
418 { .fw_name = "xo" },
419 { .hw = &mmpll4_out_even.clkr.hw },
420 { .hw = &mmpll7_out_even.clkr.hw },
421 { .hw = &mmpll10_out_even.clkr.hw },
422 { .fw_name = "gpll0" },
423 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
424 };
425
426 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
427 { P_XO, 0 },
428 { P_MMPLL0_OUT_EVEN, 1 },
429 { P_MMPLL7_OUT_EVEN, 2 },
430 { P_MMPLL10_OUT_EVEN, 3 },
431 { P_GPLL0, 5 },
432 { P_GPLL0_DIV, 6 },
433 };
434
435 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
436 { .fw_name = "xo" },
437 { .hw = &mmpll0_out_even.clkr.hw },
438 { .hw = &mmpll7_out_even.clkr.hw },
439 { .hw = &mmpll10_out_even.clkr.hw },
440 { .fw_name = "gpll0" },
441 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
442 };
443
444 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
445 { P_XO, 0 },
446 { P_MMPLL0_OUT_EVEN, 1 },
447 { P_MMPLL4_OUT_EVEN, 2 },
448 { P_MMPLL7_OUT_EVEN, 3 },
449 { P_MMPLL10_OUT_EVEN, 4 },
450 { P_GPLL0, 5 },
451 { P_GPLL0_DIV, 6 },
452 };
453
454 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
455 { .fw_name = "xo" },
456 { .hw = &mmpll0_out_even.clkr.hw },
457 { .hw = &mmpll4_out_even.clkr.hw },
458 { .hw = &mmpll7_out_even.clkr.hw },
459 { .hw = &mmpll10_out_even.clkr.hw },
460 { .fw_name = "gpll0" },
461 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
462 };
463
464 static struct clk_rcg2 byte0_clk_src = {
465 .cmd_rcgr = 0x2120,
466 .hid_width = 5,
467 .parent_map = mmss_xo_dsibyte_map,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "byte0_clk_src",
470 .parent_data = mmss_xo_dsibyte,
471 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
472 .ops = &clk_byte2_ops,
473 .flags = CLK_SET_RATE_PARENT,
474 },
475 };
476
477 static struct clk_rcg2 byte1_clk_src = {
478 .cmd_rcgr = 0x2140,
479 .hid_width = 5,
480 .parent_map = mmss_xo_dsibyte_map,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "byte1_clk_src",
483 .parent_data = mmss_xo_dsibyte,
484 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
485 .ops = &clk_byte2_ops,
486 .flags = CLK_SET_RATE_PARENT,
487 },
488 };
489
490 static const struct freq_tbl ftbl_cci_clk_src[] = {
491 F(37500000, P_GPLL0, 16, 0, 0),
492 F(50000000, P_GPLL0, 12, 0, 0),
493 F(100000000, P_GPLL0, 6, 0, 0),
494 { }
495 };
496
497 static struct clk_rcg2 cci_clk_src = {
498 .cmd_rcgr = 0x3300,
499 .hid_width = 5,
500 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
501 .freq_tbl = ftbl_cci_clk_src,
502 .clkr.hw.init = &(struct clk_init_data){
503 .name = "cci_clk_src",
504 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
505 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
506 .ops = &clk_rcg2_ops,
507 },
508 };
509
510 static const struct freq_tbl ftbl_cpp_clk_src[] = {
511 F(100000000, P_GPLL0, 6, 0, 0),
512 F(200000000, P_GPLL0, 3, 0, 0),
513 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
514 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
515 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
516 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
517 F(600000000, P_GPLL0, 1, 0, 0),
518 { }
519 };
520
521 static struct clk_rcg2 cpp_clk_src = {
522 .cmd_rcgr = 0x3640,
523 .hid_width = 5,
524 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
525 .freq_tbl = ftbl_cpp_clk_src,
526 .clkr.hw.init = &(struct clk_init_data){
527 .name = "cpp_clk_src",
528 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
529 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
530 .ops = &clk_rcg2_ops,
531 },
532 };
533
534 static const struct freq_tbl ftbl_csi_clk_src[] = {
535 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
536 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
537 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
538 F(300000000, P_GPLL0, 2, 0, 0),
539 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
540 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
541 { }
542 };
543
544 static struct clk_rcg2 csi0_clk_src = {
545 .cmd_rcgr = 0x3090,
546 .hid_width = 5,
547 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
548 .freq_tbl = ftbl_csi_clk_src,
549 .clkr.hw.init = &(struct clk_init_data){
550 .name = "csi0_clk_src",
551 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
552 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
553 .ops = &clk_rcg2_ops,
554 },
555 };
556
557 static struct clk_rcg2 csi1_clk_src = {
558 .cmd_rcgr = 0x3100,
559 .hid_width = 5,
560 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
561 .freq_tbl = ftbl_csi_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "csi1_clk_src",
564 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
565 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
566 .ops = &clk_rcg2_ops,
567 },
568 };
569
570 static struct clk_rcg2 csi2_clk_src = {
571 .cmd_rcgr = 0x3160,
572 .hid_width = 5,
573 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
574 .freq_tbl = ftbl_csi_clk_src,
575 .clkr.hw.init = &(struct clk_init_data){
576 .name = "csi2_clk_src",
577 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
578 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
579 .ops = &clk_rcg2_ops,
580 },
581 };
582
583 static struct clk_rcg2 csi3_clk_src = {
584 .cmd_rcgr = 0x31c0,
585 .hid_width = 5,
586 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
587 .freq_tbl = ftbl_csi_clk_src,
588 .clkr.hw.init = &(struct clk_init_data){
589 .name = "csi3_clk_src",
590 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
591 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
592 .ops = &clk_rcg2_ops,
593 },
594 };
595
596 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
597 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
598 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
599 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
600 F(300000000, P_GPLL0, 2, 0, 0),
601 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
602 { }
603 };
604
605 static struct clk_rcg2 csiphy_clk_src = {
606 .cmd_rcgr = 0x3800,
607 .hid_width = 5,
608 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
609 .freq_tbl = ftbl_csiphy_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "csiphy_clk_src",
612 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
613 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
614 .ops = &clk_rcg2_ops,
615 },
616 };
617
618 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
619 F(200000000, P_GPLL0, 3, 0, 0),
620 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
621 { }
622 };
623
624 static struct clk_rcg2 csi0phytimer_clk_src = {
625 .cmd_rcgr = 0x3000,
626 .hid_width = 5,
627 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
628 .freq_tbl = ftbl_csiphytimer_clk_src,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "csi0phytimer_clk_src",
631 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
632 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
633 .ops = &clk_rcg2_ops,
634 },
635 };
636
637 static struct clk_rcg2 csi1phytimer_clk_src = {
638 .cmd_rcgr = 0x3030,
639 .hid_width = 5,
640 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
641 .freq_tbl = ftbl_csiphytimer_clk_src,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "csi1phytimer_clk_src",
644 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
645 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
646 .ops = &clk_rcg2_ops,
647 },
648 };
649
650 static struct clk_rcg2 csi2phytimer_clk_src = {
651 .cmd_rcgr = 0x3060,
652 .hid_width = 5,
653 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
654 .freq_tbl = ftbl_csiphytimer_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "csi2phytimer_clk_src",
657 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
658 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
659 .ops = &clk_rcg2_ops,
660 },
661 };
662
663 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
664 F(19200000, P_XO, 1, 0, 0),
665 { }
666 };
667
668 static struct clk_rcg2 dp_aux_clk_src = {
669 .cmd_rcgr = 0x2260,
670 .hid_width = 5,
671 .parent_map = mmss_xo_gpll0_gpll0_div_map,
672 .freq_tbl = ftbl_dp_aux_clk_src,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "dp_aux_clk_src",
675 .parent_data = mmss_xo_gpll0_gpll0_div,
676 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
677 .ops = &clk_rcg2_ops,
678 },
679 };
680
681 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
682 F(101250, P_DPLINK, 1, 5, 16),
683 F(168750, P_DPLINK, 1, 5, 16),
684 F(337500, P_DPLINK, 1, 5, 16),
685 { }
686 };
687
688 static struct clk_rcg2 dp_crypto_clk_src = {
689 .cmd_rcgr = 0x2220,
690 .hid_width = 5,
691 .parent_map = mmss_xo_dp_map,
692 .freq_tbl = ftbl_dp_crypto_clk_src,
693 .clkr.hw.init = &(struct clk_init_data){
694 .name = "dp_crypto_clk_src",
695 .parent_data = mmss_xo_dp,
696 .num_parents = ARRAY_SIZE(mmss_xo_dp),
697 .ops = &clk_rcg2_ops,
698 },
699 };
700
701 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
702 F(162000, P_DPLINK, 2, 0, 0),
703 F(270000, P_DPLINK, 2, 0, 0),
704 F(540000, P_DPLINK, 2, 0, 0),
705 { }
706 };
707
708 static struct clk_rcg2 dp_link_clk_src = {
709 .cmd_rcgr = 0x2200,
710 .hid_width = 5,
711 .parent_map = mmss_xo_dp_map,
712 .freq_tbl = ftbl_dp_link_clk_src,
713 .clkr.hw.init = &(struct clk_init_data){
714 .name = "dp_link_clk_src",
715 .parent_data = mmss_xo_dp,
716 .num_parents = ARRAY_SIZE(mmss_xo_dp),
717 .ops = &clk_rcg2_ops,
718 },
719 };
720
721 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
722 F(154000000, P_DPVCO, 1, 0, 0),
723 F(337500000, P_DPVCO, 2, 0, 0),
724 F(675000000, P_DPVCO, 2, 0, 0),
725 { }
726 };
727
728 static struct clk_rcg2 dp_pixel_clk_src = {
729 .cmd_rcgr = 0x2240,
730 .hid_width = 5,
731 .parent_map = mmss_xo_dp_map,
732 .freq_tbl = ftbl_dp_pixel_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "dp_pixel_clk_src",
735 .parent_data = mmss_xo_dp,
736 .num_parents = ARRAY_SIZE(mmss_xo_dp),
737 .ops = &clk_rcg2_ops,
738 },
739 };
740
741 static const struct freq_tbl ftbl_esc_clk_src[] = {
742 F(19200000, P_XO, 1, 0, 0),
743 { }
744 };
745
746 static struct clk_rcg2 esc0_clk_src = {
747 .cmd_rcgr = 0x2160,
748 .hid_width = 5,
749 .parent_map = mmss_xo_dsibyte_map,
750 .freq_tbl = ftbl_esc_clk_src,
751 .clkr.hw.init = &(struct clk_init_data){
752 .name = "esc0_clk_src",
753 .parent_data = mmss_xo_dsibyte,
754 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
755 .ops = &clk_rcg2_ops,
756 },
757 };
758
759 static struct clk_rcg2 esc1_clk_src = {
760 .cmd_rcgr = 0x2180,
761 .hid_width = 5,
762 .parent_map = mmss_xo_dsibyte_map,
763 .freq_tbl = ftbl_esc_clk_src,
764 .clkr.hw.init = &(struct clk_init_data){
765 .name = "esc1_clk_src",
766 .parent_data = mmss_xo_dsibyte,
767 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
768 .ops = &clk_rcg2_ops,
769 },
770 };
771
772 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
773 { .src = P_HDMIPLL },
774 { }
775 };
776
777 static struct clk_rcg2 extpclk_clk_src = {
778 .cmd_rcgr = 0x2060,
779 .hid_width = 5,
780 .parent_map = mmss_xo_hdmi_map,
781 .freq_tbl = ftbl_extpclk_clk_src,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "extpclk_clk_src",
784 .parent_data = mmss_xo_hdmi,
785 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
786 .ops = &clk_byte_ops,
787 .flags = CLK_SET_RATE_PARENT,
788 },
789 };
790
791 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
792 F(100000000, P_GPLL0, 6, 0, 0),
793 F(200000000, P_GPLL0, 3, 0, 0),
794 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
795 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
796 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
797 { }
798 };
799
800 static struct clk_rcg2 fd_core_clk_src = {
801 .cmd_rcgr = 0x3b00,
802 .hid_width = 5,
803 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
804 .freq_tbl = ftbl_fd_core_clk_src,
805 .clkr.hw.init = &(struct clk_init_data){
806 .name = "fd_core_clk_src",
807 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
808 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
809 .ops = &clk_rcg2_ops,
810 },
811 };
812
813 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
814 F(19200000, P_XO, 1, 0, 0),
815 { }
816 };
817
818 static struct clk_rcg2 hdmi_clk_src = {
819 .cmd_rcgr = 0x2100,
820 .hid_width = 5,
821 .parent_map = mmss_xo_gpll0_gpll0_div_map,
822 .freq_tbl = ftbl_hdmi_clk_src,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "hdmi_clk_src",
825 .parent_data = mmss_xo_gpll0_gpll0_div,
826 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
827 .ops = &clk_rcg2_ops,
828 },
829 };
830
831 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
832 F(75000000, P_GPLL0, 8, 0, 0),
833 F(150000000, P_GPLL0, 4, 0, 0),
834 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
835 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
836 { }
837 };
838
839 static struct clk_rcg2 jpeg0_clk_src = {
840 .cmd_rcgr = 0x3500,
841 .hid_width = 5,
842 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
843 .freq_tbl = ftbl_jpeg0_clk_src,
844 .clkr.hw.init = &(struct clk_init_data){
845 .name = "jpeg0_clk_src",
846 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
847 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
848 .ops = &clk_rcg2_ops,
849 },
850 };
851
852 static const struct freq_tbl ftbl_maxi_clk_src[] = {
853 F(19200000, P_XO, 1, 0, 0),
854 F(75000000, P_GPLL0_DIV, 4, 0, 0),
855 F(171428571, P_GPLL0, 3.5, 0, 0),
856 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
857 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
858 { }
859 };
860
861 static struct clk_rcg2 maxi_clk_src = {
862 .cmd_rcgr = 0xf020,
863 .hid_width = 5,
864 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
865 .freq_tbl = ftbl_maxi_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "maxi_clk_src",
868 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
869 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
870 .ops = &clk_rcg2_ops,
871 },
872 };
873
874 static const struct freq_tbl ftbl_mclk_clk_src[] = {
875 F(4800000, P_XO, 4, 0, 0),
876 F(6000000, P_GPLL0_DIV, 10, 1, 5),
877 F(8000000, P_GPLL0_DIV, 1, 2, 75),
878 F(9600000, P_XO, 2, 0, 0),
879 F(16666667, P_GPLL0_DIV, 2, 1, 9),
880 F(19200000, P_XO, 1, 0, 0),
881 F(24000000, P_GPLL0_DIV, 1, 2, 25),
882 F(33333333, P_GPLL0_DIV, 1, 2, 9),
883 F(48000000, P_GPLL0, 1, 2, 25),
884 F(66666667, P_GPLL0, 1, 2, 9),
885 { }
886 };
887
888 static struct clk_rcg2 mclk0_clk_src = {
889 .cmd_rcgr = 0x3360,
890 .hid_width = 5,
891 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
892 .freq_tbl = ftbl_mclk_clk_src,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "mclk0_clk_src",
895 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
896 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
897 .ops = &clk_rcg2_ops,
898 },
899 };
900
901 static struct clk_rcg2 mclk1_clk_src = {
902 .cmd_rcgr = 0x3390,
903 .hid_width = 5,
904 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
905 .freq_tbl = ftbl_mclk_clk_src,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "mclk1_clk_src",
908 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
909 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
910 .ops = &clk_rcg2_ops,
911 },
912 };
913
914 static struct clk_rcg2 mclk2_clk_src = {
915 .cmd_rcgr = 0x33c0,
916 .hid_width = 5,
917 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
918 .freq_tbl = ftbl_mclk_clk_src,
919 .clkr.hw.init = &(struct clk_init_data){
920 .name = "mclk2_clk_src",
921 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
922 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
923 .ops = &clk_rcg2_ops,
924 },
925 };
926
927 static struct clk_rcg2 mclk3_clk_src = {
928 .cmd_rcgr = 0x33f0,
929 .hid_width = 5,
930 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
931 .freq_tbl = ftbl_mclk_clk_src,
932 .clkr.hw.init = &(struct clk_init_data){
933 .name = "mclk3_clk_src",
934 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
935 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
936 .ops = &clk_rcg2_ops,
937 },
938 };
939
940 static const struct freq_tbl ftbl_mdp_clk_src[] = {
941 F(85714286, P_GPLL0, 7, 0, 0),
942 F(100000000, P_GPLL0, 6, 0, 0),
943 F(150000000, P_GPLL0, 4, 0, 0),
944 F(171428571, P_GPLL0, 3.5, 0, 0),
945 F(200000000, P_GPLL0, 3, 0, 0),
946 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
947 F(300000000, P_GPLL0, 2, 0, 0),
948 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
949 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
950 { }
951 };
952
953 static struct clk_rcg2 mdp_clk_src = {
954 .cmd_rcgr = 0x2040,
955 .hid_width = 5,
956 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
957 .freq_tbl = ftbl_mdp_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "mdp_clk_src",
960 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
961 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
962 .ops = &clk_rcg2_ops,
963 },
964 };
965
966 static const struct freq_tbl ftbl_vsync_clk_src[] = {
967 F(19200000, P_XO, 1, 0, 0),
968 { }
969 };
970
971 static struct clk_rcg2 vsync_clk_src = {
972 .cmd_rcgr = 0x2080,
973 .hid_width = 5,
974 .parent_map = mmss_xo_gpll0_gpll0_div_map,
975 .freq_tbl = ftbl_vsync_clk_src,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "vsync_clk_src",
978 .parent_data = mmss_xo_gpll0_gpll0_div,
979 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
980 .ops = &clk_rcg2_ops,
981 },
982 };
983
984 static const struct freq_tbl ftbl_ahb_clk_src[] = {
985 F(19200000, P_XO, 1, 0, 0),
986 F(40000000, P_GPLL0, 15, 0, 0),
987 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
988 { }
989 };
990
991 static struct clk_rcg2 ahb_clk_src = {
992 .cmd_rcgr = 0x5000,
993 .hid_width = 5,
994 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
995 .freq_tbl = ftbl_ahb_clk_src,
996 .clkr.hw.init = &(struct clk_init_data){
997 .name = "ahb_clk_src",
998 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
999 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
1000 .ops = &clk_rcg2_ops,
1001 },
1002 };
1003
1004 static const struct freq_tbl ftbl_axi_clk_src[] = {
1005 F(75000000, P_GPLL0, 8, 0, 0),
1006 F(171428571, P_GPLL0, 3.5, 0, 0),
1007 F(240000000, P_GPLL0, 2.5, 0, 0),
1008 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1009 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1010 { }
1011 };
1012
1013 /* RO to linux */
1014 static struct clk_rcg2 axi_clk_src = {
1015 .cmd_rcgr = 0xd000,
1016 .hid_width = 5,
1017 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1018 .freq_tbl = ftbl_axi_clk_src,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "axi_clk_src",
1021 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1022 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
1023 .ops = &clk_rcg2_ops,
1024 },
1025 };
1026
1027 static struct clk_rcg2 pclk0_clk_src = {
1028 .cmd_rcgr = 0x2000,
1029 .mnd_width = 8,
1030 .hid_width = 5,
1031 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1032 .clkr.hw.init = &(struct clk_init_data){
1033 .name = "pclk0_clk_src",
1034 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1035 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1036 .ops = &clk_pixel_ops,
1037 .flags = CLK_SET_RATE_PARENT,
1038 },
1039 };
1040
1041 static struct clk_rcg2 pclk1_clk_src = {
1042 .cmd_rcgr = 0x2020,
1043 .mnd_width = 8,
1044 .hid_width = 5,
1045 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1046 .clkr.hw.init = &(struct clk_init_data){
1047 .name = "pclk1_clk_src",
1048 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1049 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1050 .ops = &clk_pixel_ops,
1051 .flags = CLK_SET_RATE_PARENT,
1052 },
1053 };
1054
1055 static const struct freq_tbl ftbl_rot_clk_src[] = {
1056 F(171428571, P_GPLL0, 3.5, 0, 0),
1057 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1058 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1059 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1060 { }
1061 };
1062
1063 static struct clk_rcg2 rot_clk_src = {
1064 .cmd_rcgr = 0x21a0,
1065 .hid_width = 5,
1066 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1067 .freq_tbl = ftbl_rot_clk_src,
1068 .clkr.hw.init = &(struct clk_init_data){
1069 .name = "rot_clk_src",
1070 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1071 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1072 .ops = &clk_rcg2_ops,
1073 },
1074 };
1075
1076 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1077 F(200000000, P_GPLL0, 3, 0, 0),
1078 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1079 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1080 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1081 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1082 { }
1083 };
1084
1085 static struct clk_rcg2 video_core_clk_src = {
1086 .cmd_rcgr = 0x1000,
1087 .hid_width = 5,
1088 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1089 .freq_tbl = ftbl_video_core_clk_src,
1090 .clkr.hw.init = &(struct clk_init_data){
1091 .name = "video_core_clk_src",
1092 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1093 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1094 .ops = &clk_rcg2_ops,
1095 },
1096 };
1097
1098 static struct clk_rcg2 video_subcore0_clk_src = {
1099 .cmd_rcgr = 0x1060,
1100 .hid_width = 5,
1101 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1102 .freq_tbl = ftbl_video_core_clk_src,
1103 .clkr.hw.init = &(struct clk_init_data){
1104 .name = "video_subcore0_clk_src",
1105 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1106 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1107 .ops = &clk_rcg2_ops,
1108 },
1109 };
1110
1111 static struct clk_rcg2 video_subcore1_clk_src = {
1112 .cmd_rcgr = 0x1080,
1113 .hid_width = 5,
1114 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1115 .freq_tbl = ftbl_video_core_clk_src,
1116 .clkr.hw.init = &(struct clk_init_data){
1117 .name = "video_subcore1_clk_src",
1118 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1119 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1120 .ops = &clk_rcg2_ops,
1121 },
1122 };
1123
1124 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1125 F(200000000, P_GPLL0, 3, 0, 0),
1126 F(300000000, P_GPLL0, 2, 0, 0),
1127 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1128 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1129 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1130 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1131 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1132 F(600000000, P_GPLL0, 1, 0, 0),
1133 { }
1134 };
1135
1136 static struct clk_rcg2 vfe0_clk_src = {
1137 .cmd_rcgr = 0x3600,
1138 .hid_width = 5,
1139 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1140 .freq_tbl = ftbl_vfe_clk_src,
1141 .clkr.hw.init = &(struct clk_init_data){
1142 .name = "vfe0_clk_src",
1143 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1144 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1145 .ops = &clk_rcg2_ops,
1146 },
1147 };
1148
1149 static struct clk_rcg2 vfe1_clk_src = {
1150 .cmd_rcgr = 0x3620,
1151 .hid_width = 5,
1152 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1153 .freq_tbl = ftbl_vfe_clk_src,
1154 .clkr.hw.init = &(struct clk_init_data){
1155 .name = "vfe1_clk_src",
1156 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1157 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1158 .ops = &clk_rcg2_ops,
1159 },
1160 };
1161
1162 static struct clk_branch misc_ahb_clk = {
1163 .halt_reg = 0x328,
1164 .hwcg_reg = 0x328,
1165 .hwcg_bit = 1,
1166 .clkr = {
1167 .enable_reg = 0x328,
1168 .enable_mask = BIT(0),
1169 .hw.init = &(struct clk_init_data){
1170 .name = "misc_ahb_clk",
1171 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1172 .num_parents = 1,
1173 .ops = &clk_branch2_ops,
1174 .flags = CLK_SET_RATE_PARENT,
1175 },
1176 },
1177 };
1178
1179 static struct clk_branch video_core_clk = {
1180 .halt_reg = 0x1028,
1181 .clkr = {
1182 .enable_reg = 0x1028,
1183 .enable_mask = BIT(0),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "video_core_clk",
1186 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1187 .num_parents = 1,
1188 .ops = &clk_branch2_ops,
1189 .flags = CLK_SET_RATE_PARENT,
1190 },
1191 },
1192 };
1193
1194 static struct clk_branch video_ahb_clk = {
1195 .halt_reg = 0x1030,
1196 .hwcg_reg = 0x1030,
1197 .hwcg_bit = 1,
1198 .clkr = {
1199 .enable_reg = 0x1030,
1200 .enable_mask = BIT(0),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "video_ahb_clk",
1203 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1204 .num_parents = 1,
1205 .ops = &clk_branch2_ops,
1206 .flags = CLK_SET_RATE_PARENT,
1207 },
1208 },
1209 };
1210
1211 static struct clk_branch video_axi_clk = {
1212 .halt_reg = 0x1034,
1213 .clkr = {
1214 .enable_reg = 0x1034,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "video_axi_clk",
1218 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1219 .num_parents = 1,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223 };
1224
1225 static struct clk_branch video_maxi_clk = {
1226 .halt_reg = 0x1038,
1227 .clkr = {
1228 .enable_reg = 0x1038,
1229 .enable_mask = BIT(0),
1230 .hw.init = &(struct clk_init_data){
1231 .name = "video_maxi_clk",
1232 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1233 .num_parents = 1,
1234 .ops = &clk_branch2_ops,
1235 .flags = CLK_SET_RATE_PARENT,
1236 },
1237 },
1238 };
1239
1240 static struct clk_branch video_subcore0_clk = {
1241 .halt_reg = 0x1048,
1242 .clkr = {
1243 .enable_reg = 0x1048,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "video_subcore0_clk",
1247 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1248 .num_parents = 1,
1249 .ops = &clk_branch2_ops,
1250 .flags = CLK_SET_RATE_PARENT,
1251 },
1252 },
1253 };
1254
1255 static struct clk_branch video_subcore1_clk = {
1256 .halt_reg = 0x104c,
1257 .clkr = {
1258 .enable_reg = 0x104c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "video_subcore1_clk",
1262 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1263 .num_parents = 1,
1264 .ops = &clk_branch2_ops,
1265 .flags = CLK_SET_RATE_PARENT,
1266 },
1267 },
1268 };
1269
1270 static struct clk_branch mdss_ahb_clk = {
1271 .halt_reg = 0x2308,
1272 .hwcg_reg = 0x2308,
1273 .hwcg_bit = 1,
1274 .clkr = {
1275 .enable_reg = 0x2308,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "mdss_ahb_clk",
1279 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1280 .num_parents = 1,
1281 .ops = &clk_branch2_ops,
1282 .flags = CLK_SET_RATE_PARENT,
1283 },
1284 },
1285 };
1286
1287 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1288 .halt_reg = 0x230c,
1289 .clkr = {
1290 .enable_reg = 0x230c,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "mdss_hdmi_dp_ahb_clk",
1294 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1295 .num_parents = 1,
1296 .ops = &clk_branch2_ops,
1297 .flags = CLK_SET_RATE_PARENT,
1298 },
1299 },
1300 };
1301
1302 static struct clk_branch mdss_axi_clk = {
1303 .halt_reg = 0x2310,
1304 .clkr = {
1305 .enable_reg = 0x2310,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "mdss_axi_clk",
1309 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1310 .num_parents = 1,
1311 .ops = &clk_branch2_ops,
1312 },
1313 },
1314 };
1315
1316 static struct clk_branch mdss_pclk0_clk = {
1317 .halt_reg = 0x2314,
1318 .clkr = {
1319 .enable_reg = 0x2314,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "mdss_pclk0_clk",
1323 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1324 .num_parents = 1,
1325 .ops = &clk_branch2_ops,
1326 .flags = CLK_SET_RATE_PARENT,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch mdss_pclk1_clk = {
1332 .halt_reg = 0x2318,
1333 .clkr = {
1334 .enable_reg = 0x2318,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "mdss_pclk1_clk",
1338 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1339 .num_parents = 1,
1340 .ops = &clk_branch2_ops,
1341 .flags = CLK_SET_RATE_PARENT,
1342 },
1343 },
1344 };
1345
1346 static struct clk_branch mdss_mdp_clk = {
1347 .halt_reg = 0x231c,
1348 .clkr = {
1349 .enable_reg = 0x231c,
1350 .enable_mask = BIT(0),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "mdss_mdp_clk",
1353 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1354 .num_parents = 1,
1355 .ops = &clk_branch2_ops,
1356 .flags = CLK_SET_RATE_PARENT,
1357 },
1358 },
1359 };
1360
1361 static struct clk_branch mdss_mdp_lut_clk = {
1362 .halt_reg = 0x2320,
1363 .clkr = {
1364 .enable_reg = 0x2320,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "mdss_mdp_lut_clk",
1368 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1369 .num_parents = 1,
1370 .ops = &clk_branch2_ops,
1371 .flags = CLK_SET_RATE_PARENT,
1372 },
1373 },
1374 };
1375
1376 static struct clk_branch mdss_extpclk_clk = {
1377 .halt_reg = 0x2324,
1378 .clkr = {
1379 .enable_reg = 0x2324,
1380 .enable_mask = BIT(0),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "mdss_extpclk_clk",
1383 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1384 .num_parents = 1,
1385 .ops = &clk_branch2_ops,
1386 .flags = CLK_SET_RATE_PARENT,
1387 },
1388 },
1389 };
1390
1391 static struct clk_branch mdss_vsync_clk = {
1392 .halt_reg = 0x2328,
1393 .clkr = {
1394 .enable_reg = 0x2328,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "mdss_vsync_clk",
1398 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1399 .num_parents = 1,
1400 .ops = &clk_branch2_ops,
1401 .flags = CLK_SET_RATE_PARENT,
1402 },
1403 },
1404 };
1405
1406 static struct clk_branch mdss_hdmi_clk = {
1407 .halt_reg = 0x2338,
1408 .clkr = {
1409 .enable_reg = 0x2338,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "mdss_hdmi_clk",
1413 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1414 .num_parents = 1,
1415 .ops = &clk_branch2_ops,
1416 .flags = CLK_SET_RATE_PARENT,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch mdss_byte0_clk = {
1422 .halt_reg = 0x233c,
1423 .clkr = {
1424 .enable_reg = 0x233c,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "mdss_byte0_clk",
1428 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1429 .num_parents = 1,
1430 .ops = &clk_branch2_ops,
1431 .flags = CLK_SET_RATE_PARENT,
1432 },
1433 },
1434 };
1435
1436 static struct clk_branch mdss_byte1_clk = {
1437 .halt_reg = 0x2340,
1438 .clkr = {
1439 .enable_reg = 0x2340,
1440 .enable_mask = BIT(0),
1441 .hw.init = &(struct clk_init_data){
1442 .name = "mdss_byte1_clk",
1443 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1444 .num_parents = 1,
1445 .ops = &clk_branch2_ops,
1446 .flags = CLK_SET_RATE_PARENT,
1447 },
1448 },
1449 };
1450
1451 static struct clk_branch mdss_esc0_clk = {
1452 .halt_reg = 0x2344,
1453 .clkr = {
1454 .enable_reg = 0x2344,
1455 .enable_mask = BIT(0),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "mdss_esc0_clk",
1458 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1459 .num_parents = 1,
1460 .ops = &clk_branch2_ops,
1461 .flags = CLK_SET_RATE_PARENT,
1462 },
1463 },
1464 };
1465
1466 static struct clk_branch mdss_esc1_clk = {
1467 .halt_reg = 0x2348,
1468 .clkr = {
1469 .enable_reg = 0x2348,
1470 .enable_mask = BIT(0),
1471 .hw.init = &(struct clk_init_data){
1472 .name = "mdss_esc1_clk",
1473 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1474 .num_parents = 1,
1475 .ops = &clk_branch2_ops,
1476 .flags = CLK_SET_RATE_PARENT,
1477 },
1478 },
1479 };
1480
1481 static struct clk_branch mdss_rot_clk = {
1482 .halt_reg = 0x2350,
1483 .clkr = {
1484 .enable_reg = 0x2350,
1485 .enable_mask = BIT(0),
1486 .hw.init = &(struct clk_init_data){
1487 .name = "mdss_rot_clk",
1488 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1489 .num_parents = 1,
1490 .ops = &clk_branch2_ops,
1491 .flags = CLK_SET_RATE_PARENT,
1492 },
1493 },
1494 };
1495
1496 static struct clk_branch mdss_dp_link_clk = {
1497 .halt_reg = 0x2354,
1498 .clkr = {
1499 .enable_reg = 0x2354,
1500 .enable_mask = BIT(0),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "mdss_dp_link_clk",
1503 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1504 .num_parents = 1,
1505 .ops = &clk_branch2_ops,
1506 .flags = CLK_SET_RATE_PARENT,
1507 },
1508 },
1509 };
1510
1511 static struct clk_branch mdss_dp_link_intf_clk = {
1512 .halt_reg = 0x2358,
1513 .clkr = {
1514 .enable_reg = 0x2358,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "mdss_dp_link_intf_clk",
1518 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1519 .num_parents = 1,
1520 .ops = &clk_branch2_ops,
1521 .flags = CLK_SET_RATE_PARENT,
1522 },
1523 },
1524 };
1525
1526 static struct clk_branch mdss_dp_crypto_clk = {
1527 .halt_reg = 0x235c,
1528 .clkr = {
1529 .enable_reg = 0x235c,
1530 .enable_mask = BIT(0),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "mdss_dp_crypto_clk",
1533 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1534 .num_parents = 1,
1535 .ops = &clk_branch2_ops,
1536 .flags = CLK_SET_RATE_PARENT,
1537 },
1538 },
1539 };
1540
1541 static struct clk_branch mdss_dp_pixel_clk = {
1542 .halt_reg = 0x2360,
1543 .clkr = {
1544 .enable_reg = 0x2360,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "mdss_dp_pixel_clk",
1548 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1549 .num_parents = 1,
1550 .ops = &clk_branch2_ops,
1551 .flags = CLK_SET_RATE_PARENT,
1552 },
1553 },
1554 };
1555
1556 static struct clk_branch mdss_dp_aux_clk = {
1557 .halt_reg = 0x2364,
1558 .clkr = {
1559 .enable_reg = 0x2364,
1560 .enable_mask = BIT(0),
1561 .hw.init = &(struct clk_init_data){
1562 .name = "mdss_dp_aux_clk",
1563 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1564 .num_parents = 1,
1565 .ops = &clk_branch2_ops,
1566 .flags = CLK_SET_RATE_PARENT,
1567 },
1568 },
1569 };
1570
1571 static struct clk_branch mdss_byte0_intf_clk = {
1572 .halt_reg = 0x2374,
1573 .clkr = {
1574 .enable_reg = 0x2374,
1575 .enable_mask = BIT(0),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "mdss_byte0_intf_clk",
1578 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1579 .num_parents = 1,
1580 .ops = &clk_branch2_ops,
1581 .flags = CLK_SET_RATE_PARENT,
1582 },
1583 },
1584 };
1585
1586 static struct clk_branch mdss_byte1_intf_clk = {
1587 .halt_reg = 0x2378,
1588 .clkr = {
1589 .enable_reg = 0x2378,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "mdss_byte1_intf_clk",
1593 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1594 .num_parents = 1,
1595 .ops = &clk_branch2_ops,
1596 .flags = CLK_SET_RATE_PARENT,
1597 },
1598 },
1599 };
1600
1601 static struct clk_branch camss_csi0phytimer_clk = {
1602 .halt_reg = 0x3024,
1603 .clkr = {
1604 .enable_reg = 0x3024,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "camss_csi0phytimer_clk",
1608 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1609 .num_parents = 1,
1610 .ops = &clk_branch2_ops,
1611 .flags = CLK_SET_RATE_PARENT,
1612 },
1613 },
1614 };
1615
1616 static struct clk_branch camss_csi1phytimer_clk = {
1617 .halt_reg = 0x3054,
1618 .clkr = {
1619 .enable_reg = 0x3054,
1620 .enable_mask = BIT(0),
1621 .hw.init = &(struct clk_init_data){
1622 .name = "camss_csi1phytimer_clk",
1623 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1624 .num_parents = 1,
1625 .ops = &clk_branch2_ops,
1626 .flags = CLK_SET_RATE_PARENT,
1627 },
1628 },
1629 };
1630
1631 static struct clk_branch camss_csi2phytimer_clk = {
1632 .halt_reg = 0x3084,
1633 .clkr = {
1634 .enable_reg = 0x3084,
1635 .enable_mask = BIT(0),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "camss_csi2phytimer_clk",
1638 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1639 .num_parents = 1,
1640 .ops = &clk_branch2_ops,
1641 .flags = CLK_SET_RATE_PARENT,
1642 },
1643 },
1644 };
1645
1646 static struct clk_branch camss_csi0_clk = {
1647 .halt_reg = 0x30b4,
1648 .clkr = {
1649 .enable_reg = 0x30b4,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "camss_csi0_clk",
1653 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1654 .num_parents = 1,
1655 .ops = &clk_branch2_ops,
1656 .flags = CLK_SET_RATE_PARENT,
1657 },
1658 },
1659 };
1660
1661 static struct clk_branch camss_csi0_ahb_clk = {
1662 .halt_reg = 0x30bc,
1663 .clkr = {
1664 .enable_reg = 0x30bc,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_csi0_ahb_clk",
1668 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1669 .num_parents = 1,
1670 .ops = &clk_branch2_ops,
1671 .flags = CLK_SET_RATE_PARENT,
1672 },
1673 },
1674 };
1675
1676 static struct clk_branch camss_csi0rdi_clk = {
1677 .halt_reg = 0x30d4,
1678 .clkr = {
1679 .enable_reg = 0x30d4,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "camss_csi0rdi_clk",
1683 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1684 .num_parents = 1,
1685 .ops = &clk_branch2_ops,
1686 .flags = CLK_SET_RATE_PARENT,
1687 },
1688 },
1689 };
1690
1691 static struct clk_branch camss_csi0pix_clk = {
1692 .halt_reg = 0x30e4,
1693 .clkr = {
1694 .enable_reg = 0x30e4,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "camss_csi0pix_clk",
1698 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1699 .num_parents = 1,
1700 .ops = &clk_branch2_ops,
1701 .flags = CLK_SET_RATE_PARENT,
1702 },
1703 },
1704 };
1705
1706 static struct clk_branch camss_csi1_clk = {
1707 .halt_reg = 0x3124,
1708 .clkr = {
1709 .enable_reg = 0x3124,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "camss_csi1_clk",
1713 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1714 .num_parents = 1,
1715 .ops = &clk_branch2_ops,
1716 .flags = CLK_SET_RATE_PARENT,
1717 },
1718 },
1719 };
1720
1721 static struct clk_branch camss_csi1_ahb_clk = {
1722 .halt_reg = 0x3128,
1723 .clkr = {
1724 .enable_reg = 0x3128,
1725 .enable_mask = BIT(0),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "camss_csi1_ahb_clk",
1728 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1729 .num_parents = 1,
1730 .ops = &clk_branch2_ops,
1731 .flags = CLK_SET_RATE_PARENT,
1732 },
1733 },
1734 };
1735
1736 static struct clk_branch camss_csi1rdi_clk = {
1737 .halt_reg = 0x3144,
1738 .clkr = {
1739 .enable_reg = 0x3144,
1740 .enable_mask = BIT(0),
1741 .hw.init = &(struct clk_init_data){
1742 .name = "camss_csi1rdi_clk",
1743 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1744 .num_parents = 1,
1745 .ops = &clk_branch2_ops,
1746 .flags = CLK_SET_RATE_PARENT,
1747 },
1748 },
1749 };
1750
1751 static struct clk_branch camss_csi1pix_clk = {
1752 .halt_reg = 0x3154,
1753 .clkr = {
1754 .enable_reg = 0x3154,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "camss_csi1pix_clk",
1758 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1759 .num_parents = 1,
1760 .ops = &clk_branch2_ops,
1761 .flags = CLK_SET_RATE_PARENT,
1762 },
1763 },
1764 };
1765
1766 static struct clk_branch camss_csi2_clk = {
1767 .halt_reg = 0x3184,
1768 .clkr = {
1769 .enable_reg = 0x3184,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "camss_csi2_clk",
1773 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1774 .num_parents = 1,
1775 .ops = &clk_branch2_ops,
1776 .flags = CLK_SET_RATE_PARENT,
1777 },
1778 },
1779 };
1780
1781 static struct clk_branch camss_csi2_ahb_clk = {
1782 .halt_reg = 0x3188,
1783 .clkr = {
1784 .enable_reg = 0x3188,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "camss_csi2_ahb_clk",
1788 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1789 .num_parents = 1,
1790 .ops = &clk_branch2_ops,
1791 .flags = CLK_SET_RATE_PARENT,
1792 },
1793 },
1794 };
1795
1796 static struct clk_branch camss_csi2rdi_clk = {
1797 .halt_reg = 0x31a4,
1798 .clkr = {
1799 .enable_reg = 0x31a4,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "camss_csi2rdi_clk",
1803 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1804 .num_parents = 1,
1805 .ops = &clk_branch2_ops,
1806 .flags = CLK_SET_RATE_PARENT,
1807 },
1808 },
1809 };
1810
1811 static struct clk_branch camss_csi2pix_clk = {
1812 .halt_reg = 0x31b4,
1813 .clkr = {
1814 .enable_reg = 0x31b4,
1815 .enable_mask = BIT(0),
1816 .hw.init = &(struct clk_init_data){
1817 .name = "camss_csi2pix_clk",
1818 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1819 .num_parents = 1,
1820 .ops = &clk_branch2_ops,
1821 .flags = CLK_SET_RATE_PARENT,
1822 },
1823 },
1824 };
1825
1826 static struct clk_branch camss_csi3_clk = {
1827 .halt_reg = 0x31e4,
1828 .clkr = {
1829 .enable_reg = 0x31e4,
1830 .enable_mask = BIT(0),
1831 .hw.init = &(struct clk_init_data){
1832 .name = "camss_csi3_clk",
1833 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1834 .num_parents = 1,
1835 .ops = &clk_branch2_ops,
1836 .flags = CLK_SET_RATE_PARENT,
1837 },
1838 },
1839 };
1840
1841 static struct clk_branch camss_csi3_ahb_clk = {
1842 .halt_reg = 0x31e8,
1843 .clkr = {
1844 .enable_reg = 0x31e8,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "camss_csi3_ahb_clk",
1848 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1849 .num_parents = 1,
1850 .ops = &clk_branch2_ops,
1851 .flags = CLK_SET_RATE_PARENT,
1852 },
1853 },
1854 };
1855
1856 static struct clk_branch camss_csi3rdi_clk = {
1857 .halt_reg = 0x3204,
1858 .clkr = {
1859 .enable_reg = 0x3204,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "camss_csi3rdi_clk",
1863 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1864 .num_parents = 1,
1865 .ops = &clk_branch2_ops,
1866 .flags = CLK_SET_RATE_PARENT,
1867 },
1868 },
1869 };
1870
1871 static struct clk_branch camss_csi3pix_clk = {
1872 .halt_reg = 0x3214,
1873 .clkr = {
1874 .enable_reg = 0x3214,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "camss_csi3pix_clk",
1878 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1879 .num_parents = 1,
1880 .ops = &clk_branch2_ops,
1881 .flags = CLK_SET_RATE_PARENT,
1882 },
1883 },
1884 };
1885
1886 static struct clk_branch camss_ispif_ahb_clk = {
1887 .halt_reg = 0x3224,
1888 .clkr = {
1889 .enable_reg = 0x3224,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "camss_ispif_ahb_clk",
1893 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1894 .num_parents = 1,
1895 .ops = &clk_branch2_ops,
1896 .flags = CLK_SET_RATE_PARENT,
1897 },
1898 },
1899 };
1900
1901 static struct clk_branch camss_cci_clk = {
1902 .halt_reg = 0x3344,
1903 .clkr = {
1904 .enable_reg = 0x3344,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "camss_cci_clk",
1908 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1909 .num_parents = 1,
1910 .ops = &clk_branch2_ops,
1911 .flags = CLK_SET_RATE_PARENT,
1912 },
1913 },
1914 };
1915
1916 static struct clk_branch camss_cci_ahb_clk = {
1917 .halt_reg = 0x3348,
1918 .clkr = {
1919 .enable_reg = 0x3348,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "camss_cci_ahb_clk",
1923 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1924 .num_parents = 1,
1925 .ops = &clk_branch2_ops,
1926 .flags = CLK_SET_RATE_PARENT,
1927 },
1928 },
1929 };
1930
1931 static struct clk_branch camss_mclk0_clk = {
1932 .halt_reg = 0x3384,
1933 .clkr = {
1934 .enable_reg = 0x3384,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "camss_mclk0_clk",
1938 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1939 .num_parents = 1,
1940 .ops = &clk_branch2_ops,
1941 .flags = CLK_SET_RATE_PARENT,
1942 },
1943 },
1944 };
1945
1946 static struct clk_branch camss_mclk1_clk = {
1947 .halt_reg = 0x33b4,
1948 .clkr = {
1949 .enable_reg = 0x33b4,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(struct clk_init_data){
1952 .name = "camss_mclk1_clk",
1953 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1954 .num_parents = 1,
1955 .ops = &clk_branch2_ops,
1956 .flags = CLK_SET_RATE_PARENT,
1957 },
1958 },
1959 };
1960
1961 static struct clk_branch camss_mclk2_clk = {
1962 .halt_reg = 0x33e4,
1963 .clkr = {
1964 .enable_reg = 0x33e4,
1965 .enable_mask = BIT(0),
1966 .hw.init = &(struct clk_init_data){
1967 .name = "camss_mclk2_clk",
1968 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1969 .num_parents = 1,
1970 .ops = &clk_branch2_ops,
1971 .flags = CLK_SET_RATE_PARENT,
1972 },
1973 },
1974 };
1975
1976 static struct clk_branch camss_mclk3_clk = {
1977 .halt_reg = 0x3414,
1978 .clkr = {
1979 .enable_reg = 0x3414,
1980 .enable_mask = BIT(0),
1981 .hw.init = &(struct clk_init_data){
1982 .name = "camss_mclk3_clk",
1983 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1984 .num_parents = 1,
1985 .ops = &clk_branch2_ops,
1986 .flags = CLK_SET_RATE_PARENT,
1987 },
1988 },
1989 };
1990
1991 static struct clk_branch camss_top_ahb_clk = {
1992 .halt_reg = 0x3484,
1993 .clkr = {
1994 .enable_reg = 0x3484,
1995 .enable_mask = BIT(0),
1996 .hw.init = &(struct clk_init_data){
1997 .name = "camss_top_ahb_clk",
1998 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1999 .num_parents = 1,
2000 .ops = &clk_branch2_ops,
2001 .flags = CLK_SET_RATE_PARENT,
2002 },
2003 },
2004 };
2005
2006 static struct clk_branch camss_ahb_clk = {
2007 .halt_reg = 0x348c,
2008 .clkr = {
2009 .enable_reg = 0x348c,
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "camss_ahb_clk",
2013 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2014 .num_parents = 1,
2015 .ops = &clk_branch2_ops,
2016 .flags = CLK_SET_RATE_PARENT,
2017 },
2018 },
2019 };
2020
2021 static struct clk_branch camss_micro_ahb_clk = {
2022 .halt_reg = 0x3494,
2023 .clkr = {
2024 .enable_reg = 0x3494,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "camss_micro_ahb_clk",
2028 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2029 .num_parents = 1,
2030 .ops = &clk_branch2_ops,
2031 .flags = CLK_SET_RATE_PARENT,
2032 },
2033 },
2034 };
2035
2036 static struct clk_branch camss_jpeg0_clk = {
2037 .halt_reg = 0x35a8,
2038 .clkr = {
2039 .enable_reg = 0x35a8,
2040 .enable_mask = BIT(0),
2041 .hw.init = &(struct clk_init_data){
2042 .name = "camss_jpeg0_clk",
2043 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2044 .num_parents = 1,
2045 .ops = &clk_branch2_ops,
2046 .flags = CLK_SET_RATE_PARENT,
2047 },
2048 },
2049 };
2050
2051 static struct clk_branch camss_jpeg_ahb_clk = {
2052 .halt_reg = 0x35b4,
2053 .clkr = {
2054 .enable_reg = 0x35b4,
2055 .enable_mask = BIT(0),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "camss_jpeg_ahb_clk",
2058 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2059 .num_parents = 1,
2060 .ops = &clk_branch2_ops,
2061 .flags = CLK_SET_RATE_PARENT,
2062 },
2063 },
2064 };
2065
2066 static struct clk_branch camss_jpeg_axi_clk = {
2067 .halt_reg = 0x35b8,
2068 .clkr = {
2069 .enable_reg = 0x35b8,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "camss_jpeg_axi_clk",
2073 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2074 .num_parents = 1,
2075 .ops = &clk_branch2_ops,
2076 },
2077 },
2078 };
2079
2080 static struct clk_branch camss_vfe0_ahb_clk = {
2081 .halt_reg = 0x3668,
2082 .clkr = {
2083 .enable_reg = 0x3668,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "camss_vfe0_ahb_clk",
2087 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2088 .num_parents = 1,
2089 .ops = &clk_branch2_ops,
2090 .flags = CLK_SET_RATE_PARENT,
2091 },
2092 },
2093 };
2094
2095 static struct clk_branch camss_vfe1_ahb_clk = {
2096 .halt_reg = 0x3678,
2097 .clkr = {
2098 .enable_reg = 0x3678,
2099 .enable_mask = BIT(0),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "camss_vfe1_ahb_clk",
2102 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2103 .num_parents = 1,
2104 .ops = &clk_branch2_ops,
2105 .flags = CLK_SET_RATE_PARENT,
2106 },
2107 },
2108 };
2109
2110 static struct clk_branch camss_vfe0_clk = {
2111 .halt_reg = 0x36a8,
2112 .clkr = {
2113 .enable_reg = 0x36a8,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(struct clk_init_data){
2116 .name = "camss_vfe0_clk",
2117 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2118 .num_parents = 1,
2119 .ops = &clk_branch2_ops,
2120 .flags = CLK_SET_RATE_PARENT,
2121 },
2122 },
2123 };
2124
2125 static struct clk_branch camss_vfe1_clk = {
2126 .halt_reg = 0x36ac,
2127 .clkr = {
2128 .enable_reg = 0x36ac,
2129 .enable_mask = BIT(0),
2130 .hw.init = &(struct clk_init_data){
2131 .name = "camss_vfe1_clk",
2132 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2133 .num_parents = 1,
2134 .ops = &clk_branch2_ops,
2135 .flags = CLK_SET_RATE_PARENT,
2136 },
2137 },
2138 };
2139
2140 static struct clk_branch camss_cpp_clk = {
2141 .halt_reg = 0x36b0,
2142 .clkr = {
2143 .enable_reg = 0x36b0,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "camss_cpp_clk",
2147 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2148 .num_parents = 1,
2149 .ops = &clk_branch2_ops,
2150 .flags = CLK_SET_RATE_PARENT,
2151 },
2152 },
2153 };
2154
2155 static struct clk_branch camss_cpp_ahb_clk = {
2156 .halt_reg = 0x36b4,
2157 .clkr = {
2158 .enable_reg = 0x36b4,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "camss_cpp_ahb_clk",
2162 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2163 .num_parents = 1,
2164 .ops = &clk_branch2_ops,
2165 .flags = CLK_SET_RATE_PARENT,
2166 },
2167 },
2168 };
2169
2170 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2171 .halt_reg = 0x36b8,
2172 .clkr = {
2173 .enable_reg = 0x36b8,
2174 .enable_mask = BIT(0),
2175 .hw.init = &(struct clk_init_data){
2176 .name = "camss_vfe_vbif_ahb_clk",
2177 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2178 .num_parents = 1,
2179 .ops = &clk_branch2_ops,
2180 .flags = CLK_SET_RATE_PARENT,
2181 },
2182 },
2183 };
2184
2185 static struct clk_branch camss_vfe_vbif_axi_clk = {
2186 .halt_reg = 0x36bc,
2187 .clkr = {
2188 .enable_reg = 0x36bc,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "camss_vfe_vbif_axi_clk",
2192 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2193 .num_parents = 1,
2194 .ops = &clk_branch2_ops,
2195 },
2196 },
2197 };
2198
2199 static struct clk_branch camss_cpp_axi_clk = {
2200 .halt_reg = 0x36c4,
2201 .clkr = {
2202 .enable_reg = 0x36c4,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "camss_cpp_axi_clk",
2206 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2207 .num_parents = 1,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211 };
2212
2213 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2214 .halt_reg = 0x36c8,
2215 .clkr = {
2216 .enable_reg = 0x36c8,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "camss_cpp_vbif_ahb_clk",
2220 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2221 .num_parents = 1,
2222 .ops = &clk_branch2_ops,
2223 .flags = CLK_SET_RATE_PARENT,
2224 },
2225 },
2226 };
2227
2228 static struct clk_branch camss_csi_vfe0_clk = {
2229 .halt_reg = 0x3704,
2230 .clkr = {
2231 .enable_reg = 0x3704,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "camss_csi_vfe0_clk",
2235 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2236 .num_parents = 1,
2237 .ops = &clk_branch2_ops,
2238 .flags = CLK_SET_RATE_PARENT,
2239 },
2240 },
2241 };
2242
2243 static struct clk_branch camss_csi_vfe1_clk = {
2244 .halt_reg = 0x3714,
2245 .clkr = {
2246 .enable_reg = 0x3714,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "camss_csi_vfe1_clk",
2250 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2251 .num_parents = 1,
2252 .ops = &clk_branch2_ops,
2253 .flags = CLK_SET_RATE_PARENT,
2254 },
2255 },
2256 };
2257
2258 static struct clk_branch camss_vfe0_stream_clk = {
2259 .halt_reg = 0x3720,
2260 .clkr = {
2261 .enable_reg = 0x3720,
2262 .enable_mask = BIT(0),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "camss_vfe0_stream_clk",
2265 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2266 .num_parents = 1,
2267 .ops = &clk_branch2_ops,
2268 .flags = CLK_SET_RATE_PARENT,
2269 },
2270 },
2271 };
2272
2273 static struct clk_branch camss_vfe1_stream_clk = {
2274 .halt_reg = 0x3724,
2275 .clkr = {
2276 .enable_reg = 0x3724,
2277 .enable_mask = BIT(0),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "camss_vfe1_stream_clk",
2280 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2281 .num_parents = 1,
2282 .ops = &clk_branch2_ops,
2283 .flags = CLK_SET_RATE_PARENT,
2284 },
2285 },
2286 };
2287
2288 static struct clk_branch camss_cphy_csid0_clk = {
2289 .halt_reg = 0x3730,
2290 .clkr = {
2291 .enable_reg = 0x3730,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "camss_cphy_csid0_clk",
2295 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2296 .num_parents = 1,
2297 .ops = &clk_branch2_ops,
2298 .flags = CLK_SET_RATE_PARENT,
2299 },
2300 },
2301 };
2302
2303 static struct clk_branch camss_cphy_csid1_clk = {
2304 .halt_reg = 0x3734,
2305 .clkr = {
2306 .enable_reg = 0x3734,
2307 .enable_mask = BIT(0),
2308 .hw.init = &(struct clk_init_data){
2309 .name = "camss_cphy_csid1_clk",
2310 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2311 .num_parents = 1,
2312 .ops = &clk_branch2_ops,
2313 .flags = CLK_SET_RATE_PARENT,
2314 },
2315 },
2316 };
2317
2318 static struct clk_branch camss_cphy_csid2_clk = {
2319 .halt_reg = 0x3738,
2320 .clkr = {
2321 .enable_reg = 0x3738,
2322 .enable_mask = BIT(0),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "camss_cphy_csid2_clk",
2325 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2326 .num_parents = 1,
2327 .ops = &clk_branch2_ops,
2328 .flags = CLK_SET_RATE_PARENT,
2329 },
2330 },
2331 };
2332
2333 static struct clk_branch camss_cphy_csid3_clk = {
2334 .halt_reg = 0x373c,
2335 .clkr = {
2336 .enable_reg = 0x373c,
2337 .enable_mask = BIT(0),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "camss_cphy_csid3_clk",
2340 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2341 .num_parents = 1,
2342 .ops = &clk_branch2_ops,
2343 .flags = CLK_SET_RATE_PARENT,
2344 },
2345 },
2346 };
2347
2348 static struct clk_branch camss_csiphy0_clk = {
2349 .halt_reg = 0x3740,
2350 .clkr = {
2351 .enable_reg = 0x3740,
2352 .enable_mask = BIT(0),
2353 .hw.init = &(struct clk_init_data){
2354 .name = "camss_csiphy0_clk",
2355 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2356 .num_parents = 1,
2357 .ops = &clk_branch2_ops,
2358 .flags = CLK_SET_RATE_PARENT,
2359 },
2360 },
2361 };
2362
2363 static struct clk_branch camss_csiphy1_clk = {
2364 .halt_reg = 0x3744,
2365 .clkr = {
2366 .enable_reg = 0x3744,
2367 .enable_mask = BIT(0),
2368 .hw.init = &(struct clk_init_data){
2369 .name = "camss_csiphy1_clk",
2370 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2371 .num_parents = 1,
2372 .ops = &clk_branch2_ops,
2373 .flags = CLK_SET_RATE_PARENT,
2374 },
2375 },
2376 };
2377
2378 static struct clk_branch camss_csiphy2_clk = {
2379 .halt_reg = 0x3748,
2380 .clkr = {
2381 .enable_reg = 0x3748,
2382 .enable_mask = BIT(0),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "camss_csiphy2_clk",
2385 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2386 .num_parents = 1,
2387 .ops = &clk_branch2_ops,
2388 .flags = CLK_SET_RATE_PARENT,
2389 },
2390 },
2391 };
2392
2393 static struct clk_branch fd_core_clk = {
2394 .halt_reg = 0x3b68,
2395 .clkr = {
2396 .enable_reg = 0x3b68,
2397 .enable_mask = BIT(0),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "fd_core_clk",
2400 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2401 .num_parents = 1,
2402 .ops = &clk_branch2_ops,
2403 .flags = CLK_SET_RATE_PARENT,
2404 },
2405 },
2406 };
2407
2408 static struct clk_branch fd_core_uar_clk = {
2409 .halt_reg = 0x3b6c,
2410 .clkr = {
2411 .enable_reg = 0x3b6c,
2412 .enable_mask = BIT(0),
2413 .hw.init = &(struct clk_init_data){
2414 .name = "fd_core_uar_clk",
2415 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2416 .num_parents = 1,
2417 .ops = &clk_branch2_ops,
2418 .flags = CLK_SET_RATE_PARENT,
2419 },
2420 },
2421 };
2422
2423 static struct clk_branch fd_ahb_clk = {
2424 .halt_reg = 0x3b74,
2425 .clkr = {
2426 .enable_reg = 0x3b74,
2427 .enable_mask = BIT(0),
2428 .hw.init = &(struct clk_init_data){
2429 .name = "fd_ahb_clk",
2430 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2431 .num_parents = 1,
2432 .ops = &clk_branch2_ops,
2433 .flags = CLK_SET_RATE_PARENT,
2434 },
2435 },
2436 };
2437
2438 static struct clk_branch mnoc_ahb_clk = {
2439 .halt_reg = 0x5024,
2440 .halt_check = BRANCH_HALT_SKIP,
2441 .clkr = {
2442 .enable_reg = 0x5024,
2443 .enable_mask = BIT(0),
2444 .hw.init = &(struct clk_init_data){
2445 .name = "mnoc_ahb_clk",
2446 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2447 .num_parents = 1,
2448 .ops = &clk_branch2_ops,
2449 .flags = CLK_SET_RATE_PARENT,
2450 },
2451 },
2452 };
2453
2454 static struct clk_branch bimc_smmu_ahb_clk = {
2455 .halt_reg = 0xe004,
2456 .halt_check = BRANCH_HALT_SKIP,
2457 .hwcg_reg = 0xe004,
2458 .hwcg_bit = 1,
2459 .clkr = {
2460 .enable_reg = 0xe004,
2461 .enable_mask = BIT(0),
2462 .hw.init = &(struct clk_init_data){
2463 .name = "bimc_smmu_ahb_clk",
2464 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2465 .num_parents = 1,
2466 .ops = &clk_branch2_ops,
2467 .flags = CLK_SET_RATE_PARENT,
2468 },
2469 },
2470 };
2471
2472 static struct clk_branch bimc_smmu_axi_clk = {
2473 .halt_reg = 0xe008,
2474 .halt_check = BRANCH_HALT_SKIP,
2475 .hwcg_reg = 0xe008,
2476 .hwcg_bit = 1,
2477 .clkr = {
2478 .enable_reg = 0xe008,
2479 .enable_mask = BIT(0),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "bimc_smmu_axi_clk",
2482 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2483 .num_parents = 1,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487 };
2488
2489 static struct clk_branch mnoc_maxi_clk = {
2490 .halt_reg = 0xf004,
2491 .clkr = {
2492 .enable_reg = 0xf004,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mnoc_maxi_clk",
2496 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2497 .num_parents = 1,
2498 .ops = &clk_branch2_ops,
2499 .flags = CLK_SET_RATE_PARENT,
2500 },
2501 },
2502 };
2503
2504 static struct clk_branch vmem_maxi_clk = {
2505 .halt_reg = 0xf064,
2506 .clkr = {
2507 .enable_reg = 0xf064,
2508 .enable_mask = BIT(0),
2509 .hw.init = &(struct clk_init_data){
2510 .name = "vmem_maxi_clk",
2511 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2512 .num_parents = 1,
2513 .ops = &clk_branch2_ops,
2514 .flags = CLK_SET_RATE_PARENT,
2515 },
2516 },
2517 };
2518
2519 static struct clk_branch vmem_ahb_clk = {
2520 .halt_reg = 0xf068,
2521 .clkr = {
2522 .enable_reg = 0xf068,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "vmem_ahb_clk",
2526 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2527 .num_parents = 1,
2528 .ops = &clk_branch2_ops,
2529 .flags = CLK_SET_RATE_PARENT,
2530 },
2531 },
2532 };
2533
2534 static struct gdsc video_top_gdsc = {
2535 .gdscr = 0x1024,
2536 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2537 .cxc_count = 3,
2538 .pd = {
2539 .name = "video_top",
2540 },
2541 .pwrsts = PWRSTS_OFF_ON,
2542 };
2543
2544 static struct gdsc video_subcore0_gdsc = {
2545 .gdscr = 0x1040,
2546 .cxcs = (unsigned int []){ 0x1048 },
2547 .cxc_count = 1,
2548 .pd = {
2549 .name = "video_subcore0",
2550 },
2551 .parent = &video_top_gdsc.pd,
2552 .pwrsts = PWRSTS_OFF_ON,
2553 .flags = HW_CTRL,
2554 };
2555
2556 static struct gdsc video_subcore1_gdsc = {
2557 .gdscr = 0x1044,
2558 .cxcs = (unsigned int []){ 0x104c },
2559 .cxc_count = 1,
2560 .pd = {
2561 .name = "video_subcore1",
2562 },
2563 .parent = &video_top_gdsc.pd,
2564 .pwrsts = PWRSTS_OFF_ON,
2565 .flags = HW_CTRL,
2566 };
2567
2568 static struct gdsc mdss_gdsc = {
2569 .gdscr = 0x2304,
2570 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2571 .cxc_count = 4,
2572 .pd = {
2573 .name = "mdss",
2574 },
2575 .pwrsts = PWRSTS_OFF_ON,
2576 };
2577
2578 static struct gdsc camss_top_gdsc = {
2579 .gdscr = 0x34a0,
2580 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2581 0x35a8, 0x3868 },
2582 .cxc_count = 7,
2583 .pd = {
2584 .name = "camss_top",
2585 },
2586 .pwrsts = PWRSTS_OFF_ON,
2587 };
2588
2589 static struct gdsc camss_vfe0_gdsc = {
2590 .gdscr = 0x3664,
2591 .pd = {
2592 .name = "camss_vfe0",
2593 },
2594 .parent = &camss_top_gdsc.pd,
2595 .pwrsts = PWRSTS_OFF_ON,
2596 };
2597
2598 static struct gdsc camss_vfe1_gdsc = {
2599 .gdscr = 0x3674,
2600 .pd = {
2601 .name = "camss_vfe1_gdsc",
2602 },
2603 .parent = &camss_top_gdsc.pd,
2604 .pwrsts = PWRSTS_OFF_ON,
2605 };
2606
2607 static struct gdsc camss_cpp_gdsc = {
2608 .gdscr = 0x36d4,
2609 .pd = {
2610 .name = "camss_cpp",
2611 },
2612 .parent = &camss_top_gdsc.pd,
2613 .pwrsts = PWRSTS_OFF_ON,
2614 };
2615
2616 static struct gdsc bimc_smmu_gdsc = {
2617 .gdscr = 0xe020,
2618 .gds_hw_ctrl = 0xe024,
2619 .cxcs = (unsigned int []){ 0xe008 },
2620 .cxc_count = 1,
2621 .pd = {
2622 .name = "bimc_smmu",
2623 },
2624 .pwrsts = PWRSTS_OFF_ON,
2625 .flags = VOTABLE,
2626 };
2627
2628 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2629 [MMPLL0] = &mmpll0.clkr,
2630 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2631 [MMPLL1] = &mmpll1.clkr,
2632 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2633 [MMPLL3] = &mmpll3.clkr,
2634 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2635 [MMPLL4] = &mmpll4.clkr,
2636 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2637 [MMPLL5] = &mmpll5.clkr,
2638 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2639 [MMPLL6] = &mmpll6.clkr,
2640 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2641 [MMPLL7] = &mmpll7.clkr,
2642 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2643 [MMPLL10] = &mmpll10.clkr,
2644 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2645 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2646 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2647 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2648 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2649 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2650 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2651 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2652 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2653 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2654 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2655 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2656 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2657 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2658 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2659 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2660 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2661 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2662 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2663 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2664 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2665 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2666 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2667 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2668 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2669 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2670 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2671 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2672 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2673 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2674 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2675 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2676 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2677 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2678 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2679 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2680 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2681 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2682 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2683 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2684 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2685 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2686 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2687 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2688 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2689 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2690 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2691 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2692 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2693 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2694 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2695 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2696 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2697 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2698 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2699 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2700 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2701 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2702 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2703 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2704 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2705 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2706 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2707 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2708 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2709 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2710 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2711 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2712 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2713 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2714 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2715 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2716 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2717 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2718 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2719 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2720 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2721 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2722 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2723 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2724 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2725 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2726 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2727 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2728 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2729 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2730 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2731 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2732 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2733 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2734 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2735 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2736 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2737 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2738 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2739 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2740 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2741 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2742 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2743 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2744 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2745 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2746 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2747 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2748 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2749 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2750 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2751 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2752 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2753 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2754 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2755 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2756 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2757 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2758 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2759 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2760 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2761 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2762 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2763 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2764 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2765 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2766 [FD_CORE_CLK] = &fd_core_clk.clkr,
2767 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2768 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2769 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2770 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2771 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2772 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2773 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2774 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2775 };
2776
2777 static struct gdsc *mmcc_msm8998_gdscs[] = {
2778 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2779 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2780 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2781 [MDSS_GDSC] = &mdss_gdsc,
2782 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2783 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2784 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2785 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2786 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2787 };
2788
2789 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2790 [SPDM_BCR] = { 0x200 },
2791 [SPDM_RM_BCR] = { 0x300 },
2792 [MISC_BCR] = { 0x320 },
2793 [VIDEO_TOP_BCR] = { 0x1020 },
2794 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2795 [MDSS_BCR] = { 0x2300 },
2796 [THROTTLE_MDSS_BCR] = { 0x2460 },
2797 [CAMSS_PHY0_BCR] = { 0x3020 },
2798 [CAMSS_PHY1_BCR] = { 0x3050 },
2799 [CAMSS_PHY2_BCR] = { 0x3080 },
2800 [CAMSS_CSI0_BCR] = { 0x30b0 },
2801 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2802 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2803 [CAMSS_CSI1_BCR] = { 0x3120 },
2804 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2805 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2806 [CAMSS_CSI2_BCR] = { 0x3180 },
2807 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2808 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2809 [CAMSS_CSI3_BCR] = { 0x31e0 },
2810 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2811 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2812 [CAMSS_ISPIF_BCR] = { 0x3220 },
2813 [CAMSS_CCI_BCR] = { 0x3340 },
2814 [CAMSS_TOP_BCR] = { 0x3480 },
2815 [CAMSS_AHB_BCR] = { 0x3488 },
2816 [CAMSS_MICRO_BCR] = { 0x3490 },
2817 [CAMSS_JPEG_BCR] = { 0x35a0 },
2818 [CAMSS_VFE0_BCR] = { 0x3660 },
2819 [CAMSS_VFE1_BCR] = { 0x3670 },
2820 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2821 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2822 [CAMSS_CPP_BCR] = { 0x36d0 },
2823 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2824 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2825 [CAMSS_FD_BCR] = { 0x3b60 },
2826 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2827 [MNOCAHB_BCR] = { 0x5020 },
2828 [MNOCAXI_BCR] = { 0xd020 },
2829 [BMIC_SMMU_BCR] = { 0xe000 },
2830 [MNOC_MAXI_BCR] = { 0xf000 },
2831 [VMEM_BCR] = { 0xf060 },
2832 [BTO_BCR] = { 0x10004 },
2833 };
2834
2835 static const struct regmap_config mmcc_msm8998_regmap_config = {
2836 .reg_bits = 32,
2837 .reg_stride = 4,
2838 .val_bits = 32,
2839 .max_register = 0x10004,
2840 .fast_io = true,
2841 };
2842
2843 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2844 .config = &mmcc_msm8998_regmap_config,
2845 .clks = mmcc_msm8998_clocks,
2846 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2847 .resets = mmcc_msm8998_resets,
2848 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2849 .gdscs = mmcc_msm8998_gdscs,
2850 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2851 };
2852
2853 static const struct of_device_id mmcc_msm8998_match_table[] = {
2854 { .compatible = "qcom,mmcc-msm8998" },
2855 { }
2856 };
2857 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2858
mmcc_msm8998_probe(struct platform_device * pdev)2859 static int mmcc_msm8998_probe(struct platform_device *pdev)
2860 {
2861 struct regmap *regmap;
2862
2863 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2864 if (IS_ERR(regmap))
2865 return PTR_ERR(regmap);
2866
2867 return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8998_desc, regmap);
2868 }
2869
2870 static struct platform_driver mmcc_msm8998_driver = {
2871 .probe = mmcc_msm8998_probe,
2872 .driver = {
2873 .name = "mmcc-msm8998",
2874 .of_match_table = mmcc_msm8998_match_table,
2875 },
2876 };
2877 module_platform_driver(mmcc_msm8998_driver);
2878
2879 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2880 MODULE_LICENSE("GPL v2");
2881