1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2025 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/irqdomain.h> 12 #include <linux/kernel.h> 13 #include <linux/mutex.h> 14 #include <linux/pcs/pcs-xpcs.h> 15 #include <linux/phy.h> 16 #include <linux/regmap.h> 17 #include <net/dsa.h> 18 #include <net/pkt_cls.h> 19 #include <linux/irq.h> 20 #include <linux/platform_data/microchip-ksz.h> 21 22 #include "ksz_ptp.h" 23 24 #define KSZ_MAX_NUM_PORTS 8 25 /* all KSZ switches count ports from 1 */ 26 #define KSZ_PORT_1 0 27 #define KSZ_PORT_2 1 28 #define KSZ_PORT_4 3 29 30 struct ksz_device; 31 struct ksz_port; 32 struct phylink_mac_ops; 33 34 enum ksz_regmap_width { 35 KSZ_REGMAP_8, 36 KSZ_REGMAP_16, 37 KSZ_REGMAP_32, 38 __KSZ_NUM_REGMAPS, 39 }; 40 41 struct vlan_table { 42 u32 table[3]; 43 }; 44 45 struct ksz_stats_raw { 46 u64 rx_hi; 47 u64 rx_undersize; 48 u64 rx_fragments; 49 u64 rx_oversize; 50 u64 rx_jabbers; 51 u64 rx_symbol_err; 52 u64 rx_crc_err; 53 u64 rx_align_err; 54 u64 rx_mac_ctrl; 55 u64 rx_pause; 56 u64 rx_bcast; 57 u64 rx_mcast; 58 u64 rx_ucast; 59 u64 rx_64_or_less; 60 u64 rx_65_127; 61 u64 rx_128_255; 62 u64 rx_256_511; 63 u64 rx_512_1023; 64 u64 rx_1024_1522; 65 u64 rx_1523_2000; 66 u64 rx_2001; 67 u64 tx_hi; 68 u64 tx_late_col; 69 u64 tx_pause; 70 u64 tx_bcast; 71 u64 tx_mcast; 72 u64 tx_ucast; 73 u64 tx_deferred; 74 u64 tx_total_col; 75 u64 tx_exc_col; 76 u64 tx_single_col; 77 u64 tx_mult_col; 78 u64 rx_total; 79 u64 tx_total; 80 u64 rx_discards; 81 u64 tx_discards; 82 }; 83 84 struct ksz_port_mib { 85 struct mutex cnt_mutex; /* structure access */ 86 u8 cnt_ptr; 87 u64 *counters; 88 struct rtnl_link_stats64 stats64; 89 struct ethtool_pause_stats pause_stats; 90 struct spinlock stats64_lock; 91 }; 92 93 struct ksz_mib_names { 94 int index; 95 char string[ETH_GSTRING_LEN]; 96 }; 97 98 struct ksz_chip_data { 99 u32 chip_id; 100 const char *dev_name; 101 int num_vlans; 102 int num_alus; 103 int num_statics; 104 int cpu_ports; 105 int port_cnt; 106 u8 port_nirqs; 107 u8 num_tx_queues; 108 u8 num_ipms; /* number of Internal Priority Maps */ 109 bool tc_cbs_supported; 110 111 /** 112 * @phy_side_mdio_supported: Indicates if the chip supports an additional 113 * side MDIO channel for accessing integrated PHYs. 114 */ 115 bool phy_side_mdio_supported; 116 const struct ksz_dev_ops *ops; 117 const struct dsa_switch_ops *switch_ops; 118 const struct phylink_mac_ops *phylink_mac_ops; 119 bool phy_errata_9477; 120 bool ksz87xx_eee_link_erratum; 121 const struct ksz_mib_names *mib_names; 122 int mib_cnt; 123 u8 reg_mib_cnt; 124 const u16 *regs; 125 const u32 *masks; 126 const u8 *shifts; 127 const u8 *xmii_ctrl0; 128 const u8 *xmii_ctrl1; 129 int stp_ctrl_reg; 130 int broadcast_ctrl_reg; 131 int multicast_ctrl_reg; 132 int start_ctrl_reg; 133 bool supports_mii[KSZ_MAX_NUM_PORTS]; 134 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 135 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 136 bool internal_phy[KSZ_MAX_NUM_PORTS]; 137 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 138 bool ptp_capable; 139 u8 sgmii_port; 140 const struct regmap_access_table *wr_table; 141 const struct regmap_access_table *rd_table; 142 const u8 n_pins; 143 const u8 n_per_out; 144 }; 145 146 struct ksz_irq { 147 u16 masked; 148 u16 reg_mask; 149 u16 reg_status; 150 struct irq_domain *domain; 151 int nirqs; 152 int irq_num; 153 char name[16]; 154 struct ksz_device *dev; 155 u16 irq0_offset; 156 }; 157 158 struct ksz_ptp_irq { 159 struct ksz_port *port; 160 u16 ts_reg; 161 bool ts_en; 162 char name[16]; 163 int num; 164 }; 165 166 struct ksz_switch_macaddr { 167 unsigned char addr[ETH_ALEN]; 168 refcount_t refcount; 169 }; 170 171 struct ksz_port { 172 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 173 bool learning; 174 bool isolated; 175 int stp_state; 176 int speed; 177 int duplex; 178 bool link; 179 180 u32 fiber:1; /* port is fiber */ 181 u32 force:1; 182 u32 read:1; /* read MIB counters in background */ 183 u32 freeze:1; /* MIB counter freeze is enabled */ 184 u32 sgmii_adv_write:1; 185 186 struct ksz_port_mib mib; 187 phy_interface_t interface; 188 u32 rgmii_tx_val; 189 u32 rgmii_rx_val; 190 struct ksz_device *ksz_dev; 191 void *acl_priv; 192 struct ksz_irq pirq; 193 u8 num; 194 struct phylink_pcs *pcs; 195 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 196 struct kernel_hwtstamp_config tstamp_config; 197 bool hwts_tx_en; 198 bool hwts_rx_en; 199 bool last_tx_is_pdelayresp; 200 struct ksz_irq ptpirq; 201 struct ksz_ptp_irq ptpmsg_irq[3]; 202 ktime_t tstamp_msg; 203 struct completion tstamp_msg_comp; 204 #endif 205 bool manual_flow; 206 }; 207 208 struct ksz_device { 209 struct dsa_switch *ds; 210 struct ksz_platform_data *pdata; 211 const struct ksz_chip_data *info; 212 213 struct mutex dev_mutex; /* device access */ 214 struct mutex regmap_mutex; /* regmap access */ 215 struct mutex alu_mutex; /* ALU access */ 216 struct mutex vlan_mutex; /* vlan access */ 217 const struct ksz_dev_ops *dev_ops; 218 219 struct device *dev; 220 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 221 222 void *priv; 223 int irq; 224 225 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 226 227 /* chip specific data */ 228 u32 chip_id; 229 u8 chip_rev; 230 int cpu_port; /* port connected to CPU */ 231 int phy_port_cnt; 232 phy_interface_t compat_interface; 233 bool synclko_125; 234 bool synclko_disable; 235 bool wakeup_source; 236 bool pme_active_high; 237 238 struct vlan_table *vlan_cache; 239 240 struct ksz_port *ports; 241 struct delayed_work mib_read; 242 unsigned long mib_read_interval; 243 u16 mirror_rx; 244 u16 mirror_tx; 245 u16 port_mask; 246 struct mutex lock_irq; /* IRQ Access */ 247 struct ksz_irq girq; 248 struct ksz_ptp_data ptp_data; 249 250 struct ksz_switch_macaddr *switch_macaddr; 251 struct net_device *hsr_dev; /* HSR */ 252 u8 hsr_ports; 253 254 /** 255 * @phy_addr_map: Array mapping switch ports to their corresponding PHY 256 * addresses. 257 */ 258 u8 phy_addr_map[KSZ_MAX_NUM_PORTS]; 259 260 /** 261 * @parent_mdio_bus: Pointer to the external MDIO bus controller. 262 * 263 * This points to an external MDIO bus controller that is used to access 264 * the PHYs integrated within the switch. Unlike an integrated MDIO 265 * bus, this external controller provides a direct path for managing 266 * the switch’s internal PHYs, bypassing the main SPI interface. 267 */ 268 struct mii_bus *parent_mdio_bus; 269 270 /* KSZ87xx low-loss tuning state */ 271 u8 lpf_bw; /* KSZ87XX_PHY_LPF_* */ 272 u8 eq_init; /* DSP EQ initial value */ 273 }; 274 275 /* List of supported models */ 276 enum ksz_model { 277 KSZ8463, 278 KSZ8563, 279 KSZ8567, 280 KSZ8795, 281 KSZ8794, 282 KSZ8765, 283 KSZ88X3, 284 KSZ8864, 285 KSZ8895, 286 KSZ8995XA, 287 KSZ9477, 288 KSZ9896, 289 KSZ9897, 290 KSZ9897S, 291 KSZ9893, 292 KSZ9563, 293 KSZ9567, 294 LAN9370, 295 LAN9371, 296 LAN9372, 297 LAN9373, 298 LAN9374, 299 LAN9646, 300 }; 301 302 enum ksz_regs { 303 REG_SW_MAC_ADDR, 304 REG_IND_CTRL_0, 305 REG_IND_DATA_8, 306 REG_IND_DATA_CHECK, 307 REG_IND_DATA_HI, 308 REG_IND_DATA_LO, 309 REG_IND_MIB_CHECK, 310 REG_IND_BYTE, 311 P_FORCE_CTRL, 312 P_LINK_STATUS, 313 P_LOCAL_CTRL, 314 P_NEG_RESTART_CTRL, 315 P_REMOTE_STATUS, 316 P_SPEED_STATUS, 317 S_TAIL_TAG_CTRL, 318 P_STP_CTRL, 319 S_START_CTRL, 320 S_BROADCAST_CTRL, 321 S_MULTICAST_CTRL, 322 P_XMII_CTRL_0, 323 P_XMII_CTRL_1, 324 REG_SW_PME_CTRL, 325 REG_PORT_PME_STATUS, 326 REG_PORT_PME_CTRL, 327 PTP_CLK_CTRL, 328 PTP_RTC_NANOSEC, 329 PTP_RTC_SEC, 330 PTP_RTC_SUB_NANOSEC, 331 PTP_SUBNANOSEC_RATE, 332 PTP_MSG_CONF1, 333 }; 334 335 enum ksz_masks { 336 PORT_802_1P_REMAPPING, 337 SW_TAIL_TAG_ENABLE, 338 MIB_COUNTER_OVERFLOW, 339 MIB_COUNTER_VALID, 340 VLAN_TABLE_FID, 341 VLAN_TABLE_MEMBERSHIP, 342 VLAN_TABLE_VALID, 343 STATIC_MAC_TABLE_VALID, 344 STATIC_MAC_TABLE_USE_FID, 345 STATIC_MAC_TABLE_FID, 346 STATIC_MAC_TABLE_OVERRIDE, 347 STATIC_MAC_TABLE_FWD_PORTS, 348 DYNAMIC_MAC_TABLE_ENTRIES_H, 349 DYNAMIC_MAC_TABLE_MAC_EMPTY, 350 DYNAMIC_MAC_TABLE_NOT_READY, 351 DYNAMIC_MAC_TABLE_ENTRIES, 352 DYNAMIC_MAC_TABLE_FID, 353 DYNAMIC_MAC_TABLE_SRC_PORT, 354 DYNAMIC_MAC_TABLE_TIMESTAMP, 355 ALU_STAT_WRITE, 356 ALU_STAT_READ, 357 ALU_STAT_DIRECT, 358 ALU_RESV_MCAST_ADDR, 359 P_MII_TX_FLOW_CTRL, 360 P_MII_RX_FLOW_CTRL, 361 }; 362 363 enum ksz_shifts { 364 VLAN_TABLE_MEMBERSHIP_S, 365 VLAN_TABLE, 366 STATIC_MAC_FWD_PORTS, 367 STATIC_MAC_FID, 368 DYNAMIC_MAC_ENTRIES_H, 369 DYNAMIC_MAC_ENTRIES, 370 DYNAMIC_MAC_FID, 371 DYNAMIC_MAC_TIMESTAMP, 372 DYNAMIC_MAC_SRC_PORT, 373 ALU_STAT_INDEX, 374 }; 375 376 enum ksz_xmii_ctrl0 { 377 P_MII_100MBIT, 378 P_MII_10MBIT, 379 P_MII_FULL_DUPLEX, 380 P_MII_HALF_DUPLEX, 381 }; 382 383 enum ksz_xmii_ctrl1 { 384 P_RGMII_SEL, 385 P_RMII_SEL, 386 P_GMII_SEL, 387 P_MII_SEL, 388 P_GMII_1GBIT, 389 P_GMII_NOT_1GBIT, 390 }; 391 392 struct alu_struct { 393 /* entry 1 */ 394 u8 is_static:1; 395 u8 is_src_filter:1; 396 u8 is_dst_filter:1; 397 u8 prio_age:3; 398 u32 _reserv_0_1:23; 399 u8 mstp:3; 400 /* entry 2 */ 401 u8 is_override:1; 402 u8 is_use_fid:1; 403 u32 _reserv_1_1:23; 404 u8 port_forward:7; 405 /* entry 3 & 4*/ 406 u32 _reserv_2_1:9; 407 u8 fid:7; 408 u8 mac[ETH_ALEN]; 409 }; 410 411 struct ksz_dev_ops { 412 u32 (*get_port_addr)(int port, int offset); 413 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 414 415 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 416 u64 *cnt); 417 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 418 u64 *dropped, u64 *cnt); 419 void (*r_mib_stat64)(struct ksz_device *dev, int port); 420 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 421 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 422 u8 *data); 423 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 424 u8 data); 425 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 426 void (*port_init_cnt)(struct ksz_device *dev, int port); 427 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 428 int (*init)(struct ksz_device *dev); 429 }; 430 431 struct ksz_device *ksz_switch_alloc(struct device *base, 432 const struct ksz_chip_data *chip, 433 void *priv); 434 int ksz_switch_register(struct ksz_device *dev); 435 void ksz_switch_remove(struct ksz_device *dev); 436 int ksz_switch_suspend(struct device *dev); 437 int ksz_switch_resume(struct device *dev); 438 439 void ksz_teardown(struct dsa_switch *ds); 440 441 void ksz_init_mib_timer(struct ksz_device *dev); 442 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 443 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 444 extern const struct ksz_chip_data ksz_switch_chips[]; 445 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 446 struct netlink_ext_ack *extack); 447 void ksz_switch_macaddr_put(struct dsa_switch *ds); 448 void ksz_switch_shutdown(struct ksz_device *dev); 449 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 450 451 int ksz_sset_count(struct dsa_switch *ds, int port, int sset); 452 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 453 uint64_t *buf); 454 void ksz_get_stats64(struct dsa_switch *ds, int port, 455 struct rtnl_link_stats64 *s); 456 void ksz_get_pause_stats(struct dsa_switch *ds, int port, 457 struct ethtool_pause_stats *pause_stats); 458 void ksz_get_strings(struct dsa_switch *ds, int port, 459 u32 stringset, uint8_t *buf); 460 461 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 462 struct dsa_bridge bridge, 463 bool *tx_fwd_offload, 464 struct netlink_ext_ack *extack); 465 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 466 struct dsa_bridge bridge); 467 int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 468 struct switchdev_brport_flags flags, 469 struct netlink_ext_ack *extack); 470 int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 471 struct switchdev_brport_flags flags, 472 struct netlink_ext_ack *extack); 473 474 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 475 struct phylink_config *config); 476 void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config); 477 int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 478 u32 timer, bool tx_clock_stop); 479 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface); 480 bool ksz_phylink_need_config(struct phylink_config *config, unsigned int mode); 481 void ksz_phylink_mac_config(struct phylink_config *config, 482 unsigned int mode, 483 const struct phylink_link_state *state); 484 void ksz_phylink_mac_link_down(struct phylink_config *config, 485 unsigned int mode, 486 phy_interface_t interface); 487 488 int ksz_set_mac_eee(struct dsa_switch *ds, int port, 489 struct ethtool_keee *e); 490 491 int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 492 int band); 493 int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 494 struct tc_cbs_qopt_offload *qopt); 495 int ksz_tc_ets_validate(struct ksz_device *dev, int port, 496 struct tc_ets_qopt_offload_replace_params *p); 497 int ksz_setup_tc(struct dsa_switch *ds, int port, 498 enum tc_setup_type type, void *type_data); 499 500 void ksz_get_wol(struct dsa_switch *ds, int port, 501 struct ethtool_wolinfo *wol); 502 int ksz_set_wol(struct dsa_switch *ds, int port, 503 struct ethtool_wolinfo *wol); 504 int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 505 const unsigned char *addr); 506 507 int ksz_suspend(struct dsa_switch *ds); 508 int ksz_resume(struct dsa_switch *ds); 509 510 int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 511 struct device_node *mdio_np); 512 int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum); 513 int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val); 514 int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum); 515 int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val); 516 int ksz_mdio_register(struct ksz_device *dev); 517 void ksz_irq_bus_lock(struct irq_data *d); 518 void ksz_irq_bus_sync_unlock(struct irq_data *d); 519 int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq, 520 const struct irq_domain_ops *ops); 521 int ksz_pirq_setup(struct ksz_device *dev, u8 p); 522 int ksz_girq_setup(struct ksz_device *dev); 523 void ksz_irq_free(struct ksz_irq *kirq); 524 525 struct ksz_driver_strength_prop { 526 const char *name; 527 int offset; 528 int value; 529 }; 530 531 enum ksz_driver_strength_type { 532 KSZ_DRIVER_STRENGTH_HI, 533 KSZ_DRIVER_STRENGTH_LO, 534 KSZ_DRIVER_STRENGTH_IO, 535 }; 536 537 /** 538 * struct ksz_drive_strength - drive strength mapping 539 * @reg_val: register value 540 * @microamp: microamp value 541 */ 542 struct ksz_drive_strength { 543 u32 reg_val; 544 u32 microamp; 545 }; 546 547 void ksz_drive_strength_error(struct ksz_device *dev, 548 const struct ksz_drive_strength *array, 549 size_t array_size, int microamp); 550 int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 551 size_t array_size, int microamp); 552 int ksz_drive_strength_write(struct ksz_device *dev, 553 struct ksz_driver_strength_prop *props, 554 int num_props); 555 556 /* Common register access functions */ 557 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 558 { 559 return dev->regmap[KSZ_REGMAP_8]; 560 } 561 562 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 563 { 564 return dev->regmap[KSZ_REGMAP_16]; 565 } 566 567 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 568 { 569 return dev->regmap[KSZ_REGMAP_32]; 570 } 571 572 static inline bool ksz_is_ksz8463(struct ksz_device *dev) 573 { 574 return dev->chip_id == KSZ8463_CHIP_ID; 575 } 576 577 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 578 { 579 unsigned int value; 580 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 581 582 if (ret) 583 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 584 ERR_PTR(ret)); 585 586 *val = value; 587 return ret; 588 } 589 590 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 591 { 592 unsigned int value; 593 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 594 595 if (ret) 596 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 597 ERR_PTR(ret)); 598 599 *val = value; 600 return ret; 601 } 602 603 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 604 { 605 unsigned int value; 606 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 607 608 if (ret) 609 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 610 ERR_PTR(ret)); 611 612 *val = value; 613 return ret; 614 } 615 616 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 617 { 618 u32 value[2]; 619 int ret; 620 621 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 622 if (ret) 623 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 624 ERR_PTR(ret)); 625 else 626 *val = (u64)value[0] << 32 | value[1]; 627 628 return ret; 629 } 630 631 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 632 { 633 int ret; 634 635 ret = regmap_write(ksz_regmap_8(dev), reg, value); 636 if (ret) 637 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 638 ERR_PTR(ret)); 639 640 return ret; 641 } 642 643 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 644 { 645 int ret; 646 647 ret = regmap_write(ksz_regmap_16(dev), reg, value); 648 if (ret) 649 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 650 ERR_PTR(ret)); 651 652 return ret; 653 } 654 655 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 656 { 657 int ret; 658 659 ret = regmap_write(ksz_regmap_32(dev), reg, value); 660 if (ret) 661 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 662 ERR_PTR(ret)); 663 664 return ret; 665 } 666 667 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 668 u16 value) 669 { 670 int ret; 671 672 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 673 if (ret) 674 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 675 ERR_PTR(ret)); 676 677 return ret; 678 } 679 680 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 681 u32 value) 682 { 683 int ret; 684 685 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 686 if (ret) 687 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 688 ERR_PTR(ret)); 689 690 return ret; 691 } 692 693 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 694 { 695 u32 val[2]; 696 697 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 698 value = swab64(value); 699 val[0] = swab32(value & 0xffffffffULL); 700 val[1] = swab32(value >> 32ULL); 701 702 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 703 } 704 705 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 706 { 707 int ret; 708 709 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 710 if (ret) 711 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 712 ERR_PTR(ret)); 713 714 return ret; 715 } 716 717 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 718 u8 *data) 719 { 720 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 721 } 722 723 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 724 u16 *data) 725 { 726 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 727 } 728 729 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 730 u32 *data) 731 { 732 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 733 } 734 735 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 736 u8 data) 737 { 738 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 739 } 740 741 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 742 u16 data) 743 { 744 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 745 data); 746 } 747 748 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 749 u32 data) 750 { 751 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 752 data); 753 } 754 755 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 756 u8 mask, u8 val) 757 { 758 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 759 mask, val); 760 } 761 762 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 763 u32 mask, u32 val) 764 { 765 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 766 mask, val); 767 } 768 769 static inline void ksz_regmap_lock(void *__mtx) 770 { 771 struct mutex *mtx = __mtx; 772 mutex_lock(mtx); 773 } 774 775 static inline void ksz_regmap_unlock(void *__mtx) 776 { 777 struct mutex *mtx = __mtx; 778 mutex_unlock(mtx); 779 } 780 781 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 782 { 783 return dev->chip_id == KSZ8795_CHIP_ID || 784 dev->chip_id == KSZ8794_CHIP_ID || 785 dev->chip_id == KSZ8765_CHIP_ID; 786 } 787 788 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 789 { 790 return dev->chip_id == KSZ88X3_CHIP_ID; 791 } 792 793 static inline bool ksz_is_8895_family(struct ksz_device *dev) 794 { 795 return dev->chip_id == KSZ8895_CHIP_ID || 796 dev->chip_id == KSZ8864_CHIP_ID || 797 dev->chip_id == KSZ8995XA_CHIP_ID; 798 } 799 800 static inline bool ksz_is_ksz8995xa(struct ksz_device *dev) 801 { 802 return dev->chip_id == KSZ8995XA_CHIP_ID; 803 } 804 805 static inline bool is_ksz8(struct ksz_device *dev) 806 { 807 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 808 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev); 809 } 810 811 static inline bool is_ksz88xx(struct ksz_device *dev) 812 { 813 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) || 814 ksz_is_ksz8463(dev); 815 } 816 817 static inline bool is_ksz9477(struct ksz_device *dev) 818 { 819 return dev->chip_id == KSZ9477_CHIP_ID; 820 } 821 822 static inline int is_lan937x(struct ksz_device *dev) 823 { 824 return dev->chip_id == LAN9370_CHIP_ID || 825 dev->chip_id == LAN9371_CHIP_ID || 826 dev->chip_id == LAN9372_CHIP_ID || 827 dev->chip_id == LAN9373_CHIP_ID || 828 dev->chip_id == LAN9374_CHIP_ID; 829 } 830 831 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 832 { 833 return (dev->chip_id == LAN9371_CHIP_ID || 834 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 835 } 836 837 static inline int ksz_get_sgmii_port(struct ksz_device *dev) 838 { 839 return dev->info->sgmii_port - 1; 840 } 841 842 static inline bool ksz_has_sgmii_port(struct ksz_device *dev) 843 { 844 return dev->info->sgmii_port > 0; 845 } 846 847 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port) 848 { 849 return dev->info->sgmii_port == port + 1; 850 } 851 852 /* STP State Defines */ 853 #define PORT_TX_ENABLE BIT(2) 854 #define PORT_RX_ENABLE BIT(1) 855 #define PORT_LEARN_DISABLE BIT(0) 856 857 /* Switch ID Defines */ 858 #define REG_CHIP_ID0 0x00 859 860 #define SW_FAMILY_ID_M GENMASK(15, 8) 861 #define KSZ84_FAMILY_ID 0x84 862 #define KSZ87_FAMILY_ID 0x87 863 #define KSZ88_FAMILY_ID 0x88 864 #define KSZ8895_FAMILY_ID 0x95 865 866 #define KSZ8_PORT_STATUS_0 0x18 867 #define KSZ8_PORT_FIBER_MODE BIT(7) 868 869 #define SW_CHIP_ID_M GENMASK(7, 4) 870 #define KSZ87_CHIP_ID_94 0x6 871 #define KSZ87_CHIP_ID_95 0x9 872 #define KSZ88_CHIP_ID_63 0x3 873 #define KSZ8895_CHIP_ID_95XA 0x0 874 #define KSZ8895_CHIP_ID_95 0x4 875 #define KSZ8895_CHIP_ID_95R 0x6 876 877 /* KSZ8895 specific register */ 878 #define REG_KSZ8864_CHIP_ID 0xFE 879 #define SW_KSZ8864 BIT(7) 880 881 #define SW_REV_ID_M GENMASK(7, 4) 882 883 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 884 #define REG_CHIP_ID4 0x0f 885 #define SKU_ID_KSZ8563 0x3c 886 #define SKU_ID_KSZ9563 0x1c 887 888 /* KSZ9897 specific register: port 7 XMII control 0 */ 889 #define KSZ9897_REG_PORT7_XMII_CTRL_0 0x7300 890 #define KSZ9897_PORT7_SGMII_SEL BIT(7) 891 892 /* Driver set switch broadcast storm protection at 10% rate. */ 893 #define BROADCAST_STORM_PROT_RATE 10 894 895 /* 148,800 frames * 67 ms / 100 */ 896 #define BROADCAST_STORM_VALUE 9969 897 898 #define BROADCAST_STORM_RATE_HI 0x07 899 #define BROADCAST_STORM_RATE_LO 0xFF 900 #define BROADCAST_STORM_RATE 0x07FF 901 902 #define MULTICAST_STORM_DISABLE BIT(6) 903 904 #define SW_START 0x01 905 906 /* xMII configuration */ 907 #define P_MII_DUPLEX_M BIT(6) 908 #define P_MII_100MBIT_M BIT(4) 909 910 #define P_GMII_1GBIT_M BIT(6) 911 #define P_RGMII_ID_IG_ENABLE BIT(4) 912 #define P_RGMII_ID_EG_ENABLE BIT(3) 913 #define P_MII_MAC_MODE BIT(2) 914 #define P_MII_SEL_M 0x3 915 916 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 917 #define PME_WOL_MAGICPKT BIT(2) 918 #define PME_WOL_LINKUP BIT(1) 919 #define PME_WOL_ENERGY BIT(0) 920 921 #define PME_ENABLE BIT(1) 922 #define PME_POLARITY BIT(0) 923 924 #define KSZ87XX_REG_INT_EN 0x7D 925 #define KSZ87XX_INT_PME_MASK BIT(4) 926 927 /* Interrupt */ 928 #define REG_SW_PORT_INT_STATUS__1 0x001B 929 #define REG_SW_PORT_INT_MASK__1 0x001F 930 931 #define REG_PORT_INT_STATUS 0x001B 932 #define REG_PORT_INT_MASK 0x001F 933 934 #define PORT_SRC_PHY_INT 1 935 #define PORT_SRC_PTP_INT 2 936 937 #define KSZ8795_HUGE_PACKET_SIZE 2000 938 #define KSZ8863_HUGE_PACKET_SIZE 1916 939 #define KSZ8863_NORMAL_PACKET_SIZE 1536 940 #define KSZ8_LEGAL_PACKET_SIZE 1518 941 #define KSZ8995XA_LEGAL_PACKET_SIZE 1522 942 #define KSZ9477_MAX_FRAME_SIZE 9000 943 944 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 945 /* Drive Strength of I/O Pad 946 * 0: 8mA, 1: 16mA 947 */ 948 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 949 950 #define KSZ8795_REG_SW_CTRL_20 0xa3 951 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 952 #define SW_DRIVE_STRENGTH_M 0x7 953 #define SW_DRIVE_STRENGTH_2MA 0 954 #define SW_DRIVE_STRENGTH_4MA 1 955 #define SW_DRIVE_STRENGTH_8MA 2 956 #define SW_DRIVE_STRENGTH_12MA 3 957 #define SW_DRIVE_STRENGTH_16MA 4 958 #define SW_DRIVE_STRENGTH_20MA 5 959 #define SW_DRIVE_STRENGTH_24MA 6 960 #define SW_DRIVE_STRENGTH_28MA 7 961 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 962 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 963 964 /* TXQ Split Control Register for per-port, per-queue configuration. 965 * Register 0xAF is TXQ Split for Q3 on Port 1. 966 * Register offset formula: 0xAF + (port * 4) + (3 - queue) 967 * where: port = 0..2, queue = 0..3 968 */ 969 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \ 970 (0xAF + ((port) * 4) + (3 - (queue))) 971 972 /* Bit 7 selects between: 973 * 0 = Strict priority mode (highest-priority queue first) 974 * 1 = Weighted Fair Queuing (WFQ) mode: 975 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1 976 * If any queues are empty, weight is redistributed. 977 * 978 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873 979 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs. 980 */ 981 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7) 982 983 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 984 #define KSZ9477_OUT_RATE_NO_LIMIT 0 985 986 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 987 988 #define KSZ9477_PORT_TC_MAP_S 4 989 990 /* CBS related registers */ 991 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 992 993 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 994 995 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 996 #define MTI_SCHEDULE_STRICT_PRIO 0 997 #define MTI_SCHEDULE_WRR 2 998 #define MTI_SHAPING_M GENMASK(5, 4) 999 #define MTI_SHAPING_OFF 0 1000 #define MTI_SHAPING_SRP 1 1001 #define MTI_SHAPING_TIME_AWARE 2 1002 1003 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 1004 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 1005 1006 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 1007 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 1008 1009 /* Regmap tables generation */ 1010 #define KSZ_SPI_OP_RD 3 1011 #define KSZ_SPI_OP_WR 2 1012 1013 #define swabnot_used(x) 0 1014 1015 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 1016 swab##swp((opcode) << ((regbits) + (regpad))) 1017 1018 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 1019 { \ 1020 .name = #width, \ 1021 .val_bits = (width), \ 1022 .reg_stride = 1, \ 1023 .reg_bits = (regbits) + (regalign), \ 1024 .pad_bits = (regpad), \ 1025 .max_register = BIT(regbits) - 1, \ 1026 .cache_type = REGCACHE_NONE, \ 1027 .read_flag_mask = \ 1028 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 1029 regbits, regpad), \ 1030 .write_flag_mask = \ 1031 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 1032 regbits, regpad), \ 1033 .lock = ksz_regmap_lock, \ 1034 .unlock = ksz_regmap_unlock, \ 1035 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 1036 .val_format_endian = REGMAP_ENDIAN_BIG \ 1037 } 1038 1039 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 1040 static const struct regmap_config ksz##_regmap_config[] = { \ 1041 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 1042 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 1043 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 1044 } 1045 1046 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \ 1047 { \ 1048 .name = #width, \ 1049 .val_bits = (width), \ 1050 .reg_stride = (width / 8), \ 1051 .reg_bits = (regbits) + (regalign), \ 1052 .pad_bits = (regpad), \ 1053 .read = ksz8463_spi_read, \ 1054 .write = ksz8463_spi_write, \ 1055 .max_register = BIT(regbits) - 1, \ 1056 .cache_type = REGCACHE_NONE, \ 1057 .zero_flag_mask = 1, \ 1058 .use_single_read = 1, \ 1059 .use_single_write = 1, \ 1060 .lock = ksz_regmap_lock, \ 1061 .unlock = ksz_regmap_unlock, \ 1062 } 1063 1064 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \ 1065 static const struct regmap_config ksz##_regmap_config[] = { \ 1066 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \ 1067 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \ 1068 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \ 1069 } 1070 1071 #endif 1072