1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4 #ifndef __PVR_ROGUE_FWIF_DEV_INFO_H__ 5 #define __PVR_ROGUE_FWIF_DEV_INFO_H__ 6 7 enum { 8 PVR_FW_HAS_BRN_44079 = 0, 9 PVR_FW_HAS_BRN_47217, 10 PVR_FW_HAS_BRN_48492, 11 PVR_FW_HAS_BRN_48545, 12 PVR_FW_HAS_BRN_49927, 13 PVR_FW_HAS_BRN_50767, 14 PVR_FW_HAS_BRN_51764, 15 PVR_FW_HAS_BRN_62269, 16 PVR_FW_HAS_BRN_63142, 17 PVR_FW_HAS_BRN_63553, 18 PVR_FW_HAS_BRN_66011, 19 PVR_FW_HAS_BRN_71242, 20 21 PVR_FW_HAS_BRN_MAX 22 }; 23 24 enum { 25 PVR_FW_HAS_ERN_35421 = 0, 26 PVR_FW_HAS_ERN_38020, 27 PVR_FW_HAS_ERN_38748, 28 PVR_FW_HAS_ERN_42064, 29 PVR_FW_HAS_ERN_42290, 30 PVR_FW_HAS_ERN_42606, 31 PVR_FW_HAS_ERN_47025, 32 PVR_FW_HAS_ERN_57596, 33 34 PVR_FW_HAS_ERN_MAX 35 }; 36 37 enum { 38 PVR_FW_HAS_FEATURE_AXI_ACELITE = 0, 39 PVR_FW_HAS_FEATURE_CDM_CONTROL_STREAM_FORMAT, 40 PVR_FW_HAS_FEATURE_CLUSTER_GROUPING, 41 PVR_FW_HAS_FEATURE_COMMON_STORE_SIZE_IN_DWORDS, 42 PVR_FW_HAS_FEATURE_COMPUTE, 43 PVR_FW_HAS_FEATURE_COMPUTE_MORTON_CAPABLE, 44 PVR_FW_HAS_FEATURE_COMPUTE_OVERLAP, 45 PVR_FW_HAS_FEATURE_COREID_PER_OS, 46 PVR_FW_HAS_FEATURE_DYNAMIC_DUST_POWER, 47 PVR_FW_HAS_FEATURE_ECC_RAMS, 48 PVR_FW_HAS_FEATURE_FBCDC, 49 PVR_FW_HAS_FEATURE_FBCDC_ALGORITHM, 50 PVR_FW_HAS_FEATURE_FBCDC_ARCHITECTURE, 51 PVR_FW_HAS_FEATURE_FBC_MAX_DEFAULT_DESCRIPTORS, 52 PVR_FW_HAS_FEATURE_FBC_MAX_LARGE_DESCRIPTORS, 53 PVR_FW_HAS_FEATURE_FB_CDC_V4, 54 PVR_FW_HAS_FEATURE_GPU_MULTICORE_SUPPORT, 55 PVR_FW_HAS_FEATURE_GPU_VIRTUALISATION, 56 PVR_FW_HAS_FEATURE_GS_RTA_SUPPORT, 57 PVR_FW_HAS_FEATURE_IRQ_PER_OS, 58 PVR_FW_HAS_FEATURE_ISP_MAX_TILES_IN_FLIGHT, 59 PVR_FW_HAS_FEATURE_ISP_SAMPLES_PER_PIXEL, 60 PVR_FW_HAS_FEATURE_ISP_ZLS_D24_S8_PACKING_OGL_MODE, 61 PVR_FW_HAS_FEATURE_LAYOUT_MARS, 62 PVR_FW_HAS_FEATURE_MAX_PARTITIONS, 63 PVR_FW_HAS_FEATURE_META, 64 PVR_FW_HAS_FEATURE_META_COREMEM_SIZE, 65 PVR_FW_HAS_FEATURE_MIPS, 66 PVR_FW_HAS_FEATURE_NUM_CLUSTERS, 67 PVR_FW_HAS_FEATURE_NUM_ISP_IPP_PIPES, 68 PVR_FW_HAS_FEATURE_NUM_OSIDS, 69 PVR_FW_HAS_FEATURE_NUM_RASTER_PIPES, 70 PVR_FW_HAS_FEATURE_PBE2_IN_XE, 71 PVR_FW_HAS_FEATURE_PBVNC_COREID_REG, 72 PVR_FW_HAS_FEATURE_PERFBUS, 73 PVR_FW_HAS_FEATURE_PERF_COUNTER_BATCH, 74 PVR_FW_HAS_FEATURE_PHYS_BUS_WIDTH, 75 PVR_FW_HAS_FEATURE_RISCV_FW_PROCESSOR, 76 PVR_FW_HAS_FEATURE_ROGUEXE, 77 PVR_FW_HAS_FEATURE_S7_TOP_INFRASTRUCTURE, 78 PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT, 79 PVR_FW_HAS_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT_V2, 80 PVR_FW_HAS_FEATURE_SIMPLE_PARAMETER_FORMAT_VERSION, 81 PVR_FW_HAS_FEATURE_SLC_BANKS, 82 PVR_FW_HAS_FEATURE_SLC_CACHE_LINE_SIZE_BITS, 83 PVR_FW_HAS_FEATURE_SLC_SIZE_CONFIGURABLE, 84 PVR_FW_HAS_FEATURE_SLC_SIZE_IN_KILOBYTES, 85 PVR_FW_HAS_FEATURE_SOC_TIMER, 86 PVR_FW_HAS_FEATURE_SYS_BUS_SECURE_RESET, 87 PVR_FW_HAS_FEATURE_TESSELLATION, 88 PVR_FW_HAS_FEATURE_TILE_REGION_PROTECTION, 89 PVR_FW_HAS_FEATURE_TILE_SIZE_X, 90 PVR_FW_HAS_FEATURE_TILE_SIZE_Y, 91 PVR_FW_HAS_FEATURE_TLA, 92 PVR_FW_HAS_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS, 93 PVR_FW_HAS_FEATURE_TPU_DM_GLOBAL_REGISTERS, 94 PVR_FW_HAS_FEATURE_TPU_FILTERING_MODE_CONTROL, 95 PVR_FW_HAS_FEATURE_USC_MIN_OUTPUT_REGISTERS_PER_PIX, 96 PVR_FW_HAS_FEATURE_VDM_DRAWINDIRECT, 97 PVR_FW_HAS_FEATURE_VDM_OBJECT_LEVEL_LLS, 98 PVR_FW_HAS_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS, 99 PVR_FW_HAS_FEATURE_WATCHDOG_TIMER, 100 PVR_FW_HAS_FEATURE_WORKGROUP_PROTECTION, 101 PVR_FW_HAS_FEATURE_XE_ARCHITECTURE, 102 PVR_FW_HAS_FEATURE_XE_MEMORY_HIERARCHY, 103 PVR_FW_HAS_FEATURE_XE_TPU2, 104 PVR_FW_HAS_FEATURE_XPU_MAX_REGBANKS_ADDR_WIDTH, 105 PVR_FW_HAS_FEATURE_XPU_MAX_SLAVES, 106 PVR_FW_HAS_FEATURE_XPU_REGISTER_BROADCAST, 107 PVR_FW_HAS_FEATURE_XT_TOP_INFRASTRUCTURE, 108 PVR_FW_HAS_FEATURE_ZLS_SUBTILE, 109 110 PVR_FW_HAS_FEATURE_MAX 111 }; 112 113 #endif /* __PVR_ROGUE_FWIF_DEV_INFO_H__ */ 114