1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_MMU_H
3 #define __KVM_X86_MMU_H
4
5 #include <linux/kvm_host.h>
6 #include "kvm_cache_regs.h"
7 #include "x86.h"
8 #include "cpuid.h"
9
10 extern bool __read_mostly enable_mmio_caching;
11
12 #define PT_WRITABLE_SHIFT 1
13 #define PT_USER_SHIFT 2
14
15 #define PT_PRESENT_MASK (1ULL << 0)
16 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
17 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
18 #define PT_PWT_MASK (1ULL << 3)
19 #define PT_PCD_MASK (1ULL << 4)
20 #define PT_ACCESSED_SHIFT 5
21 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
22 #define PT_DIRTY_SHIFT 6
23 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
24 #define PT_PAGE_SIZE_SHIFT 7
25 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
26 #define PT_PAT_MASK (1ULL << 7)
27 #define PT_GLOBAL_MASK (1ULL << 8)
28 #define PT64_NX_SHIFT 63
29 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
30
31 #define PT_PAT_SHIFT 7
32 #define PT_DIR_PAT_SHIFT 12
33 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
34
35 #define PT64_ROOT_5LEVEL 5
36 #define PT64_ROOT_4LEVEL 4
37 #define PT32_ROOT_LEVEL 2
38 #define PT32E_ROOT_LEVEL 3
39
40 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
41 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
42
43 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
44 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
45
rsvd_bits(int s,int e)46 static __always_inline u64 rsvd_bits(int s, int e)
47 {
48 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
49
50 if (__builtin_constant_p(e))
51 BUILD_BUG_ON(e > 63);
52 else
53 e &= 63;
54
55 if (e < s)
56 return 0;
57
58 return ((2ULL << (e - s)) - 1) << s;
59 }
60
kvm_mmu_max_gfn(void)61 static inline gfn_t kvm_mmu_max_gfn(void)
62 {
63 /*
64 * Note that this uses the host MAXPHYADDR, not the guest's.
65 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
66 * assuming KVM is running on bare metal, guest accesses beyond
67 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
68 * (either EPT Violation/Misconfig or #NPF), and so KVM will never
69 * install a SPTE for such addresses. If KVM is running as a VM
70 * itself, on the other hand, it might see a MAXPHYADDR that is less
71 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR
72 * disallows such SPTEs entirely and simplifies the TDP MMU.
73 */
74 int max_gpa_bits = likely(tdp_enabled) ? kvm_host.maxphyaddr : 52;
75
76 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
77 }
78
79 u8 kvm_mmu_get_max_tdp_level(void);
80
81 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
82 void kvm_mmu_set_mmio_spte_value(struct kvm *kvm, u64 mmio_value);
83 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
84 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
85
86 void kvm_init_mmu(struct kvm_vcpu *vcpu);
87 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
88 unsigned long cr4, u64 efer, gpa_t nested_cr3);
89 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
90 int huge_page_level, bool accessed_dirty,
91 gpa_t new_eptp);
92 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
93 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
94 u64 fault_address, char *insn, int insn_len);
95 void __kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
96 struct kvm_mmu *mmu);
97
98 int kvm_mmu_load(struct kvm_vcpu *vcpu);
99 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
100 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
101 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
102 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
103 void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
104 int bytes);
105
kvm_mmu_reload(struct kvm_vcpu * vcpu)106 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
107 {
108 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
109 kvm_mmu_free_obsolete_roots(vcpu);
110
111 /*
112 * Checking root.hpa is sufficient even when KVM has mirror root.
113 * We can have either:
114 * (1) mirror_root_hpa = INVALID_PAGE, root.hpa = INVALID_PAGE
115 * (2) mirror_root_hpa = root, root.hpa = INVALID_PAGE
116 * (3) mirror_root_hpa = root1, root.hpa = root2
117 * We don't ever have:
118 * mirror_root_hpa = INVALID_PAGE, root.hpa = root
119 */
120 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
121 return 0;
122
123 return kvm_mmu_load(vcpu);
124 }
125
kvm_get_pcid(struct kvm_vcpu * vcpu,gpa_t cr3)126 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
127 {
128 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
129
130 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)
131 ? cr3 & X86_CR3_PCID_MASK
132 : 0;
133 }
134
kvm_get_active_pcid(struct kvm_vcpu * vcpu)135 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
136 {
137 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
138 }
139
kvm_get_active_cr3_lam_bits(struct kvm_vcpu * vcpu)140 static inline unsigned long kvm_get_active_cr3_lam_bits(struct kvm_vcpu *vcpu)
141 {
142 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_LAM))
143 return 0;
144
145 return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57);
146 }
147
kvm_mmu_load_pgd(struct kvm_vcpu * vcpu)148 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
149 {
150 u64 root_hpa = vcpu->arch.mmu->root.hpa;
151
152 if (!VALID_PAGE(root_hpa))
153 return;
154
155 kvm_x86_call(load_mmu_pgd)(vcpu, root_hpa,
156 vcpu->arch.mmu->root_role.level);
157 }
158
kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu)159 static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu,
160 struct kvm_mmu *mmu)
161 {
162 /*
163 * When EPT is enabled, KVM may passthrough CR0.WP to the guest, i.e.
164 * @mmu's snapshot of CR0.WP and thus all related paging metadata may
165 * be stale. Refresh CR0.WP and the metadata on-demand when checking
166 * for permission faults. Exempt nested MMUs, i.e. MMUs for shadowing
167 * nEPT and nNPT, as CR0.WP is ignored in both cases. Note, KVM does
168 * need to refresh nested_mmu, a.k.a. the walker used to translate L2
169 * GVAs to GPAs, as that "MMU" needs to honor L2's CR0.WP.
170 */
171 if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu)
172 return;
173
174 __kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
175 }
176
177 /*
178 * Check if a given access (described through the I/D, W/R and U/S bits of a
179 * page fault error code pfec) causes a permission fault with the given PTE
180 * access rights (in ACC_* format).
181 *
182 * Return zero if the access does not fault; return the page fault error code
183 * if the access faults.
184 */
permission_fault(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu,unsigned pte_access,unsigned pte_pkey,u64 access)185 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
186 unsigned pte_access, unsigned pte_pkey,
187 u64 access)
188 {
189 /* strip nested paging fault error codes */
190 unsigned int pfec = access;
191 unsigned long rflags = kvm_x86_call(get_rflags)(vcpu);
192
193 /*
194 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
195 * For implicit supervisor accesses, SMAP cannot be overridden.
196 *
197 * SMAP works on supervisor accesses only, and not_smap can
198 * be set or not set when user access with neither has any bearing
199 * on the result.
200 *
201 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
202 * this bit will always be zero in pfec, but it will be one in index
203 * if SMAP checks are being disabled.
204 */
205 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
206 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
207 int index = (pfec | (not_smap ? PFERR_RSVD_MASK : 0)) >> 1;
208 u32 errcode = PFERR_PRESENT_MASK;
209 bool fault;
210
211 kvm_mmu_refresh_passthrough_bits(vcpu, mmu);
212
213 fault = (mmu->permissions[index] >> pte_access) & 1;
214
215 WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
216 if (unlikely(mmu->pkru_mask)) {
217 u32 pkru_bits, offset;
218
219 /*
220 * PKRU defines 32 bits, there are 16 domains and 2
221 * attribute bits per domain in pkru. pte_pkey is the
222 * index of the protection domain, so pte_pkey * 2 is
223 * is the index of the first bit for the domain.
224 */
225 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
226
227 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
228 offset = (pfec & ~1) | ((pte_access & PT_USER_MASK) ? PFERR_RSVD_MASK : 0);
229
230 pkru_bits &= mmu->pkru_mask >> offset;
231 errcode |= -pkru_bits & PFERR_PK_MASK;
232 fault |= (pkru_bits != 0);
233 }
234
235 return -(u32)fault & errcode;
236 }
237
238 bool kvm_mmu_may_ignore_guest_pat(struct kvm *kvm);
239
240 int kvm_mmu_post_init_vm(struct kvm *kvm);
241 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
242
kvm_shadow_root_allocated(struct kvm * kvm)243 static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
244 {
245 /*
246 * Read shadow_root_allocated before related pointers. Hence, threads
247 * reading shadow_root_allocated in any lock context are guaranteed to
248 * see the pointers. Pairs with smp_store_release in
249 * mmu_first_shadow_root_alloc.
250 */
251 return smp_load_acquire(&kvm->arch.shadow_root_allocated);
252 }
253
254 #ifdef CONFIG_X86_64
255 extern bool tdp_mmu_enabled;
256 #else
257 #define tdp_mmu_enabled false
258 #endif
259
260 bool kvm_tdp_mmu_gpa_is_mapped(struct kvm_vcpu *vcpu, u64 gpa);
261 int kvm_tdp_map_page(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code, u8 *level);
262
kvm_memslots_have_rmaps(struct kvm * kvm)263 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
264 {
265 return !tdp_mmu_enabled || kvm_shadow_root_allocated(kvm);
266 }
267
gfn_to_index(gfn_t gfn,gfn_t base_gfn,int level)268 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
269 {
270 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
271 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
272 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
273 }
274
275 static inline unsigned long
__kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,unsigned long npages,int level)276 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
277 int level)
278 {
279 return gfn_to_index(slot->base_gfn + npages - 1,
280 slot->base_gfn, level) + 1;
281 }
282
283 static inline unsigned long
kvm_mmu_slot_lpages(struct kvm_memory_slot * slot,int level)284 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
285 {
286 return __kvm_mmu_slot_lpages(slot, slot->npages, level);
287 }
288
kvm_update_page_stats(struct kvm * kvm,int level,int count)289 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
290 {
291 atomic64_add(count, &kvm->stat.pages[level - 1]);
292 }
293
294 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
295 struct x86_exception *exception);
296
kvm_translate_gpa(struct kvm_vcpu * vcpu,struct kvm_mmu * mmu,gpa_t gpa,u64 access,struct x86_exception * exception)297 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
298 struct kvm_mmu *mmu,
299 gpa_t gpa, u64 access,
300 struct x86_exception *exception)
301 {
302 if (mmu != &vcpu->arch.nested_mmu)
303 return gpa;
304 return translate_nested_gpa(vcpu, gpa, access, exception);
305 }
306
kvm_has_mirrored_tdp(const struct kvm * kvm)307 static inline bool kvm_has_mirrored_tdp(const struct kvm *kvm)
308 {
309 return kvm->arch.vm_type == KVM_X86_TDX_VM;
310 }
311
kvm_gfn_direct_bits(const struct kvm * kvm)312 static inline gfn_t kvm_gfn_direct_bits(const struct kvm *kvm)
313 {
314 return kvm->arch.gfn_direct_bits;
315 }
316
kvm_is_addr_direct(struct kvm * kvm,gpa_t gpa)317 static inline bool kvm_is_addr_direct(struct kvm *kvm, gpa_t gpa)
318 {
319 gpa_t gpa_direct_bits = gfn_to_gpa(kvm_gfn_direct_bits(kvm));
320
321 return !gpa_direct_bits || (gpa & gpa_direct_bits);
322 }
323
kvm_is_gfn_alias(struct kvm * kvm,gfn_t gfn)324 static inline bool kvm_is_gfn_alias(struct kvm *kvm, gfn_t gfn)
325 {
326 return gfn & kvm_gfn_direct_bits(kvm);
327 }
328 #endif
329