1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_MMU_H 3 #define __KVM_X86_MMU_H 4 5 #include <linux/kvm_host.h> 6 #include "regs.h" 7 #include "x86.h" 8 #include "cpuid.h" 9 10 extern bool __read_mostly enable_mmio_caching; 11 12 #define PT_WRITABLE_SHIFT 1 13 #define PT_USER_SHIFT 2 14 15 #define PT_PRESENT_MASK (1ULL << 0) 16 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT) 17 #define PT_USER_MASK (1ULL << PT_USER_SHIFT) 18 #define PT_PWT_MASK (1ULL << 3) 19 #define PT_PCD_MASK (1ULL << 4) 20 #define PT_ACCESSED_SHIFT 5 21 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT) 22 #define PT_DIRTY_SHIFT 6 23 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT) 24 #define PT_PAGE_SIZE_SHIFT 7 25 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT) 26 #define PT_PAT_MASK (1ULL << 7) 27 #define PT_GLOBAL_MASK (1ULL << 8) 28 #define PT64_NX_SHIFT 63 29 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT) 30 31 #define PT_PAT_SHIFT 7 32 #define PT_DIR_PAT_SHIFT 12 33 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT) 34 35 #define PT64_ROOT_5LEVEL 5 36 #define PT64_ROOT_4LEVEL 4 37 #define PT32_ROOT_LEVEL 2 38 #define PT32E_ROOT_LEVEL 3 39 40 #define ACC_READ_MASK PT_PRESENT_MASK 41 #define ACC_WRITE_MASK PT_WRITABLE_MASK 42 #define ACC_USER_MASK PT_USER_MASK /* non EPT */ 43 #define ACC_USER_EXEC_MASK ACC_USER_MASK /* EPT only */ 44 #define ACC_EXEC_MASK 8 45 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK | ACC_READ_MASK) 46 47 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ 48 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) 49 50 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) 51 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX) 52 53 static __always_inline u64 rsvd_bits(int s, int e) 54 { 55 BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s); 56 57 if (__builtin_constant_p(e)) 58 BUILD_BUG_ON(e > 63); 59 else 60 e &= 63; 61 62 if (e < s) 63 return 0; 64 65 return ((2ULL << (e - s)) - 1) << s; 66 } 67 68 static inline gfn_t kvm_mmu_max_gfn(void) 69 { 70 /* 71 * Note that this uses the host MAXPHYADDR, not the guest's. 72 * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR; 73 * assuming KVM is running on bare metal, guest accesses beyond 74 * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit 75 * (either EPT Violation/Misconfig or #NPF), and so KVM will never 76 * install a SPTE for such addresses. If KVM is running as a VM 77 * itself, on the other hand, it might see a MAXPHYADDR that is less 78 * than hardware's real MAXPHYADDR. Using the host MAXPHYADDR 79 * disallows such SPTEs entirely and simplifies the TDP MMU. 80 */ 81 int max_gpa_bits = likely(tdp_enabled) ? kvm_host.maxphyaddr : 52; 82 83 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1; 84 } 85 86 static inline bool mmu_has_mbec(struct kvm_mmu *mmu) 87 { 88 return mmu->root_role.cr4_smep; 89 } 90 91 u8 kvm_mmu_get_max_tdp_level(void); 92 93 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask); 94 void kvm_mmu_set_mmio_spte_value(struct kvm *kvm, u64 mmio_value); 95 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask); 96 void kvm_mmu_set_ept_masks(bool has_ad_bits); 97 98 void kvm_init_mmu(struct kvm_vcpu *vcpu); 99 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr4, 100 u64 efer, gpa_t nested_cr3, u64 misc_ctl); 101 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, 102 int huge_page_level, bool accessed_dirty, 103 bool mbec, gpa_t new_eptp); 104 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu); 105 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, 106 u64 fault_address, char *insn, int insn_len); 107 void __kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu, 108 struct kvm_mmu *mmu); 109 110 int kvm_mmu_load(struct kvm_vcpu *vcpu); 111 void kvm_mmu_unload(struct kvm_vcpu *vcpu); 112 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu); 113 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); 114 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu); 115 void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new, 116 int bytes); 117 118 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu) 119 { 120 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) 121 kvm_mmu_free_obsolete_roots(vcpu); 122 123 /* 124 * Checking root.hpa is sufficient even when KVM has mirror root. 125 * We can have either: 126 * (1) mirror_root_hpa = INVALID_PAGE, root.hpa = INVALID_PAGE 127 * (2) mirror_root_hpa = root, root.hpa = INVALID_PAGE 128 * (3) mirror_root_hpa = root1, root.hpa = root2 129 * We don't ever have: 130 * mirror_root_hpa = INVALID_PAGE, root.hpa = root 131 */ 132 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) 133 return 0; 134 135 return kvm_mmu_load(vcpu); 136 } 137 138 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3) 139 { 140 BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0); 141 142 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE) 143 ? cr3 & X86_CR3_PCID_MASK 144 : 0; 145 } 146 147 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu) 148 { 149 return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu)); 150 } 151 152 static inline unsigned long kvm_get_active_cr3_lam_bits(struct kvm_vcpu *vcpu) 153 { 154 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_LAM)) 155 return 0; 156 157 return kvm_read_cr3(vcpu) & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57); 158 } 159 160 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) 161 { 162 u64 root_hpa = vcpu->arch.mmu->root.hpa; 163 164 if (!VALID_PAGE(root_hpa)) 165 return; 166 167 kvm_x86_call(load_mmu_pgd)(vcpu, root_hpa, 168 vcpu->arch.mmu->root_role.level); 169 } 170 171 static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu, 172 struct kvm_mmu *mmu) 173 { 174 /* 175 * When EPT is enabled, KVM may passthrough CR0.WP to the guest, i.e. 176 * @mmu's snapshot of CR0.WP and thus all related paging metadata may 177 * be stale. Refresh CR0.WP and the metadata on-demand when checking 178 * for permission faults. Exempt nested MMUs, i.e. MMUs for shadowing 179 * nEPT and nNPT, as CR0.WP is ignored in both cases. Note, KVM does 180 * need to refresh nested_mmu, a.k.a. the walker used to translate L2 181 * GVAs to GPAs, as that "MMU" needs to honor L2's CR0.WP. 182 */ 183 if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu) 184 return; 185 186 __kvm_mmu_refresh_passthrough_bits(vcpu, mmu); 187 } 188 189 /* 190 * Check if a given access (described through the I/D, W/R and U/S bits of a 191 * page fault error code pfec) causes a permission fault with the given PTE 192 * access rights (in ACC_* format). 193 * 194 * Return zero if the access does not fault; return the page fault error code 195 * if the access faults. 196 */ 197 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, 198 unsigned pte_access, unsigned pte_pkey, 199 u64 access) 200 { 201 /* strip nested paging fault error codes */ 202 unsigned int pfec = access; 203 unsigned long rflags = kvm_x86_call(get_rflags)(vcpu); 204 205 /* 206 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1. 207 * For implicit supervisor accesses, SMAP cannot be overridden. 208 * 209 * SMAP works on supervisor accesses only, and not_smap can 210 * be set or not set when user access with neither has any bearing 211 * on the result. 212 * 213 * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit; 214 * this bit will always be zero in pfec, but it will be one in index 215 * if SMAP checks are being disabled. 216 */ 217 u64 implicit_access = access & PFERR_IMPLICIT_ACCESS; 218 bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC; 219 int index = (pfec | (not_smap ? PFERR_RSVD_MASK : 0)) >> 1; 220 u32 errcode = PFERR_PRESENT_MASK; 221 bool fault; 222 223 kvm_mmu_refresh_passthrough_bits(vcpu, mmu); 224 225 fault = (mmu->permissions[index] >> pte_access) & 1; 226 227 WARN_ON_ONCE(pfec & (PFERR_PK_MASK | PFERR_SS_MASK | PFERR_RSVD_MASK)); 228 if (unlikely(mmu->pkru_mask)) { 229 u32 pkru_bits, offset; 230 231 /* 232 * PKRU defines 32 bits, there are 16 domains and 2 233 * attribute bits per domain in pkru. pte_pkey is the 234 * index of the protection domain, so pte_pkey * 2 is 235 * is the index of the first bit for the domain. 236 */ 237 pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3; 238 239 /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */ 240 offset = (pfec & ~1) | ((pte_access & PT_USER_MASK) ? PFERR_RSVD_MASK : 0); 241 242 pkru_bits &= mmu->pkru_mask >> offset; 243 errcode |= -pkru_bits & PFERR_PK_MASK; 244 fault |= (pkru_bits != 0); 245 } 246 247 return -(u32)fault & errcode; 248 } 249 250 int kvm_mmu_post_init_vm(struct kvm *kvm); 251 void kvm_mmu_pre_destroy_vm(struct kvm *kvm); 252 253 static inline bool kvm_shadow_root_allocated(struct kvm *kvm) 254 { 255 /* 256 * Read shadow_root_allocated before related pointers. Hence, threads 257 * reading shadow_root_allocated in any lock context are guaranteed to 258 * see the pointers. Pairs with smp_store_release in 259 * mmu_first_shadow_root_alloc. 260 */ 261 return smp_load_acquire(&kvm->arch.shadow_root_allocated); 262 } 263 264 #ifdef CONFIG_X86_64 265 extern bool tdp_mmu_enabled; 266 #else 267 #define tdp_mmu_enabled false 268 #endif 269 270 int kvm_tdp_mmu_map_private_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn); 271 272 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm) 273 { 274 return !tdp_mmu_enabled || kvm_shadow_root_allocated(kvm); 275 } 276 277 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) 278 { 279 /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */ 280 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - 281 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); 282 } 283 284 static inline unsigned long 285 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages, 286 int level) 287 { 288 return gfn_to_index(slot->base_gfn + npages - 1, 289 slot->base_gfn, level) + 1; 290 } 291 292 static inline unsigned long 293 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level) 294 { 295 return __kvm_mmu_slot_lpages(slot, slot->npages, level); 296 } 297 298 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count) 299 { 300 atomic64_add(count, &kvm->stat.pages[level - 1]); 301 } 302 303 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu, 304 struct kvm_mmu *mmu, 305 gpa_t gpa, u64 access, 306 struct x86_exception *exception, 307 u64 pte_access) 308 { 309 if (mmu != &vcpu->arch.nested_mmu) 310 return gpa; 311 return kvm_x86_ops.nested_ops->translate_nested_gpa(vcpu, gpa, access, 312 exception, 313 pte_access); 314 } 315 316 static inline bool kvm_has_mirrored_tdp(const struct kvm *kvm) 317 { 318 return kvm->arch.vm_type == KVM_X86_TDX_VM; 319 } 320 321 static inline gfn_t kvm_gfn_direct_bits(const struct kvm *kvm) 322 { 323 return kvm->arch.gfn_direct_bits; 324 } 325 326 static inline bool kvm_is_addr_direct(struct kvm *kvm, gpa_t gpa) 327 { 328 gpa_t gpa_direct_bits = gfn_to_gpa(kvm_gfn_direct_bits(kvm)); 329 330 return !gpa_direct_bits || (gpa & gpa_direct_bits); 331 } 332 333 static inline bool kvm_is_gfn_alias(struct kvm *kvm, gfn_t gfn) 334 { 335 return gfn & kvm_gfn_direct_bits(kvm); 336 } 337 #endif 338