1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip KSZ PTP register definitions 3 * Copyright (C) 2022 Microchip Technology Inc. 4 */ 5 6 #ifndef __KSZ_PTP_REGS_H 7 #define __KSZ_PTP_REGS_H 8 9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120 10 #define LED_OVR_2 BIT(1) 11 #define LED_OVR_1 BIT(0) 12 13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128 14 #define LED_SRC_PTP_GPIO_1 BIT(3) 15 #define LED_SRC_PTP_GPIO_2 BIT(2) 16 17 /* 5 - PTP Clock */ 18 /* REG_PTP_CLK_CTRL */ 19 #define PTP_STEP_ADJ BIT(6) 20 #define PTP_STEP_DIR BIT(5) 21 #define PTP_READ_TIME BIT(4) 22 #define PTP_LOAD_TIME BIT(3) 23 #define PTP_CLK_ADJ_ENABLE BIT(2) 24 #define PTP_CLK_ENABLE BIT(1) 25 #define PTP_CLK_RESET BIT(0) 26 27 /* REG_PTP_RTC_SUB_NANOSEC */ 28 #define PTP_RTC_SUB_NANOSEC_M 0x0007 29 #define PTP_RTC_0NS 0x00 30 31 /* REG_PTP_SUBNANOSEC_RATE */ 32 #define PTP_SUBNANOSEC_M 0x3FFFFFFF 33 #define PTP_RATE_DIR BIT(31) 34 #define PTP_TMP_RATE_ENABLE BIT(30) 35 36 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E 37 38 #define REG_PTP_RATE_DURATION 0x0510 39 #define REG_PTP_RATE_DURATION_H 0x0510 40 #define REG_PTP_RATE_DURATION_L 0x0512 41 42 /* REG_PTP_MSG_CONF1 */ 43 #define PTP_802_1AS BIT(7) 44 #define PTP_ENABLE BIT(6) 45 #define PTP_ETH_ENABLE BIT(5) 46 #define PTP_IPV4_UDP_ENABLE BIT(4) 47 #define PTP_IPV6_UDP_ENABLE BIT(3) 48 #define PTP_TC_P2P BIT(2) 49 #define PTP_MASTER BIT(1) 50 #define PTP_1STEP BIT(0) 51 52 #define REG_PTP_UNIT_INDEX__4 0x0520 53 54 #define KSZ8463_TOU_ACTIVE 0x202 55 #define KSZ8463_TOU_EN 0x206 56 #define KSZ8463_TOU_SW_RST 0x208 57 58 #define KSZ8463_TRIGN_CFG_SIZE 0x20 59 #define KSZ8463_TRIG1_CFG 0x220 60 #define KSZ8463_TARGET_NSEC 0x000 61 #define KSZ8463_TARGET_SEC 0x004 62 #define KSZ8463_PATTERN_OFF 0x008 63 #define KSZ8463_NOTIFY_BIT BIT(8) 64 #define KSZ8463_PATTERN_M GENMASK(6, 4) 65 #define KSZ8463_PULSE_WIDTH_OFF 0x00A 66 #define KSZ8463_TRIG_PULSE_WIDTH_M GENMASK(15, 0) 67 #define KSZ8463_CYCLE_WIDTH_OFF 0x00C 68 #define KSZ8463_CYCLE_CNT_OFF 0x010 69 70 #define PTP_GPIO_INDEX GENMASK(19, 16) 71 #define PTP_TSI_INDEX BIT(8) 72 #define PTP_TOU_INDEX GENMASK(1, 0) 73 74 #define REG_PTP_TRIG_STATUS__4 0x0524 75 76 #define TRIG_ERROR_M GENMASK(18, 16) 77 #define TRIG_DONE_M GENMASK(2, 0) 78 79 #define REG_PTP_INT_STATUS__4 0x0528 80 81 #define TRIG_INT_M GENMASK(18, 16) 82 #define TS_INT_M GENMASK(1, 0) 83 84 #define REG_PTP_CTRL_STAT__4 0x052C 85 86 #define GPIO_IN BIT(7) 87 #define GPIO_OUT BIT(6) 88 #define TS_INT_ENABLE BIT(5) 89 #define TRIG_ACTIVE BIT(4) 90 #define TRIG_ENABLE BIT(3) 91 #define TRIG_RESET BIT(2) 92 #define TS_ENABLE BIT(1) 93 #define TS_RESET BIT(0) 94 95 #define REG_TRIG_TARGET_NANOSEC 0x0530 96 #define REG_TRIG_TARGET_SEC 0x0534 97 98 #define REG_TRIG_CTRL__4 0x0538 99 100 #define TRIG_CASCADE_ENABLE BIT(31) 101 #define TRIG_CASCADE_TAIL BIT(30) 102 #define TRIG_CASCADE_UPS_M GENMASK(29, 26) 103 #define TRIG_NOW BIT(25) 104 #define TRIG_NOTIFY BIT(24) 105 #define TRIG_EDGE BIT(23) 106 #define TRIG_PATTERN_M GENMASK(22, 20) 107 #define TRIG_NEG_EDGE 0 108 #define TRIG_POS_EDGE 1 109 #define TRIG_NEG_PULSE 2 110 #define TRIG_POS_PULSE 3 111 #define TRIG_NEG_PERIOD 4 112 #define TRIG_POS_PERIOD 5 113 #define TRIG_REG_OUTPUT 6 114 #define TRIG_GPO_M GENMASK(19, 16) 115 #define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0) 116 117 #define REG_TRIG_CYCLE_WIDTH 0x053C 118 #define TRIG_CYCLE_WIDTH_M GENMASK(31, 0) 119 120 #define REG_TRIG_CYCLE_CNT 0x0540 121 122 #define TRIG_CYCLE_CNT_M GENMASK(31, 16) 123 #define TRIG_BIT_PATTERN_M GENMASK(15, 0) 124 125 #define REG_TRIG_ITERATE_TIME 0x0544 126 127 #define REG_TRIG_PULSE_WIDTH__4 0x0548 128 129 #define TRIG_PULSE_WIDTH_M GENMASK(23, 0) 130 131 /* Port PTP Register */ 132 #define REG_PTP_PORT_RX_DELAY__2 0x0C00 133 #define REG_PTP_PORT_TX_DELAY__2 0x0C02 134 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 135 136 #define REG_PTP_PORT_XDELAY_TS 0x0C08 137 #define REG_PTP_PORT_SYNC_TS 0x0C0C 138 #define REG_PTP_PORT_PDRESP_TS 0x0C10 139 140 #define KSZ8463_REG_PORT_DREQ_TS 0x0648 141 #define KSZ8463_REG_PORT_SYNC_TS 0x064C 142 #define KSZ8463_REG_PORT_DRESP_TS 0x0650 143 #define KSZ8463_PTP_TS_ISR 0x068C 144 #define KSZ8463_PTP_TS_IER 0x068E 145 146 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 147 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 148 149 #define PTP_PORT_SYNC_INT BIT(15) 150 #define PTP_PORT_XDELAY_REQ_INT BIT(14) 151 #define PTP_PORT_PDELAY_RESP_INT BIT(13) 152 #define KSZ_SYNC_MSG 2 153 #define KSZ_XDREQ_MSG 1 154 #define KSZ_PDRES_MSG 0 155 156 #define KSZ8463_DRESP_TS_OFFSET (KSZ8463_REG_PORT_DRESP_TS - KSZ8463_REG_PORT_DREQ_TS) 157 #define KSZ8463_SYNC_MSG 0 158 #define KSZ8463_XDREQ_PDRES_MSG 1 159 160 #endif 161