1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip KSZ PTP register definitions 3 * Copyright (C) 2022 Microchip Technology Inc. 4 */ 5 6 #ifndef __KSZ_PTP_REGS_H 7 #define __KSZ_PTP_REGS_H 8 9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120 10 #define LED_OVR_2 BIT(1) 11 #define LED_OVR_1 BIT(0) 12 13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128 14 #define LED_SRC_PTP_GPIO_1 BIT(3) 15 #define LED_SRC_PTP_GPIO_2 BIT(2) 16 17 /* 5 - PTP Clock */ 18 /* REG_PTP_CLK_CTRL */ 19 #define PTP_STEP_ADJ BIT(6) 20 #define PTP_STEP_DIR BIT(5) 21 #define PTP_READ_TIME BIT(4) 22 #define PTP_LOAD_TIME BIT(3) 23 #define PTP_CLK_ADJ_ENABLE BIT(2) 24 #define PTP_CLK_ENABLE BIT(1) 25 #define PTP_CLK_RESET BIT(0) 26 27 /* REG_PTP_RTC_SUB_NANOSEC */ 28 #define PTP_RTC_SUB_NANOSEC_M 0x0007 29 #define PTP_RTC_0NS 0x00 30 31 /* REG_PTP_SUBNANOSEC_RATE */ 32 #define PTP_SUBNANOSEC_M 0x3FFFFFFF 33 #define PTP_RATE_DIR BIT(31) 34 #define PTP_TMP_RATE_ENABLE BIT(30) 35 36 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E 37 38 #define REG_PTP_RATE_DURATION 0x0510 39 #define REG_PTP_RATE_DURATION_H 0x0510 40 #define REG_PTP_RATE_DURATION_L 0x0512 41 42 /* REG_PTP_MSG_CONF1 */ 43 #define PTP_802_1AS BIT(7) 44 #define PTP_ENABLE BIT(6) 45 #define PTP_ETH_ENABLE BIT(5) 46 #define PTP_IPV4_UDP_ENABLE BIT(4) 47 #define PTP_IPV6_UDP_ENABLE BIT(3) 48 #define PTP_TC_P2P BIT(2) 49 #define PTP_MASTER BIT(1) 50 #define PTP_1STEP BIT(0) 51 52 #define REG_PTP_UNIT_INDEX__4 0x0520 53 54 #define PTP_GPIO_INDEX GENMASK(19, 16) 55 #define PTP_TSI_INDEX BIT(8) 56 #define PTP_TOU_INDEX GENMASK(1, 0) 57 58 #define REG_PTP_TRIG_STATUS__4 0x0524 59 60 #define TRIG_ERROR_M GENMASK(18, 16) 61 #define TRIG_DONE_M GENMASK(2, 0) 62 63 #define REG_PTP_INT_STATUS__4 0x0528 64 65 #define TRIG_INT_M GENMASK(18, 16) 66 #define TS_INT_M GENMASK(1, 0) 67 68 #define REG_PTP_CTRL_STAT__4 0x052C 69 70 #define GPIO_IN BIT(7) 71 #define GPIO_OUT BIT(6) 72 #define TS_INT_ENABLE BIT(5) 73 #define TRIG_ACTIVE BIT(4) 74 #define TRIG_ENABLE BIT(3) 75 #define TRIG_RESET BIT(2) 76 #define TS_ENABLE BIT(1) 77 #define TS_RESET BIT(0) 78 79 #define REG_TRIG_TARGET_NANOSEC 0x0530 80 #define REG_TRIG_TARGET_SEC 0x0534 81 82 #define REG_TRIG_CTRL__4 0x0538 83 84 #define TRIG_CASCADE_ENABLE BIT(31) 85 #define TRIG_CASCADE_TAIL BIT(30) 86 #define TRIG_CASCADE_UPS_M GENMASK(29, 26) 87 #define TRIG_NOW BIT(25) 88 #define TRIG_NOTIFY BIT(24) 89 #define TRIG_EDGE BIT(23) 90 #define TRIG_PATTERN_M GENMASK(22, 20) 91 #define TRIG_NEG_EDGE 0 92 #define TRIG_POS_EDGE 1 93 #define TRIG_NEG_PULSE 2 94 #define TRIG_POS_PULSE 3 95 #define TRIG_NEG_PERIOD 4 96 #define TRIG_POS_PERIOD 5 97 #define TRIG_REG_OUTPUT 6 98 #define TRIG_GPO_M GENMASK(19, 16) 99 #define TRIG_CASCADE_ITERATE_CNT_M GENMASK(15, 0) 100 101 #define REG_TRIG_CYCLE_WIDTH 0x053C 102 #define TRIG_CYCLE_WIDTH_M GENMASK(31, 0) 103 104 #define REG_TRIG_CYCLE_CNT 0x0540 105 106 #define TRIG_CYCLE_CNT_M GENMASK(31, 16) 107 #define TRIG_BIT_PATTERN_M GENMASK(15, 0) 108 109 #define REG_TRIG_ITERATE_TIME 0x0544 110 111 #define REG_TRIG_PULSE_WIDTH__4 0x0548 112 113 #define TRIG_PULSE_WIDTH_M GENMASK(23, 0) 114 115 /* Port PTP Register */ 116 #define REG_PTP_PORT_RX_DELAY__2 0x0C00 117 #define REG_PTP_PORT_TX_DELAY__2 0x0C02 118 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04 119 120 #define REG_PTP_PORT_XDELAY_TS 0x0C08 121 #define REG_PTP_PORT_SYNC_TS 0x0C0C 122 #define REG_PTP_PORT_PDRESP_TS 0x0C10 123 124 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14 125 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16 126 127 #define PTP_PORT_SYNC_INT BIT(15) 128 #define PTP_PORT_XDELAY_REQ_INT BIT(14) 129 #define PTP_PORT_PDELAY_RESP_INT BIT(13) 130 #define KSZ_SYNC_MSG 2 131 #define KSZ_XDREQ_MSG 1 132 #define KSZ_PDRES_MSG 0 133 134 #endif 135