xref: /linux/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h (revision 994aeacbb3c039b4f3e02e76e6d39407920e76c6)
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Huang Rui
23  *
24  */
25 #ifndef __AMDGPU_PSP_H__
26 #define __AMDGPU_PSP_H__
27 
28 #include "amdgpu.h"
29 #include "psp_gfx_if.h"
30 #include "ta_xgmi_if.h"
31 #include "ta_ras_if.h"
32 #include "ta_rap_if.h"
33 #include "ta_secureDisplay_if.h"
34 
35 #define PSP_FENCE_BUFFER_SIZE	0x1000
36 #define PSP_CMD_BUFFER_SIZE	0x1000
37 #define PSP_1_MEG		0x100000
38 #define PSP_TMR_SIZE(adev)	((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39 #define PSP_TMR_ALIGNMENT	0x100000
40 #define PSP_FW_NAME_LEN		0x24
41 
42 extern const struct attribute_group amdgpu_flash_attr_group;
43 
44 enum psp_shared_mem_size {
45 	PSP_ASD_SHARED_MEM_SIZE				= 0x0,
46 	PSP_XGMI_SHARED_MEM_SIZE			= 0x4000,
47 	PSP_RAS_SHARED_MEM_SIZE				= 0x4000,
48 	PSP_HDCP_SHARED_MEM_SIZE			= 0x4000,
49 	PSP_DTM_SHARED_MEM_SIZE				= 0x4000,
50 	PSP_RAP_SHARED_MEM_SIZE				= 0x4000,
51 	PSP_SECUREDISPLAY_SHARED_MEM_SIZE	= 0x4000,
52 };
53 
54 enum ta_type_id {
55 	TA_TYPE_XGMI = 1,
56 	TA_TYPE_RAS,
57 	TA_TYPE_HDCP,
58 	TA_TYPE_DTM,
59 	TA_TYPE_RAP,
60 	TA_TYPE_SECUREDISPLAY,
61 
62 	TA_TYPE_MAX_INDEX,
63 };
64 
65 struct psp_context;
66 struct psp_xgmi_node_info;
67 struct psp_xgmi_topology_info;
68 struct psp_bin_desc;
69 
70 enum psp_bootloader_cmd {
71 	PSP_BL__LOAD_SYSDRV		= 0x10000,
72 	PSP_BL__LOAD_SOSDRV		= 0x20000,
73 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
74 	PSP_BL__LOAD_SOCDRV             = 0xB0000,
75 	PSP_BL__LOAD_DBGDRV             = 0xC0000,
76 	PSP_BL__LOAD_HADDRV		= PSP_BL__LOAD_DBGDRV,
77 	PSP_BL__LOAD_INTFDRV		= 0xD0000,
78 	PSP_BL__LOAD_RASDRV		= 0xE0000,
79 	PSP_BL__LOAD_IPKEYMGRDRV	= 0xF0000,
80 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
81 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
82 	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,
83 };
84 
85 enum psp_ring_type {
86 	PSP_RING_TYPE__INVALID = 0,
87 	/*
88 	 * These values map to the way the PSP kernel identifies the
89 	 * rings.
90 	 */
91 	PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
92 	PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
93 };
94 
95 struct psp_ring {
96 	enum psp_ring_type		ring_type;
97 	struct psp_gfx_rb_frame		*ring_mem;
98 	uint64_t			ring_mem_mc_addr;
99 	void				*ring_mem_handle;
100 	uint32_t			ring_size;
101 	uint32_t			ring_wptr;
102 };
103 
104 /* More registers may will be supported */
105 enum psp_reg_prog_id {
106 	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
107 	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
108 	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
109 	PSP_REG_LAST
110 };
111 
112 struct psp_funcs {
113 	int (*init_microcode)(struct psp_context *psp);
114 	int (*wait_for_bootloader)(struct psp_context *psp);
115 	int (*bootloader_load_kdb)(struct psp_context *psp);
116 	int (*bootloader_load_spl)(struct psp_context *psp);
117 	int (*bootloader_load_sysdrv)(struct psp_context *psp);
118 	int (*bootloader_load_soc_drv)(struct psp_context *psp);
119 	int (*bootloader_load_intf_drv)(struct psp_context *psp);
120 	int (*bootloader_load_dbg_drv)(struct psp_context *psp);
121 	int (*bootloader_load_ras_drv)(struct psp_context *psp);
122 	int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp);
123 	int (*bootloader_load_sos)(struct psp_context *psp);
124 	int (*ring_create)(struct psp_context *psp,
125 			   enum psp_ring_type ring_type);
126 	int (*ring_stop)(struct psp_context *psp,
127 			    enum psp_ring_type ring_type);
128 	int (*ring_destroy)(struct psp_context *psp,
129 			    enum psp_ring_type ring_type);
130 	bool (*smu_reload_quirk)(struct psp_context *psp);
131 	int (*mode1_reset)(struct psp_context *psp);
132 	int (*mem_training)(struct psp_context *psp, uint32_t ops);
133 	uint32_t (*ring_get_wptr)(struct psp_context *psp);
134 	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
135 	int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
136 	int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
137 	int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
138 	int (*vbflash_stat)(struct psp_context *psp);
139 	int (*fatal_error_recovery_quirk)(struct psp_context *psp);
140 	bool (*get_ras_capability)(struct psp_context *psp);
141 	bool (*is_aux_sos_load_required)(struct psp_context *psp);
142 };
143 
144 struct ta_funcs {
145 	int (*fn_ta_initialize)(struct psp_context *psp);
146 	int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
147 	int (*fn_ta_terminate)(struct psp_context *psp);
148 };
149 
150 #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
151 struct psp_xgmi_node_info {
152 	uint64_t				node_id;
153 	uint8_t					num_hops;
154 	uint8_t					is_sharing_enabled;
155 	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
156 	uint8_t					num_links;
157 	struct xgmi_connected_port_num		port_num[TA_XGMI__MAX_PORT_NUM];
158 };
159 
160 struct psp_xgmi_topology_info {
161 	uint32_t			num_nodes;
162 	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
163 };
164 
165 struct psp_bin_desc {
166 	uint32_t fw_version;
167 	uint32_t feature_version;
168 	uint32_t size_bytes;
169 	uint8_t *start_addr;
170 };
171 
172 struct ta_mem_context {
173 	struct amdgpu_bo		*shared_bo;
174 	uint64_t		shared_mc_addr;
175 	void			*shared_buf;
176 	enum psp_shared_mem_size	shared_mem_size;
177 };
178 
179 struct ta_context {
180 	bool			initialized;
181 	uint32_t		session_id;
182 	uint32_t		resp_status;
183 	struct ta_mem_context	mem_context;
184 	struct psp_bin_desc		bin_desc;
185 	enum psp_gfx_cmd_id		ta_load_type;
186 	enum ta_type_id		ta_type;
187 };
188 
189 struct ta_cp_context {
190 	struct ta_context		context;
191 	struct mutex			mutex;
192 };
193 
194 struct psp_xgmi_context {
195 	struct ta_context		context;
196 	struct psp_xgmi_topology_info	top_info;
197 	bool				supports_extended_data;
198 	uint8_t				xgmi_ta_caps;
199 };
200 
201 struct psp_ras_context {
202 	struct ta_context		context;
203 	struct amdgpu_ras		*ras;
204 	struct mutex			mutex;
205 };
206 
207 #define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
208 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
209 #define GDDR6_MEM_TRAINING_OFFSET		0x8000
210 /*Define the VRAM size that will be encroached by BIST training.*/
211 #define BIST_MEM_TRAINING_ENCROACHED_SIZE	0x2000000
212 
213 enum psp_memory_training_init_flag {
214 	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
215 	PSP_MEM_TRAIN_SUPPORT		= 0x1,
216 	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
217 	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
218 	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
219 };
220 
221 enum psp_memory_training_ops {
222 	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
223 	PSP_MEM_TRAIN_SAVE		= 0x2,
224 	PSP_MEM_TRAIN_RESTORE		= 0x4,
225 	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
226 	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
227 	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
228 };
229 
230 struct psp_memory_training_context {
231 	/*training data size*/
232 	u64 train_data_size;
233 	/*
234 	 * sys_cache
235 	 * cpu virtual address
236 	 * system memory buffer that used to store the training data.
237 	 */
238 	void *sys_cache;
239 
240 	/*vram offset of the p2c training data*/
241 	u64 p2c_train_data_offset;
242 
243 	/*vram offset of the c2p training data*/
244 	u64 c2p_train_data_offset;
245 	struct amdgpu_bo *c2p_bo;
246 
247 	enum psp_memory_training_init_flag init;
248 	u32 training_cnt;
249 	bool enable_mem_training;
250 };
251 
252 /** PSP runtime DB **/
253 #define PSP_RUNTIME_DB_SIZE_IN_BYTES		0x10000
254 #define PSP_RUNTIME_DB_OFFSET			0x100000
255 #define PSP_RUNTIME_DB_COOKIE_ID		0x0ed5
256 #define PSP_RUNTIME_DB_VER_1			0x0100
257 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT	0x40
258 
259 enum psp_runtime_entry_type {
260 	PSP_RUNTIME_ENTRY_TYPE_INVALID		= 0x0,
261 	PSP_RUNTIME_ENTRY_TYPE_TEST		= 0x1,
262 	PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON	= 0x2,  /* Common mGPU runtime data */
263 	PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL	= 0x3,  /* WAFL runtime data */
264 	PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI	= 0x4,  /* XGMI runtime data */
265 	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG	= 0x5,  /* Boot Config runtime data */
266 	PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
267 };
268 
269 /* PSP runtime DB header */
270 struct psp_runtime_data_header {
271 	/* determine the existence of runtime db */
272 	uint16_t cookie;
273 	/* version of runtime db */
274 	uint16_t version;
275 };
276 
277 /* PSP runtime DB entry */
278 struct psp_runtime_entry {
279 	/* type of runtime db entry */
280 	uint32_t entry_type;
281 	/* offset of entry in bytes */
282 	uint16_t offset;
283 	/* size of entry in bytes */
284 	uint16_t size;
285 };
286 
287 /* PSP runtime DB directory */
288 struct psp_runtime_data_directory {
289 	/* number of valid entries */
290 	uint16_t			entry_count;
291 	/* db entries*/
292 	struct psp_runtime_entry	entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
293 };
294 
295 /* PSP runtime DB boot config feature bitmask */
296 enum psp_runtime_boot_cfg_feature {
297 	BOOT_CFG_FEATURE_GECC                       = 0x1,
298 	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING    = 0x2,
299 };
300 
301 /* PSP run time DB SCPM authentication defines */
302 enum psp_runtime_scpm_authentication {
303 	SCPM_DISABLE                     = 0x0,
304 	SCPM_ENABLE                      = 0x1,
305 	SCPM_ENABLE_WITH_SCPM_ERR        = 0x2,
306 };
307 
308 /* PSP runtime DB boot config entry */
309 struct psp_runtime_boot_cfg_entry {
310 	uint32_t boot_cfg_bitmask;
311 	uint32_t reserved;
312 };
313 
314 /* PSP runtime DB SCPM entry */
315 struct psp_runtime_scpm_entry {
316 	enum psp_runtime_scpm_authentication scpm_status;
317 };
318 
319 struct psp_context {
320 	struct amdgpu_device		*adev;
321 	struct psp_ring			km_ring;
322 	struct psp_gfx_cmd_resp		*cmd;
323 
324 	const struct psp_funcs		*funcs;
325 	const struct ta_funcs		*ta_funcs;
326 
327 	/* firmware buffer */
328 	struct amdgpu_bo		*fw_pri_bo;
329 	uint64_t			fw_pri_mc_addr;
330 	void				*fw_pri_buf;
331 
332 	/* sos firmware */
333 	const struct firmware		*sos_fw;
334 	struct psp_bin_desc		sys;
335 	struct psp_bin_desc		sos;
336 	struct psp_bin_desc		toc;
337 	struct psp_bin_desc		kdb;
338 	struct psp_bin_desc		spl;
339 	struct psp_bin_desc		rl;
340 	struct psp_bin_desc		soc_drv;
341 	struct psp_bin_desc		intf_drv;
342 	struct psp_bin_desc		dbg_drv;
343 	struct psp_bin_desc		ras_drv;
344 	struct psp_bin_desc		ipkeymgr_drv;
345 
346 	/* tmr buffer */
347 	struct amdgpu_bo		*tmr_bo;
348 	uint64_t			tmr_mc_addr;
349 
350 	/* asd firmware */
351 	const struct firmware		*asd_fw;
352 
353 	/* toc firmware */
354 	const struct firmware		*toc_fw;
355 
356 	/* cap firmware */
357 	const struct firmware		*cap_fw;
358 
359 	/* fence buffer */
360 	struct amdgpu_bo		*fence_buf_bo;
361 	uint64_t			fence_buf_mc_addr;
362 	void				*fence_buf;
363 
364 	/* cmd buffer */
365 	struct amdgpu_bo		*cmd_buf_bo;
366 	uint64_t			cmd_buf_mc_addr;
367 	struct psp_gfx_cmd_resp		*cmd_buf_mem;
368 
369 	/* fence value associated with cmd buffer */
370 	atomic_t			fence_value;
371 	/* flag to mark whether gfx fw autoload is supported or not */
372 	bool				autoload_supported;
373 	/* flag to mark whether psp use runtime TMR or boottime TMR */
374 	bool				boot_time_tmr;
375 	/* flag to mark whether df cstate management centralized to PMFW */
376 	bool				pmfw_centralized_cstate_management;
377 
378 	/* xgmi ta firmware and buffer */
379 	const struct firmware		*ta_fw;
380 	uint32_t			ta_fw_version;
381 
382 	uint32_t			cap_fw_version;
383 	uint32_t			cap_feature_version;
384 	uint32_t			cap_ucode_size;
385 
386 	struct ta_context		asd_context;
387 	struct psp_xgmi_context		xgmi_context;
388 	struct psp_ras_context		ras_context;
389 	struct ta_cp_context		hdcp_context;
390 	struct ta_cp_context		dtm_context;
391 	struct ta_cp_context		rap_context;
392 	struct ta_cp_context		securedisplay_context;
393 	struct mutex			mutex;
394 	struct psp_memory_training_context mem_train_ctx;
395 
396 	uint32_t			boot_cfg_bitmask;
397 
398 	/* firmware upgrades supported */
399 	bool				sup_pd_fw_up;
400 	bool				sup_ifwi_up;
401 
402 	char				*vbflash_tmp_buf;
403 	size_t				vbflash_image_size;
404 	bool				vbflash_done;
405 };
406 
407 struct amdgpu_psp_funcs {
408 	bool (*check_fw_loading_status)(struct amdgpu_device *adev,
409 					enum AMDGPU_UCODE_ID);
410 };
411 
412 
413 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
414 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
415 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
416 #define psp_init_microcode(psp) \
417 		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
418 #define psp_bootloader_load_kdb(psp) \
419 		((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
420 #define psp_bootloader_load_spl(psp) \
421 		((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
422 #define psp_bootloader_load_sysdrv(psp) \
423 		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
424 #define psp_bootloader_load_soc_drv(psp) \
425 		((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
426 #define psp_bootloader_load_intf_drv(psp) \
427 		((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
428 #define psp_bootloader_load_dbg_drv(psp) \
429 		((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
430 #define psp_bootloader_load_ras_drv(psp) \
431 		((psp)->funcs->bootloader_load_ras_drv ? \
432 		(psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
433 #define psp_bootloader_load_ipkeymgr_drv(psp) \
434 		((psp)->funcs->bootloader_load_ipkeymgr_drv ? \
435 		 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0)
436 #define psp_bootloader_load_sos(psp) \
437 		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
438 #define psp_smu_reload_quirk(psp) \
439 		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
440 #define psp_mode1_reset(psp) \
441 		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
442 #define psp_mem_training(psp, ops) \
443 	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
444 
445 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
446 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
447 
448 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
449 	((psp)->funcs->load_usbc_pd_fw ? \
450 	(psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
451 
452 #define psp_read_usbc_pd_fw(psp, fw_ver) \
453 	((psp)->funcs->read_usbc_pd_fw ? \
454 	(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
455 
456 #define psp_update_spirom(psp, fw_pri_mc_addr) \
457 	((psp)->funcs->update_spirom ? \
458 	(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
459 
460 #define psp_vbflash_status(psp) \
461 	((psp)->funcs->vbflash_stat ? \
462 	(psp)->funcs->vbflash_stat((psp)) : -EINVAL)
463 
464 #define psp_fatal_error_recovery_quirk(psp) \
465 	((psp)->funcs->fatal_error_recovery_quirk ? \
466 	(psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
467 
468 #define psp_is_aux_sos_load_required(psp) \
469 	((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0)
470 
471 extern const struct amd_ip_funcs psp_ip_funcs;
472 
473 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
474 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
475 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
476 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
477 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
478 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
479 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
480 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
481 
482 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
483 			uint32_t field_val, uint32_t mask, bool check_changed);
484 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
485 			uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
486 
487 int psp_execute_ip_fw_load(struct psp_context *psp,
488 			   struct amdgpu_firmware_info *ucode);
489 
490 int psp_gpu_reset(struct amdgpu_device *adev);
491 
492 int psp_ta_init_shared_buf(struct psp_context *psp,
493 				  struct ta_mem_context *mem_ctx);
494 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
495 int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
496 int psp_ta_load(struct psp_context *psp, struct ta_context *context);
497 int psp_ta_invoke(struct psp_context *psp,
498 			uint32_t ta_cmd_id,
499 			struct ta_context *context);
500 
501 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
502 int psp_xgmi_terminate(struct psp_context *psp);
503 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
504 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
505 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
506 int psp_xgmi_get_topology_info(struct psp_context *psp,
507 			       int number_devices,
508 			       struct psp_xgmi_topology_info *topology,
509 			       bool get_extended_data);
510 int psp_xgmi_set_topology_info(struct psp_context *psp,
511 			       int number_devices,
512 			       struct psp_xgmi_topology_info *topology);
513 int psp_ras_initialize(struct psp_context *psp);
514 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
515 int psp_ras_enable_features(struct psp_context *psp,
516 		union ta_ras_cmd_input *info, bool enable);
517 int psp_ras_trigger_error(struct psp_context *psp,
518 			  struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
519 int psp_ras_terminate(struct psp_context *psp);
520 int psp_ras_query_address(struct psp_context *psp,
521 			  struct ta_ras_query_address_input *addr_in,
522 			  struct ta_ras_query_address_output *addr_out);
523 
524 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
525 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
526 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
527 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
528 
529 int psp_rlc_autoload_start(struct psp_context *psp);
530 
531 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
532 		uint32_t value);
533 int psp_ring_cmd_submit(struct psp_context *psp,
534 			uint64_t cmd_buf_mc_addr,
535 			uint64_t fence_mc_addr,
536 			int index);
537 int psp_init_asd_microcode(struct psp_context *psp,
538 			   const char *chip_name);
539 int psp_init_toc_microcode(struct psp_context *psp,
540 			   const char *chip_name);
541 int psp_init_sos_microcode(struct psp_context *psp,
542 			   const char *chip_name);
543 int psp_init_ta_microcode(struct psp_context *psp,
544 			  const char *chip_name);
545 int psp_init_cap_microcode(struct psp_context *psp,
546 			  const char *chip_name);
547 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
548 					uint64_t *output_ptr);
549 
550 int psp_load_fw_list(struct psp_context *psp,
551 		     struct amdgpu_firmware_info **ucode_list, int ucode_count);
552 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
553 
554 int psp_spatial_partition(struct psp_context *psp, int mode);
555 
556 int is_psp_fw_valid(struct psp_bin_desc bin);
557 
558 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
559 bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
560 #endif
561