xref: /linux/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
14 #define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_
15 
16 /*
17  *****************************************
18  *   PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF)
19  *****************************************
20  */
21 
22 /* PSOC_GLOBAL_CONF_NON_RST_FLOPS */
23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT                     0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK                      0xFFFFFFFF
25 
26 /* PSOC_GLOBAL_CONF_PCI_FW_FSM */
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT                         0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK                          0x1
29 
30 /* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT                 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK                  0x1
33 
34 /* PSOC_GLOBAL_CONF_BTM_FSM */
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT                         0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK                          0xF
37 
38 /* PSOC_GLOBAL_CONF_SW_BTM_FSM */
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT                       0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK                        0xF
41 
42 /* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */
43 #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT                  0
44 #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK                   0xF
45 
46 /* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */
47 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT                  0
48 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK                   0xFFFFFFFF
49 
50 /* PSOC_GLOBAL_CONF_SPI_MEM_EN */
51 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT                        0
52 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK                         0x1
53 
54 /* PSOC_GLOBAL_CONF_PRSTN */
55 #define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT                             0
56 #define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK                              0x1
57 
58 /* PSOC_GLOBAL_CONF_PCIE_EN */
59 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT                          0
60 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK                           0x1
61 
62 /* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */
63 #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT                   0
64 #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK                    0x1
65 
66 /* PSOC_GLOBAL_CONF_SPI_IMG_STS */
67 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT                       0
68 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK                        0x1
69 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT                       1
70 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK                        0x2
71 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT                     2
72 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK                      0x4
73 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT                       3
74 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK                        0x8
75 
76 /* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */
77 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT                     0
78 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK                      0x1
79 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT                1
80 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK                 0x2
81 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT                  2
82 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK                   0x4
83 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT                  3
84 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK                   0x8
85 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT                4
86 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK                 0x10
87 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT                 5
88 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK                  0x20
89 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT                      6
90 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK                       0x40
91 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT               7
92 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK                0x80
93 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT                 8
94 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK                  0x100
95 
96 /* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */
97 #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT                  0
98 #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK                   0x1
99 
100 /* PSOC_GLOBAL_CONF_PHY_STABLE */
101 #define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT                      0
102 #define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK                       0x1
103 
104 /* PSOC_GLOBAL_CONF_PRSTN_OVR */
105 #define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT                          0
106 #define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK                           0x1
107 #define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT                         4
108 #define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK                          0x10
109 
110 /* PSOC_GLOBAL_CONF_ETR_FLUSH */
111 #define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT                        0
112 #define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK                         0x1
113 
114 /* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */
115 #define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT                    0
116 #define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK                     0xFFFFFFFF
117 
118 /* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */
119 #define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT                     0
120 #define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK                      0x1
121 
122 /* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */
123 #define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT                    0
124 #define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK                     0x1
125 
126 /* PSOC_GLOBAL_CONF_RAZWI */
127 #define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT                            0
128 #define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK                             0x1
129 #define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT                            4
130 #define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK                             0x10
131 
132 /* PSOC_GLOBAL_CONF_PROT */
133 #define PSOC_GLOBAL_CONF_PROT_AR_SHIFT                               0
134 #define PSOC_GLOBAL_CONF_PROT_AR_MASK                                0x7
135 #define PSOC_GLOBAL_CONF_PROT_AW_SHIFT                               4
136 #define PSOC_GLOBAL_CONF_PROT_AW_MASK                                0x70
137 
138 /* PSOC_GLOBAL_CONF_ADC */
139 #define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT                              0
140 #define PSOC_GLOBAL_CONF_ADC_INTR_MASK                               0x1
141 #define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT                              4
142 #define PSOC_GLOBAL_CONF_ADC_MASK_MASK                               0x10
143 
144 /* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */
145 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT                      0
146 #define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK                       0x1
147 
148 /* PSOC_GLOBAL_CONF_SCRATCHPAD */
149 #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT                        0
150 #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK                         0xFFFFFFFF
151 
152 /* PSOC_GLOBAL_CONF_SEMAPHORE */
153 #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT                         0
154 #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK                          0xFFFFFFFF
155 
156 /* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */
157 #define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT                  0
158 #define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK                   0xFFFFFFFF
159 
160 /* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */
161 #define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT                    0
162 #define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK                     0xFFFFFFFF
163 
164 /* PSOC_GLOBAL_CONF_SPL_SOURCE */
165 #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT                        0
166 #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK                         0x7
167 
168 /* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */
169 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT                   0
170 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK                    0x1
171 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT                   1
172 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK                    0x2
173 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT                    2
174 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK                     0x4
175 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT                    3
176 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK                     0x8
177 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT                      4
178 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK                       0x10
179 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT                      5
180 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK                       0x20
181 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT                      6
182 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK                       0x40
183 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT              7
184 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK               0x80
185 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT               8
186 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK                0x100
187 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT              9
188 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK               0x200
189 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT              10
190 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK               0x7C00
191 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT              15
192 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK               0x78000
193 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT                   19
194 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK                    0x80000
195 
196 /* PSOC_GLOBAL_CONF_I2C_SLV */
197 #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT                      0
198 #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK                       0x1
199 
200 /* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */
201 #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT             0
202 #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK              0x1
203 
204 /* PSOC_GLOBAL_CONF_TRACE_ADDR */
205 #define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT                        0
206 #define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK                         0x3FF
207 
208 /* PSOC_GLOBAL_CONF_ARUSER */
209 #define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT                            0
210 #define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK                             0xFFFFFFFF
211 
212 /* PSOC_GLOBAL_CONF_AWUSER */
213 #define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT                            0
214 #define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK                             0xFFFFFFFF
215 
216 /* PSOC_GLOBAL_CONF_TRACE_AWUSER */
217 #define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT                      0
218 #define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK                       0xFFFFFFFF
219 
220 /* PSOC_GLOBAL_CONF_TRACE_ARUSER */
221 #define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT                      0
222 #define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK                       0xFFFFFFFF
223 
224 /* PSOC_GLOBAL_CONF_BTL_STS */
225 #define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT                          0
226 #define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK                           0x1
227 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT                          4
228 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK                           0x10
229 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT                     8
230 #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK                      0xF00
231 
232 /* PSOC_GLOBAL_CONF_TIMEOUT_INTR */
233 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT                   0
234 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK                    0x1
235 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT                   1
236 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK                    0x2
237 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT                   2
238 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK                    0x4
239 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT                   3
240 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK                    0x8
241 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT                   4
242 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK                    0x10
243 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT                    5
244 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK                     0x20
245 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT                   6
246 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK                    0x40
247 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT                   7
248 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK                    0x80
249 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT                   8
250 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK                    0x100
251 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT                   9
252 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK                    0x200
253 
254 /* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */
255 #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT                 0
256 #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK                  0x1
257 
258 /* PSOC_GLOBAL_CONF_PERIPH_INTR */
259 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT                 0
260 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK                  0x1
261 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT                 1
262 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK                  0x2
263 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT              2
264 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK               0x4
265 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT              3
266 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK               0x8
267 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT                 4
268 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK                  0x10
269 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT                 5
270 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK                  0x20
271 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT              6
272 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK               0x40
273 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT              7
274 #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK               0x80
275 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT                      12
276 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK                       0x1000
277 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT               13
278 #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK                0x2000
279 #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT                       16
280 #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK                        0x10000
281 
282 /* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */
283 #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT                  0
284 #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK                   0x1
285 
286 /* PSOC_GLOBAL_CONF_AXI_ERR_INTR */
287 #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT                      0
288 #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK                       0x1
289 
290 /* PSOC_GLOBAL_CONF_TARGETID */
291 #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT                    1
292 #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK                     0xFFE
293 #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT                      16
294 #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK                       0xFFF0000
295 #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT                    28
296 #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK                     0xF0000000
297 
298 /* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */
299 #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT               0
300 #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK                0x1
301 
302 /* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */
303 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT          0
304 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK           0x1
305 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT               1
306 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK                0x2
307 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT            2
308 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK             0xC
309 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT                  4
310 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK                   0x10
311 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT                  5
312 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK                   0x20
313 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT                6
314 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK                 0x40
315 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT            7
316 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK             0x80
317 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT              8
318 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK               0x1FFF00
319 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT              22
320 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK               0x400000
321 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT              23
322 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK               0x800000
323 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT                   24
324 #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK                    0x1F000000
325 
326 /* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */
327 #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT                     0
328 #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK                      0x1
329 #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT                    8
330 #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK                     0xFF00
331 
332 /* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */
333 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT                   0
334 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK                    0x1
335 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT                   1
336 #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK                    0x2
337 
338 /* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */
339 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT                    0
340 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK                     0x1
341 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT                   4
342 #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK                    0x10
343 
344 /* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */
345 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT                     0
346 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK                      0x1
347 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT                     1
348 #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK                      0x2
349 
350 /* PSOC_GLOBAL_CONF_MASK_REQ */
351 #define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT                          0
352 #define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK                           0x1
353 
354 /* PSOC_GLOBAL_CONF_WD_RST_CFG_L */
355 #define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT                      0
356 #define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK                       0xFFFFFFFF
357 
358 /* PSOC_GLOBAL_CONF_WD_RST_CFG_H */
359 #define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT                      0
360 #define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK                       0x3FFFFF
361 
362 /* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */
363 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT                     0
364 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK                      0xFFFFFFFF
365 
366 /* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */
367 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT                     0
368 #define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK                      0x3FFFFF
369 
370 /* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */
371 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT                   0
372 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK                    0xFFFFFFFF
373 
374 /* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */
375 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT                   0
376 #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK                    0xFFFFFFFF
377 
378 /* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */
379 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT                  0
380 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK                   0xFFFFFFFF
381 
382 /* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */
383 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT                  0
384 #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK                   0x3FFFFF
385 
386 /* PSOC_GLOBAL_CONF_SW_ALL_RST */
387 #define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT                        0
388 #define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK                         0x1
389 
390 /* PSOC_GLOBAL_CONF_SOFT_RST */
391 #define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT                          0
392 #define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK                           0x1
393 
394 /* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */
395 #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT                    0
396 #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK                     0xFFFFFFFF
397 
398 /* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */
399 #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT                    0
400 #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK                     0x3FFFFF
401 
402 /* PSOC_GLOBAL_CONF_UNIT_RST_N */
403 #define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT                        0
404 #define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK                         0x1
405 
406 /* PSOC_GLOBAL_CONF_UNIT_RST_N_L */
407 #define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT                      0
408 #define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK                       0xFFFFFFFF
409 
410 /* PSOC_GLOBAL_CONF_UNIT_RST_N_H */
411 #define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT                      0
412 #define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK                       0x3FFFFF
413 
414 /* PSOC_GLOBAL_CONF_BTL_IMG */
415 #define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT                           0
416 #define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK                            0x1
417 
418 /* PSOC_GLOBAL_CONF_PRSTN_MASK */
419 #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT                        0
420 #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK                         0x1
421 
422 /* PSOC_GLOBAL_CONF_WD_MASK */
423 #define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT                           0
424 #define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK                            0x1
425 
426 /* PSOC_GLOBAL_CONF_RST_SRC */
427 #define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT                           0
428 #define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK                            0xF
429 
430 /* PSOC_GLOBAL_CONF_BOOT_STATE */
431 #define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT                        0
432 #define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK                         0x1
433 
434 /* PSOC_GLOBAL_CONF_PAD_1V8_CFG */
435 #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT                       0
436 #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK                        0x7F
437 
438 /* PSOC_GLOBAL_CONF_PAD_3V3_CFG */
439 #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT                       0
440 #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK                        0x7F
441 
442 /* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */
443 #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT                     0
444 #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK                      0x7
445 
446 /* PSOC_GLOBAL_CONF_BNK3V3_MS */
447 #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT                         0
448 #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK                          0x3
449 
450 /* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */
451 #define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT                      0
452 #define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK                       0xFF
453 
454 /* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */
455 #define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT              0
456 #define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK               0xFF
457 
458 /* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */
459 #define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT                  0
460 #define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK                   0x1F
461 
462 /* PSOC_GLOBAL_CONF_ADC_TPH_CS */
463 #define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT                        0
464 #define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK                         0xFF
465 
466 /* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */
467 #define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT                      0
468 #define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK                       0x1
469 
470 /* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */
471 #define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT                 0
472 #define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK                  0x1
473 
474 /* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */
475 #define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT                  0
476 #define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK                   0x1
477 
478 /* PSOC_GLOBAL_CONF_ADC_CFG_DATA */
479 #define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT                      0
480 #define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK                       0xFFFFFFFF
481 
482 /* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */
483 #define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT                      0
484 #define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK                       0xFF
485 
486 /* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */
487 #define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT                      0
488 #define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK                       0xFF
489 
490 /* PSOC_GLOBAL_CONF_PAD_DEFAULT */
491 #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT                       0
492 #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK                        0xF
493 
494 /* PSOC_GLOBAL_CONF_PAD_SEL */
495 #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT                           0
496 #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK                            0x3
497 
498 /* PSOC_GLOBAL_CONF_RST_CTRL */
499 #define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT                          0
500 #define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK                           0xFF
501 
502 #endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */
503